Patents Issued in April 26, 2007
  • Publication number: 20070090465
    Abstract: In a semiconductor device having a first MIS transistor on a semiconductor substrate, the first MIS transistor includes a p-type semiconductor layer, a first gate insulating film, a first gate electrode, a first sidewall insulting film including at least a first sidewall, an n-type extension diffusion layer, and an n-type impurity diffusion layer. The first sidewall is not formed at the side faces of the first gate electrode on the p-type semiconductor layer. An insulating film having tensile stress is formed on the semiconductor substrate so as to cover the first MIS transistor.
    Type: Application
    Filed: June 20, 2006
    Publication date: April 26, 2007
    Inventors: Ken Suzuki, Masafumi Tsutsui
  • Publication number: 20070090466
    Abstract: Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.
    Type: Application
    Filed: December 14, 2006
    Publication date: April 26, 2007
    Inventors: Min-Cheol Park, Sung-Hoi Hur
  • Publication number: 20070090467
    Abstract: A semiconductor structure and its method for fabrication include a first surface semiconductor layer of a first crystallographic orientation located upon a dielectric surface of a substrate. Located laterally separated upon the dielectric surface from the first surface semiconductor layer is a stack layer. The stack layer includes a buried semiconductor layer located nearer the dielectric surface and a second surface semiconductor layer of a second crystallographic orientation different from the first crystallographic orientation located over and not contacting the buried semiconductor layer. The semiconductor structure provides a pair of semiconductor surface regions of different crystallographic orientation. A particular embodiment may be fabricated utilizing a sequential laminating, patterning, selective stripping and selective epitaxial deposition method.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Huilong Zhu
  • Publication number: 20070090468
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
    Type: Application
    Filed: December 12, 2006
    Publication date: April 26, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru
  • Publication number: 20070090469
    Abstract: A semiconductor device according to an embodiment of the present invention includes a semiconductor chip. The semiconductor chip includes a semiconductor substrate, an interconnect layer, a back electrode (first working electrode), and a back dummy electrode (first dummy electrode). On the semiconductor substrate, the interconnect layer including an interconnect is provided. On a back surface of the semiconductor substrate, the back electrode is provided in electrical connection to the interconnect. On the back surface, also the back dummy electrode is provided, which is electrically insulated from the interconnect.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 26, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yoichiro Kurita
  • Publication number: 20070090470
    Abstract: A semiconductor device, for example a diode (200), having a pn junction (101) has an insulating material field shaping region (201) adjacent, and possibly bridging, the pn junction. The field shaping region (201) preferably has a high dielectric constant and is coupled via capacitive voltage coupling regions (204,205) to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction (101) and the device is non-conducting, a capacitive electric field, is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region (201), the electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region (208,209) and an increased reverse breakdown voltage of the device.
    Type: Application
    Filed: May 6, 2004
    Publication date: April 26, 2007
    Applicant: Koninklijke Philips Electronics N.V.
    Inventor: Anco Heringa
  • Publication number: 20070090471
    Abstract: A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eduard Cartier, Mathew Copel, Martin Frank, Evgeni Gousev, Paul Jamison, Rajarao Jammy, Barry Linder, Vijay Narayanan
  • Publication number: 20070090472
    Abstract: A semiconductor device having a silicon substrate, an element isolating film, an active region, a gate electrode provided via a gate insulating film, a diffusion layer provided on the active region on opposite sides of the gate electrode, an interlayer insulating film, and a plug filled in a hole formed on the interlayer insulating film, wherein the semiconductor device further has a contact forming region surrounded by the element isolating film, and a conductive layer formed on the contact forming region, the gate electrode extends so as to overlap with a portion of the contact forming region and is connected to the conductive layer at the overlapping portion, and the plug contacts the conductive layer at another portion of the contact forming region and is electrically connected to the gate electrode via the conductive layer.
    Type: Application
    Filed: October 24, 2006
    Publication date: April 26, 2007
    Inventor: Eiji Hasunuma
  • Publication number: 20070090473
    Abstract: A microelectromechanical component and to a method for the production thereof is disclosed. In one embodiment, the microelectromechanical component has a pressure-sensitive semiconductor chip, which is covered in its pressure-sensitive region by a rubber-elastic layer and is arranged in a cavity housing and covered by a rubber-elastic covering. This rubber-elastic covering has a greater thickness than the rubber-elastic layer on the pressure-sensitive region.
    Type: Application
    Filed: May 24, 2004
    Publication date: April 26, 2007
    Inventors: Thomas Engling, Martin Petz
  • Publication number: 20070090474
    Abstract: A MEMS device and method of fabrication including a plurality of structural tie bars for added structural integrity. The MEMS device includes an active layer and a substrate having an insulating material formed therebetween, first and second pluralities of stationary electrodes and a plurality of moveable electrodes in the active layer. A plurality of interconnects are electrically coupled to a second surface of each of the first and second pluralities of stationary electrodes. A plurality of anchors fixedly attach a first surface of each of the first and second pluralities of stationary electrodes to the substrate. A first structural tie bar couples a second surface of each of the first plurality of stationary electrodes and a second structural tie bar couples a second surface of each of the second plurality of stationary electrodes.
    Type: Application
    Filed: September 8, 2005
    Publication date: April 26, 2007
    Inventors: Gary Li, Bishnu Gogoi, Hemant Desai, Jonathan Hammond, Bernard Diem
  • Publication number: 20070090475
    Abstract: A system for conditioning a sensor die. The sensor die may have a sensor wafer and a substrate wafer anodically bonded together. The sensor die may have an inertial device such as an accelerometer or a gyroscope. The device has a scale factor that may change with a bowing of the sensor die. The die may be bonded at a high temperature to bumps on a surface of a package, but may develop a bow when cooled down to a temperature such as room temperature when the coefficients of thermal expansion of the die and the package are different. The bump material may enter a yield state. The package and the die may be subjected to a high gravity environment to reduce or reverse the bow. After the package is removed from the high gravity environment, the bow may return but at a smaller magnitude when subject to similar conditions.
    Type: Application
    Filed: October 5, 2005
    Publication date: April 26, 2007
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Drew Karnick, Peter LaFond
  • Publication number: 20070090476
    Abstract: A surface-emission cathode formed on an insulating surface having cantilevered, i.e. “undercut,” electrodes. Suitable insulating surfaces include negative electron affinity (NEA) insulators such as glass or diamond. The cathode can operate in a comprised vacuum (e.g., 10?7 Torr) with no bias on the electrodes and low vacuum electric fields (e.g., at least 10 V cm?1). Embodiments of the present invention are inexpensive to fabricate, requiring lithographic resolution of approximately 10 micrometers. These cathodes can be formed over large areas for use in lighting and displays and are suitable for satellite applications, such as cathodes for tethers, thrusters and space-charging neutralizers.
    Type: Application
    Filed: September 28, 2005
    Publication date: April 26, 2007
    Inventors: Michael Geis, Theodore Fedynyshyn, Sandra Deneault, Keith Krohn, Theodore Lyszczarz, Michael Marchant
  • Publication number: 20070090477
    Abstract: A theme is to prevent the generation of noise due to damage in a photodetecting portion in a mounting process in a photodiode array, a method of manufacturing the same, and a radiation detector. In a photodiode array, wherein a plurality of the photodiodes (4) are formed in array form on the surface at a side of the n-type silicon substrate (3) onto which light to be detected is made incident and the penetrating wirings (8), which pass through from the incidence surface side to the back surface side, are formed for the photodiodes (4), the photodiode array (1) is arranged with the spacer (6), having a predetermined planar pattern, provided at non-forming regions of the incidence surface side at which the photodiodes (4) are not formed.
    Type: Application
    Filed: March 10, 2004
    Publication date: April 26, 2007
    Inventor: Katsumi Shibayama
  • Publication number: 20070090478
    Abstract: An image sensor package structure is proposed, in which an image sensor is fixed on a substrate having metallization traces and an adhesion layer. Electric paths of the package structure are changed from the COG (chip on glass) process to the CIS (CMOS image sensor) process to improve electric characteristics. Moreover, spacers are formed at appropriate positions to prevent glue overflow from contaminating the sensing regions and solder balls. The proposed package structure can also shrink the package area to greatly enhance the yield and quality.
    Type: Application
    Filed: October 18, 2005
    Publication date: April 26, 2007
    Inventors: Po-Hung Chen, Mao-Jung Chen
  • Publication number: 20070090479
    Abstract: A system for controlling bond front propagation in wafer-scale packaging includes a first substrate, a second substrate, and a bonder pressure plate having protruded structures thereon to selectively establish at least one point of contact between the first and second substrates to initiate a bond front therebetween. The protruded structures are selectively configured to control the propagation of the bond front.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Inventors: Chien-Hua Chen, Kirby Sand, Bradley John
  • Publication number: 20070090480
    Abstract: The solid-state imaging device of the present invention includes: a plurality of photodetectors that are arranged in a two-dimensional matrix; a plurality of vertical transfer portions that transfer, in a vertical direction, signal electric charges which are read out from the respective photodetectors; a horizontal transfer portion that receives the signal electric charges transferred by the vertical transfer portions, and transfers the signal electric charges in a horizontal direction; a barrier region that is adjacent to the horizontal transfer portion, and allows an excess electric charge in the horizontal transfer portion to pass through; and a drain region that is adjacent to the barrier region and drains the excess electric charge which has passed through the barrier region; and bus lines that are disposed in parallel with the drain region, and apply control voltages to electrodes of the horizontal transfer portion.
    Type: Application
    Filed: June 26, 2006
    Publication date: April 26, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Toshihiro Kuriyama
  • Publication number: 20070090481
    Abstract: A SiC Schottky diode which includes a Schottky barrier formed on a silicon face 4H—SiC body.
    Type: Application
    Filed: October 16, 2006
    Publication date: April 26, 2007
    Inventor: Giovanni Richieri
  • Publication number: 20070090482
    Abstract: A high-breakdown voltage semiconductor switching device includes a resurf region of a second conductivity type; a base region of a first conductivity type formed to be adjacent to the resurf region; an emitter/source region of the second conductivity type formed in the base region to be spaced from the resurf region; a gate electrode formed to cover a portion of the emitter/source region and a portion of the resurf region; a drain region of the second conductivity type formed in the resurf region to be spaced from the base region; and a collector region of the first conductivity type formed in the resurf region to be spaced from the base region. Furthermore, it includes an electrode connected to the collector region and the drain region and an electrode connected to the base region and the emitter/source region.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 26, 2007
    Inventors: Saichirou Kaneko, Tetsuji Yamashita, Toshihiko Uno
  • Publication number: 20070090483
    Abstract: Systems, methods and devices relating to actuatably movable machines and with methods of using and manufacturing the same.
    Type: Application
    Filed: October 25, 2005
    Publication date: April 26, 2007
    Applicant: The Charles Stark Draper Laboratory, Inc.
    Inventors: H. Charles Tapalian, Jason Langseth
  • Publication number: 20070090484
    Abstract: An integrated circuit stress control system is provided. A gate is formed on a substrate and a channel is formed in the substrate. A source/drain is formed around the gate. A shallow trench isolation is formed in the substrate, the shallow trench isolation producing strain on the channel. A stress suppressing feature is formed in the substrate.
    Type: Application
    Filed: August 25, 2005
    Publication date: April 26, 2007
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Jae Gon Lee, Cher Sian Chua, Chew Hoe Ang, Liang-Choo Hsia
  • Publication number: 20070090485
    Abstract: Provided is a semiconductor device including: a p-type silicon substrate; a p-well which is formed in the silicon substrate, and which has a planar shape with no hole; an n-well integrally formed, in the silicon substrate, in a planar shape obtained by inverting the pattern of the p-well; a first and a second gate electrodes formed respectively on the two wells; an n-type source/drain region formed in the p-well beside the first gate electrode; a p-type impurity diffusion region for well contact which is formed in the p-well, and to which a first substrate bias voltage is applied; a p-type source/drain region formed in the n-well beside the second gate electrode; and an n-type impurity diffusion region for well contact which is formed in the n-well, and to which a second substrate bias voltage is applied.
    Type: Application
    Filed: February 27, 2006
    Publication date: April 26, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Yoshihiro Takao
  • Publication number: 20070090486
    Abstract: The fuse comprises an interconnection part 14 luding a silicon layer; a contact part 20b connected one end of the interconnection part 14; and a contact part 20aconnected to the other end of the interconnection part 14 and containing a metal material. A current is flowed from the contact part 20bto the contact part 20a to migrate the metal material of the contact part 20a to the silicon layer to thereby change the contact resistance between the interconnection part 14 and the contact part 20a.
    Type: Application
    Filed: January 23, 2006
    Publication date: April 26, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Satoshi Otsuka, Toyoji Sawada, Masato Suga, Jun Nagayama, Motonobu Sato, Takashi Suzuki
  • Publication number: 20070090487
    Abstract: A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Katherina Babich, Bruce Doris, David Medeiros, Devendra Sadana
  • Publication number: 20070090488
    Abstract: A high-efficiency matrix-type LED device comprises an epitaxial wafer on which a plurality of independently insulated LEDs are formed by a method of manufacturing integrated circuits; and a conducting line mounted on each one of the LEDs by an evaporation method for forming a large-sized matrix-type LED unit capable of increasing brightness, simplifying manufacturing procedure, and saving manufacturing cost effectively. In addition, a sub-mount having a two-way Zener diode embedded therein is applied to the matrix-type LED unit. By mounting the matrix-type LED unit on the sub-mount, the two-way Zener diode can protect the LEDs against damage from electrostatic discharge (ESD) so as to increase lifetime of LEDs.
    Type: Application
    Filed: October 24, 2005
    Publication date: April 26, 2007
    Inventors: Chi-Jen Teng, Wen-Long Chou, Kuo-Jui Huang
  • Publication number: 20070090489
    Abstract: A method and apparatus for growing nanostructures is presented. A growth substrate including at least one reaction site is provided as is a device disposed proximate the growth substrate. Energy is provided to the reaction site and a reaction species is introduced to the growth substrate. This results in a nanostructure growing from the reaction site wherein the growth process of the nanostructure is controlled by providing a force to the device.
    Type: Application
    Filed: October 25, 2006
    Publication date: April 26, 2007
    Inventors: Anastasios Hart, Alexander Slocum
  • Publication number: 20070090490
    Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.
    Type: Application
    Filed: June 20, 2006
    Publication date: April 26, 2007
    Applicant: Industrial Technology Research Institute
    Inventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
  • Publication number: 20070090491
    Abstract: A semiconductor structure with silicon on insulator is disclosed in this present invention. The semiconductor structure at least comprises a first substrate and a second substrate. The crystal orientation of the first substrate is in a first orientation favorable for dicing the semiconductor structure into chips, and the crystal orientation of the second substrate is in a second crystal orientation favorable to the electron carrier mobility. Hence, this invention can efficiently improve the yield of the semiconductor device by reducing the fracture during dicing. Additionally, this invention can improve the performance of the semiconductor device by raising the electron mobility in the substrate.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 26, 2007
    Inventors: Jiunn-Ren Hwang, Wei-Tsun Shiau
  • Publication number: 20070090492
    Abstract: A termination region of a semiconductor die is provided, which includes one or more field rings arranged in the termination region, one or more metal field plates, and an insulation layer disposed to prevent direct electrical contact between the field rings and the field plate such that the at least one field ring is capacitively coupled with the at least one field plate. Such a termination region may also include a polysilicon plate capacitively coupled with a diffusion region laterally spaced from the field rings, the polysilicon plate being located at an outer surface or directly under a passivation layer at an outer surface of the die. The termination region may also include floating field rings. The insulation layer may be a field oxide layer.
    Type: Application
    Filed: October 25, 2006
    Publication date: April 26, 2007
    Inventor: Lawrence Kulinsky
  • Publication number: 20070090493
    Abstract: Silicon oxide (210) is grown on a silicon region (130). At least a portion (210N) of the silicon oxide (210) adjacent to the silicon region (130) is nitrided. Then some of the silicon oxide (210) is removed, leaving the nitrided portion (210N). Additional silicon oxide is thermally grown on the silicon region (130) under the nitrided silicon oxide portion (210N). This additional silicon oxide and the nitrided portion (210N) form a silicon oxide layer (140) having a high nitrogen concentration adjacent to a surface opposite from the silicon region (130) and a low nitrogen concentration elsewhere. Another nitridation step increases the nitrogen concentration in the silicon oxide layer (140) adjacent to the silicon region, providing a double peak nitrogen profile.
    Type: Application
    Filed: October 11, 2005
    Publication date: April 26, 2007
    Inventors: Zhong Dong, Chiliang Chen, Chung Leung
  • Publication number: 20070090494
    Abstract: There is provided an insulation-coated conductor including a conductive member that has a comer potion and a non-comer portion, and an insulating resin coated around the conductive member.
    Type: Application
    Filed: October 23, 2006
    Publication date: April 26, 2007
    Applicant: Suncall Corporation
    Inventors: Motoaki Kimura, Iwao Hatakeyama, Takao Murakami
  • Publication number: 20070090495
    Abstract: A thin package system with external terminals and a leadframe is provided. An external bond finger defining template is provided and used to form external bond fingers on the leadframe. A die is provided and attached to the leadframe. At least portions of the die and the external bond fingers are encapsulated, and the leadframe is removed.
    Type: Application
    Filed: October 22, 2005
    Publication date: April 26, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Youngcheol Kim, Myung Kil Lee, Gwang Kim, Koo Hong Lee
  • Publication number: 20070090496
    Abstract: An electronic module includes a semiconductor power switch and a semiconductor diode. The lower side of the semiconductor power switch includes an output contact mounted on a die pad of a leadframe, and the upper side of the semiconductor power switch includes a control contact and an input contact. The anode contact of the semiconductor diode is disposed on and electrically connected to the input contact of the semiconductor power switch. The cathode contact of the diode is electrically connected with the output contact of the power semiconductor switch.
    Type: Application
    Filed: October 25, 2005
    Publication date: April 26, 2007
    Inventor: Ralf Otremba
  • Publication number: 20070090497
    Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (402) and a plurality of lead segments (403). Covering the base metal are, consecutively, a nickel layer (301) on the base metal, and a continuous layer of noble metal, which consists of a gold layer (201) on the nickel layer, and an outermost palladium layer (202) on the gold layer. A semiconductor chip (410) is attached to the chip mount pad and conductive connections (412) span from the chip to the lead segments. Polymeric encapsulation compound (420) covers the chip, the connections, and portions of the lead segments. In QFN devices with straight sides (501), the compound forms a surface (421) coplanar with the outermost palladium layer (202) on the un-encapsulated leadframe surfaces.
    Type: Application
    Filed: November 14, 2005
    Publication date: April 26, 2007
    Inventor: Donald Abbott
  • Publication number: 20070090498
    Abstract: The stack type semiconductor package module includes a lower semiconductor package having a main substrate, a chip mounted on the main substrate and electrically connected to the main substrate through a wire. An epoxy molding compound (EMC) is provided on the main substrate to cover the chip and the wire. Contact holes are formed in the EMC. A sub-substrate having protrusions coated with solder is connected to the lower semiconductor package by inserting the solder coated protrusions into the contact holes. Heat is applied to the protrusions, and the molten solder solidifies inside the contact holes. An upper semiconductor package having substantially identical structure as the lower package is then stacked on the sub-substrate.
    Type: Application
    Filed: December 15, 2005
    Publication date: April 26, 2007
    Inventor: Dae Lee
  • Publication number: 20070090499
    Abstract: In a semiconductor package including at least one plate-like mount, a semiconductor chip has at least one electrode formed on a top surface thereof, and is mounted on the plate-like mount such that a bottom surface of the semiconductor chip is in contact with the plate-like mount. The semiconductor package also includes at least one lead element having an outer portion arranged to be flush with the plate-like mount, and an inner portion deformed and shaped to overhang the semiconductor chip such that an inner end of the lead element is spaced apart from the top surface of the semiconductor chip. The semiconductor package further includes a bonding-wire element bonded at ends thereof to the electrode of the semiconductor chip and the inner end of the lead element, an enveloper sealing and encapsulating the plate-like mount, the semiconductor chip, the inner portion of the lead element, and the bonding-wire element.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 26, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takekazu Tanaka
  • Publication number: 20070090500
    Abstract: A housed DRAM chip includes a DRAM chip and a housing substrate. The DRAM chip is arranged on the housing substrate such that shorter conductive connections between the chip pads of the DRAM chip and external housing connections can be achieved for high data transmission speeds.
    Type: Application
    Filed: October 16, 2006
    Publication date: April 26, 2007
    Inventor: Peter Poechmueller
  • Publication number: 20070090501
    Abstract: A lead frame base is coated with a four-layer plating. The four-layer plating includes an underlayer plating (Ni), a palladium plating, a silver plating and a gold plating arranged in this order from bottom to top.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 26, 2007
    Inventors: Seishi Oida, Takahiro Nakano, Yoshito Miyahara, Takashi Yoshie, Harunobu Satou, Kouichi Kadosaki, Kazumitsu Seki
  • Publication number: 20070090502
    Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes a heat spreader cap defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. A planar rim portion of the cap that surrounds the cavity is coupled to the leadframe. The cap and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Applicant: Broadcom Corporation
    Inventors: Sam Zhao, Reza-ur Khan
  • Publication number: 20070090503
    Abstract: The present invention relates to a semiconductor package having an optical device and the method of making the same. The semiconductor package comprises: a transparent substrate, a chip, an optical device and a carrier substrate. The transparent substrate has a plurality of first contacts and second contacts, wherein the first contacts are electrically connected to the second contacts. The chip is connected to the transparent substrate and forms a gap therebetween. The chip has a plurality of third contacts that are electrically connected to the first contacts. The optical device is disposed in the gap. The carrier substrate has a receiving space and a plurality of fourth contacts, wherein the receiving space accommodates the chip and the optical device, and the fourth contacts are electrically connected to the second contacts of the transparent substrate. Therefore, no connecting wires are needed and the step of wire bonding is omitted.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 26, 2007
    Inventor: Cheng-Wei Huang
  • Publication number: 20070090504
    Abstract: The present invention relates to an optical sensor chip package in a cavity of forming frame thereof and has a gap between protection layer and optical sensor chip. The optical sensor chip avoids accepting the pressure from protection layer that damage the reliability between pads and metallic traces when protection layer lay on the forming frame. It improves drawbacks of the glue pass trough the gap between optical sensor chip and pads into the optical sensor area of optical sensor chip. It improves the high process yield and reduces the height of optical sensor chip package to achieve lightly and thinly.
    Type: Application
    Filed: September 14, 2005
    Publication date: April 26, 2007
    Inventors: Po-Hung Chen, Chin-Cheng Lo, Mao-Jung Chen
  • Publication number: 20070090505
    Abstract: An apparatus for manufacturing a package packing a solid-state imaging device is provided, the package having: a package container fixing the solid-state imaging device therein; and an IR-coated cover glass hermetically sealing the solid-state imaging device in the package container. The apparatus has an ultraviolet radiation unit that radiates an ultraviolet ray to the package in which the IR-coated cover glass are bonded to the package container with an ultraviolet-curing resin, the ultraviolet radiation unit being disposed in a position to radiate the ultraviolet ray in a direction inclining relative to a surface of the cover glass.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 26, 2007
    Inventor: Masato Kikuchi
  • Publication number: 20070090506
    Abstract: In one aspect, the present invention provides interposers that can mechanically, electrically, and thermally interconnect first and second microelectronic components. An interposer in accordance with the present invention includes a substrate, preferably flexible, having first and second oppositely facing surfaces. Such interposers also include an array of links traversing from the first surface of the substrate to the second surface of the substrate. In accordance with the present invention, each link preferably comprises a buried portion positioned between the first and second surfaces of the substrate. In other aspects of the present invention, microelectronic assemblies having first and second microelectronic components interconnected by an interposer and methods of interconnecting such components are provided.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Inventor: Lance Sundstrom
  • Publication number: 20070090507
    Abstract: A multi-chip package structure includes a first substrate, a first chip, a sub-package, and a first molding compound. The first substrate has a first surface and a second surface. The first chip is attached to the first surface of the first substrate by flip-chip bonding so as to reduce a step of wire bonding and reduce the total height of the package structure. The sub-package includes a second substrate, a second chip, and a second molding compound. The second substrate has a first surface and a second surface. The second substrate is a flexible substrate and is directly connected to the first surface of the first substrate so as to reduce another step of wire bonding.
    Type: Application
    Filed: January 17, 2006
    Publication date: April 26, 2007
    Inventors: Chian-Chi Lin, Cheng-Yin Lee
  • Publication number: 20070090508
    Abstract: The present invention relates to a multi-chip package structure, which comprises a first substrate, a first chip, a sub-package structure, a plurality of first solder balls, and a first molding compound. The first substrate has a first surface and a second surface. The first chip is electrically connected to the first surface of the first substrate. The sub-package structure comprises a second substrate, a second chip, and a second molding compound. The first solder balls are disposed between the first substrate and the second substrate and are used for connecting the first surface of the first substrate and the second surface of the second substrate so as to omit a step of wire bonding.
    Type: Application
    Filed: September 14, 2006
    Publication date: April 26, 2007
    Inventors: Chian-Chi Lin, Cheng-Yin Lee
  • Publication number: 20070090509
    Abstract: In one embodiment, a shielding includes one or more contact elements configured to electrically contact one or more electrical elements of an integrated circuit package. The one or more electrical elements may be located on a top surface of the package. A bottom surface of the package may be coupled to a circuit board. The one or more contact elements provide a path for a ground through the one or more electrical elements. For example, the shielding may be coupled to a ground on the circuit board. This may provide shielding of EMI.
    Type: Application
    Filed: October 12, 2006
    Publication date: April 26, 2007
    Applicant: OQO, Inc.
    Inventors: Michael Furlotti, Jonathan Betts-LaCroix
  • Publication number: 20070090510
    Abstract: Silicon substrates are applied to the package structure of solid-state lighting devices. Wet etching is performed to both top and bottom surfaces of the silicon substrate to form reflecting cavity and electrode access holes. Materials of the reflecting layer and electrode can be different from each other whose preferred materials can be chosen in accordance with a correspondent function. Formation of the electrode can be patterned by an etching method or a lift-off method.
    Type: Application
    Filed: October 16, 2006
    Publication date: April 26, 2007
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY INC.
    Inventors: Wen Tseng, Lung Chen
  • Publication number: 20070090511
    Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively.
    Type: Application
    Filed: August 31, 2006
    Publication date: April 26, 2007
    Inventors: William Borland, Saul Ferguson
  • Publication number: 20070090512
    Abstract: A signal transmission line used in a printed circuit board (PCB), the signal transmission line comprises a driving terminal for driving a signal, a contact portion, the signal line connected with the driving terminal and the contact portion to transmit the signal wherein a length of the signal line is so arranged that a time for the signal transmitted from the driving terminal to the contact portion is not less than half of a time for the transmitted signal to reach a receiving terminal.
    Type: Application
    Filed: July 21, 2006
    Publication date: April 26, 2007
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHENG-HONG LIU, SHOU-KUO HSU, YU-CHANG PAI
  • Publication number: 20070090513
    Abstract: A power module fabrication method and structure thereof is disclosed.
    Type: Application
    Filed: March 9, 2006
    Publication date: April 26, 2007
    Inventors: Chin Kuo, Yi Hsieh
  • Publication number: 20070090514
    Abstract: A semiconductor structure (100) includes a substrate (110) having a first surface (111) with a mold lock feature (101). The semiconductor structure also includes a semiconductor chip (120) located over the first surface of the substrate. The semiconductor structure further includes an electrical isolator structure (340) located over the first surface of the substrate. The electrical isolator structure includes an electrical lead (341, 342) and an electrically insulative element (343) molded to the electrical lead. An optional portion (444) of the electrical isolator structure is located in the mold lock feature. The semiconductor structure additionally includes an adhesive element (450) located between and coupling the electrical isolator structure and the first surface of the substrate.
    Type: Application
    Filed: October 24, 2005
    Publication date: April 26, 2007
    Inventors: Brian Condie, Lakshminarayan Viswanathan, Richard Wetz