Abstract: First and second transmission lines and are connected to each other in series. A first terminator is connected to the first transmission line in parallel, and is provided externally of a semiconductor device. A second terminator is connected to the second transmission line in parallel, and is provided inside the semiconductor device. The values of the first and second terminator are adjusted so that the combined resistance value of first and second terminator and the second transmission line matches with the impedance of the first transmission line. Impedance matching of the entire transmission line can be achieved with this simple construction, thus, a stable, high quality signal can be transmitted.

Abstract: The circuit arrangement comprises a driver stage and a control circuit coupled to the control input of a switching transistor. The driver stage provides a switching voltage for the operation of the switching transistor, and the control circuit provides a shaping of the switching voltage in the sense of delaying the switching through of the switching transistor. The control circuit comprises in particular a control transistor, which is coupled a control input via a high pass filter to the output of the driver stage and with an current input to the control input of the switching transistor. The switching transistor is for example a MOSFET being used for switching on and off a capacitive load.

Abstract: A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of routing lines, and the input of each of the plurality of buffers is connected to one of a first set of programmable switches, one of a second set programmable switches, one of a third set of programmable switches, and one of a fourth set of programmable switches, and each one of the first set of programmable switches is connected to a separate one of the second set of programmable switches and a separate one of the second set of programmable switches, none of which are connected to an input of a same one of the plurality of buffers. Each one of the first set of programmable switches is connected to a separate routing line for transmitting a signal in a separate direction of a second set of routing lines.

Abstract: A semiconductor device has a plurality of universal logic cells, a power supply line, a ground line, a first interconnection and a second interconnection. Each universal logic cell includes first to seventh nodes formed in a top layer of common interconnection layers which are allocated to the universal logic cells. The first interconnection connects the third node, the fourth node and the fifth node, and the second interconnection connects the power supply line and the first node. Or, the first interconnection connects the second node, the sixth node and the seventh node, and the second interconnection connects the ground line and the first node. The first and second interconnections are formed in a customize interconnection layer provided on the common interconnection layers.

Abstract: A method for analyzing a structured integrated circuit is provided. The method includes identifying a random logic region of the structured integrated circuit. The structured integrated circuit includes a predefined layout for transistors and basic interconnections to define a set of logic elements. A tile array of basic logic cells is integrated throughout the identified random logic region. The tile array of basic logic cells is defined from the set of logic elements of the structured integrated circuit. The tile array of basic cells enables communication of testing signals along the tile array of basic logic cells in a first and a second direction. The first and second directions are different from one another. The testing signals help to identify one or more errors in the tile array of basic logic cells. The array format assists in diagnosing and curing defects in the tile array of basic logic cells. The errors are pinpointed to a basic logic cell at the intersection of the first and second direction.

Abstract: A level shifting device having an input side operating at a first voltage level, an output side operating at a second voltage level and a level shifting circuit which connects the input and output sides. The input circuit receives an input signal referenced to the first voltage level and provides separate outputs corresponding to transitions of the input signal. The level shifting circuit includes MOSFETS having the gates connected respectively to each output of the input circuit; and the source-drain path coupled between the second voltage and a reference for the first voltage. The output side has a differential topology, and includes a first circuit which samples signals corresponding to the transitions of the input signal, holds the sample between transitions, and an output circuit which receives the held sample signal in differential form and converts it to single-ended form for use by other circuits. The circuit also blocks input signals when common mode transients are present.

Abstract: An electronic data processing circuit uses current mode signalling on a communication conductor, wherein a receiver supplies current to the communication conductor to try and keep a voltage on the conductor constant and measures the current that is needed to do so. A transition coding circuit is coupled between a data source circuit and the communication conductor, for driving the communication conductor in a first state in pulses in response to transitions in the logic signal and in a second state outside the pulses. The level that is used for indicating no change is selected so the current that needs to be supplied by the receiver is smaller when no change is signalled than when a change is signalled. Preferably only a nearly zero quiescent current is needed when there is no change.

Abstract: A line driver for off-chip communication comprises multiple parallel stages each with separate inputs. The parallel stages each have a controlled impedance when driving the line driver output node to a logic zero or a logic one. A line driver controller is used to select what combination of driver stages are used to drive the output node based on whether the output node is transitioning between logic state or is remaining static. During power-up, a test program tries different combinations of driver stages for particular symbol patterns and determines what is the optimal ratio between line driver resistance for the dynamic and static cases and stores the optimum combination. The data stream feeding the line driver is sampled in real time to determine the transition states and selects the optimal number of driver stages for each case.

Abstract: In order to protect semiconductor switching-devices employed in an H bridge circuit against an over-voltage without using a special protection circuit, a control circuit outputs a control signal to a driving circuit for driving the H bridge circuit in order to turn off FETs serving as the semiconductor switching-devices when an over-voltage detection circuit detects the over-voltage applied to the H bridge circuit.

Abstract: A multi-level shifter circuit is provided for a flat panel source driver, the multi-level shifter circuit having a voltage dropper for dropping a source voltage and outputting a dropped source voltage, and a plurality of level shifters to which the dropped source voltage is applied for receiving data bits and converting the level of the data, where the multi-level shifter circuit has a small chip size and consumes a small amount of current.

Abstract: A line driver (3) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors (14, 15) for generating transmission impulses as a function of the data to be transmitted, whereby the transmission impulses are preferably output via cascode transistors (16, 17), each with the differential pair transistors (14, 15) forming a cascode circuit, onto the data transmission line (8, 9) connected to the line driver (3).

Abstract: A dynamic logic register including a complementary pair of evaluation devices, delayed inversion logic, a dynamic evaluator, latching logic, and a keeper circuit coupled to the output. The evaluation devices are responsive to a clock signal and provide a pre-charged node and an evaluation node. The delayed inversion logic outputs a complete signal that is a delayed and inverted version of the clock signal. The dynamic evaluator, coupled between the pre-charged and evaluation nodes, evaluates a logic function based on a data signal during an evaluation period between operative edges of the clock and complete signals. The latching logic enables the state of an output node to be determined by the state of the pre-charged node during the evaluation period and otherwise clamps the pre-charged node to prevent perturbations of the data signal from propagating to the output node.

Abstract: A state-holding circuit having improved stability at high temperatures includes a bi-stable circuit capable of assuming one of two reversible and stable states. The bi-stable circuit comprises a plurality of logic components (e.g., transistors) arranged into two sides. Because each of the logic components has a leakage current and/or resistance that varies significantly as a function of temperature, one or more stabilization components, such as transistors or other devices, may be connected to a side of the bi-stable circuit to balance the leakage currents and/or resistances of each side. In certain embodiments, the sole function of the stabilization components is to balance the leakage currents and/or resistances of each side.

Abstract: A limiting amplifier (LIA), used for example in high speed optical communication systems, includes a loss of signal (LOS) feature that may provide improved optical receiver performance and includes wide range user-programmable thresholds for generating analog loss of signal (LOS) alarms. In particular, multiple sampling points within the limiting amplifier may be used. These samples may be differentially amplified with weighted gains and then combined and compared to a threshold value to generate an LOS alarm signal.

Abstract: A below-ground sensor interface amplifier is powered by no negative supply voltage, but the amplifier nevertheless senses an input voltage signal below ground potential. The amplifier outputs an output voltage signal that varies proportionately to the input voltage. For an input voltage beginning below ground potential and increasing past ground potential, the amplifier outputs an output voltage that remains between ground potential and a supply voltage. The output voltage increases proportionately to the increase of the input voltage. As the input voltage increases, a gate voltage on a first transistor begins to increase starting at the input voltage at which a second transistor is forced to turn on. The amplifier senses input voltages more than one threshold voltage below ground potential without using a below-ground supply voltage. The gain of the amplifier, as well as the lower limit and the size of the amplifier's voltage operating range are programmable.

Abstract: Aspects of a method and system for a linear regulator with high bandwidth, PSRR, and a wide range of output current are provided. A method for isolating voltages in a circuit may comprise applying a reference voltage to an isolation resistor based on a supply voltage. An internal voltage at a reference point may be determined based on the applied reference voltage, and a maximum and/or minimum voltage may be determined based on the internal voltage. A plurality of output transistor devices may be controlled based on either the maximum voltage or minimum voltage. The reference voltage may be modified based on controlling the plurality of output transistor devices. By turning ON and OFF the output transistor devices, a much wider operating range is facilitated.

Abstract: A signal transmitting apparatus being used in a network device includes a voltage-controlled current source for outputting a current signal according to an input digital signal; a line driver for outputting a voltage signal according to the current signal; at least one impedance-matching unit, which is coupled to the line driver, for impedance-matching at the output of the line driver; and a first correction unit, which is coupled to the voltage-controlled current source, for outputting a first correction signal to adjust the current signal outputted from the voltage-controlled current source.

Abstract: A double frequency signal generator to which a synchronization signal having a duty cycle of 1% to 999% is inputted. The synchronization signal is used for triggering of a switching component at positive and negative edges to generate a triangular-wave signal. An average of voltages of the triangular-wave signal is acquired and compared with the triangular-wave signal at a comparator to generate a square-wave having a duty cycle of 50%. Then, the square-wave signal is used for triggering at positive and negative edges to generate a double frequency signal. As such, the high cost issue and the limitation of a square-wave input signal occurred in the prior art may be efficiently overcome.

Abstract: In a power-up signal generating device, a power-up signal is activated at a certain level of the power supply voltage VDD by adjusting the turn-on resistance value of the MOS transistor so that the chip reliability can be improved. The power-up signal generating device comprises a reference voltage generating unit, a bias level adjusting unit, a bias signal generating unit and a signal outputting unit. The reference voltage generating unit generates a reference voltage. The bias level adjusting unit receives the reference voltage as an input for controlling a voltage level of a bias signal in a constant level. The bias signal generating unit generates the bias signal under control of the bias level adjusting unit. The signal outputting unit outputs a power-up signal depending on the voltage level of the bias signal.

Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

Abstract: A circuit (e.g., a receiver) has a delay loop (e.g., a voltage-controlled delay loop) and (at least) two phase detectors (PDs), where each PD compares a different pair of clock signals generated by the delay loop. The outputs of the different PDs are then used to generate a control signal for adjusting the delays provided by the delay elements in the delay loop. In one implementation, the control signal indicates that a delay adjustment should be made only if both PDs agree on that adjustment. This multiple-PD technique can reduce jitter that could otherwise result from a non-50% duty cycle in the reference clock signal used by the delay loop to generate its multiple clock signals.

Abstract: A digital-control phase-composing circuit system has a phase-composing circuit which is supplied with two input clock signals having a phase difference therebetween and a control signal, and which composes an output clock signal having a phase between the phases of the two input clock signals on the basis of weighting through the control signal, a binary comparison circuit which compares the phase of the output clock signal to the phase of a reference clock signal, a first up/down counter which increments or decrements a first count value on the basis of the result of comparison made by the binary phase comparison circuit, outputs the most significant bit of the first count value, and outputs a clock pulse when a carry or a borrow occurs in the first count value, and a second up/down counter which operates on the basis of the clock pulse as an operating clock, increments or decrements a second count value on the basis of the most significant bit of the first count value, and outputs the second count value as

Abstract: A precision PLL based transceiver having a single precision SAW or crystal resonator is configured to lock onto multiple different input frequencies and output generated clocks at the multiple different frequencies. The input reference frequency may be higher or lower than the resonator frequency. A fraction of two whole numbers describing a ratio of the resonator frequency to a given input frequency reference is first obtained. One of the numerator or denominator in the fraction is used to set the divide value of a first frequency divider coupling a VFO based on the resonator to a feedback input on a PFD. The other of the numerator or denominator is used to set a second frequency divider coupling the input frequency reference signal to the PFD. A first frequency multiplier is given a multiplication factor matching the divide value of the second frequency divider, and used to couple the output of the first frequency divider to the output of the PLL.

Abstract: A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.

Abstract: Delay locked loop circuits are provided that include a delay locked loop that generates a delay locked loop output signal and a jitter suppressor. The jitter suppressor may comprise a delay circuit that receives the delay locked loop output signal and generates one or more delayed versions of the delay locked loop output signal and a phase interpolator that receives the delay locked loop output signal and the one or more delayed versions of the delay locked loop output signal. In certain embodiments of the present invention, the delay circuit may comprise a plurality of serially connected delay cells. Each of these delay cells may delay signals input thereto for at time equal to one clock period of an external clock signal that is input to the delay locked loop.

Abstract: A method of operating a delay locked loop is comprised of producing a first output signal in response to a first lock point. A new lock point is measured, or otherwise determined, while continuing to produce the first output signal. Thereafter, a second output signal is produced in response to the new lock point. The new lock point data may be loaded into the delay locked loop while the delay locked loop continues to produce the first output signal. The delay locked loop switches from producing the first output signal, responsive to a first lock point, to producing the second output signal, responsive to the new lock point, in response to various conditions such as control signals, e.g. an auto refresh command, a precharge all command, a mode register load command, a power down entry, a power down exit (among others), in response to a timer, e.g., an internal timer (among others), or in response to environmental condition signals, e.g., a temperature sensor output signal (among others).

Abstract: Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector and an up down counter that provides a main control signal to adjust the delay by the main variable delay circuit. When the DLL circuit is locked, an arithmetic logic unit (ALU) produces a processed control signal based on the main control signal, an ALU control signal and an offset control signal, and the processed control signal is provided to the smaller variable delay circuit. By adjusting the ALU control and offset control signals, the phase shift introduced on the DLL control signal by the smaller variable delay circuit can be adjusted. In another embodiment of the invention, a second up down counter is used in place of an ALU for providing a dynamically adjustable phase shift in accordance with the principles of the present invention.

Abstract: The present invention relates to a semiconductor circuit; and, more particularly, to a duty cycle correction circuit (hereinafter referred to as “DCC”). Furthermore, the present invention relates to an open-loop digital DCC. The duty cycle correction circuit according to the present invention includes: a delayer for delaying an input clock signal and for generating a plurality of delayed clock; a phase comparator for comparing the input clock signal with the plurality of delayed clock signals; a multiplexer for selecting one out of the delayed clock signals in response to an output signal of the phase comparator and for inverting the selected delay clock signals; and a phase combiner for combining the clock signal from the multiplexer and the input clock signal. Accordingly, the digital DCC according to the present invention is of an open loop without any DLL, the duty correction can be made within five clock periods after power-up.

Abstract: A radiation hardened latch is presented. The radiation hardened latch uses two redundant inverter paths to duplicate an input signal. The duplicated inverter paths are coupled with a radiation hardened inverter that will only produce an inverted signal if both input signals have equivalent voltage levels. The radiation hardened inverter and its output signal produce a radiation hardened node that drives either one of the duplicated inverter paths back to an appropriate voltage level in the event of an SET. Because, the radiation hardened node and duplicated inverter paths are isolated, the latch may be optimized for factors such as signal speed and driving strength. These factors may be optimized without affecting radiation hardness. The radiation hardened latch may also be used to build more complex circuits such as a flip-flop.

Abstract: A delay locked circuit has multiple paths for receiving an external signal. One path measures a timing of the external signal during a measurement. Another path generates an internal signal based on the external signal. The delay locked circuit periodically performs the measurement to keep the external and internal signals synchronized. The time interval between one measurement and the next measurement is unequal to the cycle time of the external signal.

Abstract: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal.

Abstract: The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are different. Level shift circuit 10 that outputs the output signal of the high voltage source as a response to the input signal of the low voltage source has the following attribute: When feeding of the low voltage source is delayed with respect to feeding of the high voltage source, on the basis of the high voltage source, power-on-reset circuit 20 generates power-on-reset signal PWR. During the period before the input signal of the low voltage source is fed as a response to power-on-reset PWR, latch circuit 30 initializes the level shift circuit, and holds its output OUT at the low level.

Abstract: A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL1) either couples the pad and the reference signal (Vbg) together or isolates the pad and the reference signal (Vbg) from each other. The test-mode circuit includes at least one NMOS transistor (MN1) and a PMOS transistor (MP1) connected in series between the pad and the reference signal (Vbg). During normal operation, the NMOS transistor (MN1) isolates the reference signal (Vbg) from the pad, and the PMOS transistor (MP1) compensates for voltage undershoot conditions at the pad.

Abstract: An apparatus for providing over current protection for a digital pulse width modulator is disclosed. The apparatus includes first logic circuitry for generating a primary interrupt indicating that a detected output current is greater than a threshold current. Second logic circuitry blanks out current spikes in the output current occurring on a leading pulse edge of at least one of a plurality of outputs of the digital pulse-width modulator.

Abstract: CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of two multiplexing methods. The first method places switches on the data inputs while the second places the switches on the analog bias voltages inherent to a current controlled inverter.

Abstract: A half-bridge circuit, in which an input signal that is applied between two input terminals can be picked up at a phase output comprises two switching transistors controlled by a respective control signal that is applied between a control electrode and an auxiliary electrode and two diodes. The first input terminal is connected to the first electrode of the first switching transistor and to the first diode's cathode. A second electrode of the first switching transistor is connected to the first diode's anode by means of the phase output, via a line, to a first electrode of the second switching transistor and to a cathode of the second diode. A second electrode of the second switching transistor is connected to an anode of the second diode and to the second input terminal. The auxiliary electrode of the first switching transistor is connected to the line of the phase output.

Abstract: Methods and systems for measuring temperature are described. A voltage source supplies a voltage. A current source supplies an amount of current that is controlled using a digital input signal. A diode is coupled to the current source. A comparator has a first input coupled to the voltage source and a second input coupled to a node between the current source and the diode. The digital input signal is changed to a value that causes an output of the comparator to change state. A value of the digital input signal is determined for each of two voltages. The values of the digital input signal and the two voltage values (or the difference between the two voltages) are used as inputs to a temperature calculation.

Abstract: To restrain variations in the power supply potential caused among a plurality of integrated circuits as well as the voltage drop of the power supply potential that has reached each block. A semiconductor integrated circuit device is provided with integrated circuits as blocks 2–4, power supply wires 11–13 for supplying power supply potential VDD or ground potential GND from feeder terminals 5–10 to the blocks 2–4, a switch circuit 14 for connecting the power supply wire 11 and the power supply wire 12, and a switch circuit 15 for connecting the power supply wire 11 and the power supply wire 13. When the switch circuit 15 is turned on, for example, the power supply wire 11 and the power supply wire 13 of the block 2 and the block 4 are connected whereby to supply the power supply potential from the two power supply wires, so that power supply potential variation is restrained.

Abstract: A leakage path through a parasitic diode in a charge transfer MOS transistor is cut off to prevent increase in the power consumption and loss of control of a charge pump circuit. A first charge transfer MOS transistor and a second charge transfer MOS transistor are N-channel type and are connected in series with each other. A ground electric potential VSS is supplied to a source of the first charge transfer MOS transistor as an input electric potential, and an output electric potential is obtained from an output terminal connected with a drain of the second charge transfer MOS transistor. A back gate of the first charge transfer MOS transistor is set by a first switching circuit to either an electric potential at a connecting node between the first and the second charge transfer MOS transistors or the ground electric potential VSS.

Abstract: A system and method for supplying power to a peripheral device where the voltage supplied by a host device may be the voltage required for operation of the peripheral, or a higher voltage. A memory system includes a voltage regulator including an input, and output and a bypass shorting the input to the output. A voltage detector communicates with the regulator. A Bypass enable signal operable responsive to a signal generated by the host device indicating that the power up of the host is complete is coupled to the bypass element. A method for operating a voltage regulator in a memory system includes the steps of: providing a voltage regulator having an input and an output, and including a bypass shorting the input to the output; setting the bypass to off prior to power up of a host device; responsive to a power up completion signal from a host device, determining the power supplied by the host; and if the power supplied by the host is below a threshold operating voltage, enabling the bypass.

Abstract: Disclosed is a filter circuit assembly that includes a filter stage with a variable resistor and a resistor/capacitor (RC) oscillator. A controlling output of the RC oscillator controls the value of the variable resistor. The RC oscillator itself also includes a variable resistor. The controlling output of the RC oscillator also controls the value of the variable resistor of the RC oscillator. The structure of the variable resistor of the filter stage is substantially the same as the structure of the variable resistor of the RC oscillator.

Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.

Abstract: A method and apparatus is used to provide DC stabilization and noise reduction in a multistage power amplifier. The invention uses various feedback techniques to stabilize DC levels, which helps to reduce noise. The invention also uses other techniques to reduce noise, and to reduce the noise transfer function in a power amplifier.

Abstract: Briefly, techniques to couple differential amplifiers with a low RC time constant and provide minimal common mode voltage reduction.

Abstract: A power amplifier includes larger size transistors to provide higher power gain at lower frequencies. Transistors of transistor unit cells include a horseshoe-shaped emitter and a strip-shaped base to increase gain. Transistors are combined at a first level to form transistor arrays, which are combined with bonding wires at a second level to an output micro strip transmission line. A Vbe referenced bias circuit may include a smart function to lower quiescent current.

Abstract: According to one exemplary embodiment, a digitally controlled oscillator includes a capacitive tuning network, where the capacitive tuning network controls a frequency of an output signal of the digitally controlled oscillator. The capacitive tuning network includes a switched capacitor array, where a change of a first capacitance of the switched capacitor array causes the capacitive tuning network to change by a second capacitance, and where the first capacitance is larger than the second capacitance. According to this exemplary embodiment, the capacitive tuning network further includes a first capacitor coupled in parallel with the switched capacitor array. The first capacitor has a third capacitance, which is larger than the first capacitance. The capacitive tuning network further includes a second capacitor coupled in series with the first capacitor and the switched capacitor array. The second capacitor can have a fourth capacitance, where the third capacitance is larger than the fourth capacitance.

Abstract: A downhole crystal-based clock that is substantially insensitive to the factors that may cause frequency deviation as a result of downhole temperature. The clock may include a plurality of crystals, where a first crystal may be more stable, with respect to temperature, than a second crystal. The crystals may be thermally coupled together so that they may have substantially the same temperature. An error detector may monitor the differences between the frequencies associated with each crystal and provide this information to a storage device. This information may be determined prior to deploying the clock downhole. When deployed downhole, the signal from the error detector may be interpreted in light of the information in the storage device to provide a temperature measurement of the two crystals. The downhole temperature measurement then may be used to reduce frequency deviations in the downhole clock that may result from downhole temperatures.

Abstract: A mixed signal method and system for tuning a voltage controlled oscillator is described. The method includes dividing a frequency range of an oscillator circuit into a plurality of regions, digitally selecting and tuning one of the plurality of regions of the divided frequency range of the oscillator circuit, and further tuning the selected region of the frequency range of the oscillator circuit via one or more analog tuning elements.

Abstract: A device for signal transmission between units that are movable along given tracks comprises at least one transmitter for generating electrical signals, at least one conductor arrangement for conducting the electrical signals along a track of movement, and at least one receiver for coupling out electrical signals from a conductor arrangement. At least one conductor arrangement comprises at least one conductor structure for conducting electrical signals, an electric reference surface assigned thereto, and at least one dielectric between the conductor structure and the reference surface. A dielectric of the kind used has a high homogeneity, or a high symmetry with respect to the electrical center of the longitudinal axis of the conductor structure, or both.

Abstract: An impedance matching network and network assembly employ one or more variable inductive elements, wherein one or more of the variable inductive elements includes a high temperature ferrite core, a helical coil, and a means for physically translating the magnetic core through the helical coil. An impedance matching network may alternatively or additionally employ one or more variable inductive elements, wherein one or more of the variable inductive elements is cooled using a fan assembly. Further, the impedance matching network and network assembly may alternatively or additionally employ one or more variable inductive elements, wherein the cooling of one or more of the variable inductive elements is facilitated by increasing the surface area of the variable inductive element core.