Abstract: An organic electroluminescent display includes a substrate having an array portion with pixels, and a pad portion coupled to an external power supply. A semiconductor structure is formed on the substrate with a source electrode, a drain electrode and a pad. A passivation layer is formed on the semiconductor structure with via holes exposing regions of the source and the drain electrodes at the array portion and the pad at the pad portion. Portions of the passivation layer contacting the via holes between the array portion and the pad portion have the same thickness. A conductive layer fills the via holes. A pixel defining layer is formed over the entire surface of a flattening layer and the conductive layer with pixel regions exposing regions of the conductive layer at the array portion. An organic electroluminescent film is formed at each pixel region.

Abstract: A thin film transistor array panel is provided, which includes: a plurality of gate lines formed on a substrate and including a plurality of oblique portions and a plurality of gate electrodes; a first insulating layer on the gate line; a semiconductor layer formed on the first insulating layer; a plurality of data lines formed at least on the semiconductor layer and intersecting the gate lines to defined trapezoidal pixel areas; a plurality of drain electrodes separated from the data lines; a second insulating layer formed at least on portions of the semiconductor layer that are not covered with the data lines and the drain electrodes; a plurality of pixel electrodes formed on the second insulating layer and connected to the drain electrodes, at least two of the pixel electrodes disposed in each pixel area; and a plurality of common electrodes formed on the second insulating layer, arranged alternate to the pixel electrodes and connected to the drain electrodes, each common electrode having an edge spaced ap

Abstract: A light emitting device which is capable of suppressing deterioration by diffusion of impurities such as moisture, oxygen, alkaline metal and alkaline earth metal, and concretely, a flexible light emitting device which has light emitting element formed on a plastic substrate. On the plastic substrate, disposed are two layers and more of barrier films comprising a layer represented by AlNxOy which is capable of blocking intrusion of moisture and oxygen in a light emitting layer and blocking intrusion of impurities such as an alkaline metal and an alkaline earth metal in an active layer of TFT, and further, a stress relaxation film containing resin is disposed between two layers of barrier films.

Abstract: A semiconductor photodetector device includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and having a light-receiving region. The first semiconductor layer includes a first region containing an impurity of the first conductivity type at a high concentration and a second region formed on the first region and containing an impurity of the first conductivity type at a concentration lower than that of the first region. The second semiconductor layer includes a third region containing an impurity of the second conductivity type at a concentration higher than that of the second region and a fourth region formed on the third region and containing an impurity of the second conductivity type at a concentration higher than that of the third region.

Abstract: This disclosure concerns systems and devices configured to implement impedance matching schemes in a high speed data transmission environment. In one example, an optoelectronic assembly is provided that includes a TO package having a base through which one or more leads pass. The leads are electrically coupled to an optoelectronic device in the TO package, and are electrically isolated from the base. Some or all of the leads include a ground ring that is electrically isolated from the lead and electrically coupled with the base. A circuit interconnect is also included that is electrically coupled to the optoelectronic device and the TO package. The circuit interconnect includes a dielectric substrate having signal traces that are electrically coupled to the signal leads. A ground signal conductor disposed on the dielectric substrate is electrically coupled with the ground rings.

Abstract: Light-emitting devices, and related components, systems and methods are disclosed. The light-emitting device can include a multi-layer stack of materials including a light-generating region and a first layer supported by the light-generating region. A surface of the first layer can be configured so that light generated by the light-generating region can emerge from the light-emitting device via the surface of the first layer. The surface of the first layer can have a dielectric function that varies spatially according to a pattern that has an ideal lattice constant and a detuning parameter with a value greater than zero.

Abstract: A light emitting apparatus has: a support; a wiring layer that is formed on the support; and an LED element that is flip-chip mounted on the wiring layer formed on the support. The wiring layer has: a conductive layer that is formed on the support and is electrically connected to an electrode of the LED element; and a reflection layer that is formed on the conductive layer that has a light reflection property to allow a radiated light from the LED element to be reflected thereon. The reflection layer is of a material that generates no intermetallic compound to a material of the conductive layer.

Abstract: Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers.

Abstract: An improvement in electrode reliability is realized by preventing over-etching on a peripheral lower portion of an electrode while maintaining the flow of steps of roughening a surface after forming the electrode on a semiconductor substrate. After a P-side electrode 4 is formed on a main surface 3a of a semiconductor substrate 3, a surface of the P-side electrode 4 is selectively covered with a protective film 12, after the semiconductor substrate 3 is cut into chips, the surface is roughened from above the protective film 12, the main surface 3a around the P-side electrode 4 and a side surface are roughened with a non-chemical treatment region 10 which is a non-roughened surface region being left in a peripheral portion of the P-side electrode 4 covered with the protective film 12, and thereafter the protective film 12 is removed.

Abstract: In a light emitting device with a heat-release metallic part made of metal and a packaging ceramic part made of ceramics bonded to the metallic part via an adhesive, the adhesive is a hot melt that melts with heat at a melting temperature higher than a given temperature and has flexibility when it has been hardened and formed a bond, and the ceramic part has pores at least in a given bonding surface region so that the hot melt is impregnated into the pores.

Abstract: A high emission intensity group-III nitride semiconductor light-emitting device obtained by eliminating crystal lattice mismatch with substrate crystal and using a gallium nitride phosphide-based light emitting structure having excellent crystallinity. A gallium nitride phosphide-based multilayer light-emitting structure is formed on a substrate via a boron-phosphide (BP)-based buffer layer. The boron phosphide-based buffer layer is preferably grown at a low temperature and rendered amorphous so as to eliminate the lattice mismatch with the substrate crystal. After the amorphous buffer layer is formed, it is gradually converted into a crystalline layer to fabricate a light-emitting device while keeping the lattice match with the gallium nitride phosphide-based light-emitting part.

Abstract: A CSTBT includes a carrier stored layer (113) formed between a P base region (104) and a semiconductor substrate (103) and the carrier stored layer has an impurity concentration higher than that of the semiconductor substrate (103). The P base region (104) in a periphery of a gate electrode (110) functions as a channel. When it is assumed that an impurity concentration of a first carrier stored layer region (113a) just under the channel is ND1 and an impurity concentration of a second carrier stored layer region (113b) other than just under the channel is ND2 in the carrier stored layer (113), the relationship of the impurity concentrations is defined by ND1<ND2. Thus, a gate capacity and a short-circuit current can be controlled and variation in threshold voltage can be prevented.

Abstract: The present invention provides an electro-optical device capable of achieving an increased light emission efficiency and an enhanced visibility. An organic electroluminescents (EL) display device has a plurality of material layers including a luminescent layer. In a plurality of material layers layered in the direction of light emission from the luminescent layer, first and second insulating interlayers are disposed between a substrate, which is positioned at the outermost surface, and the luminescent layer. The first and second insulating interlayers have a refractive index lower than that of the substrate. Accordingly, by forming predetermined materials having a low refractive index, the resulting low refractive index layers have a low dielectric constant, and consequently, the capacity between wires can be reduced.

Abstract: A semiconductor device is formed by a first layer 32 composed of AlGaN, a second layer 42 composed of GaN, a gate electrode 34, a source electrode 38, and a drain electrode 28. The first layer 32 has a region 32a formed between the gate electrode 34 and the second layer 42. A channel is formed in the vicinity of the boundary 24 of the first layer 32 and the second layer 42. The second layer 42 has p-type conductivity and is in contact with the source electrode 38. When electrons flow in the channel, the electrons collide with surrounding atoms, and holes are formed. If holes are accumulated inside the semiconductor device, the presence of the accumulated holes causes dielectric breakdown. In the semiconductor device of the invention, holes are discharged to the outside of the device thorough the second layer 42 and the source electrode 38, and accumulation of holes can be prevented.

Abstract: A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.

Abstract: An integrated circuit includes CMOS circuit blocks and analog control lines arranged outside a layout of the CMOS circuit blocks so that the analog wiring and circuit blocks do not overlap each other. The distance of signal lines within a circuit block and the analog control lines can become as long as necessary, and the signal line within the circuit block and the analog control lines are not coupled via parasitic capacitance, and mutual interference is suppressed. In another aspect, a method of arranging a semiconductor integrated circuit includes providing a plurality of functional circuit blocks and connecting analog control wiring to the functional circuit blocks. The analog control wiring is arranged outside a layout of the functional circuit blocks on the semiconductor integrated circuit so that the analog control wiring does not overlap any one of the functional circuit blocks so as to reduce or eliminate interference between signal lines within a circuit block and the analog control lines.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: The present invention relates to systems and methods for programming a memory cell. More specifically, the present invention relates to a controlled application of current to a memory cell over a controlled time period. The invention utilizes a current mirror configuration having a first transistor and a second transistor, wherein the second transistor is coupled to the memory cell. Programming of the memory cell includes applying a voltage to the first transistor, whereby a first current is generated in the first transistor. A gate of the second transistor is coupled to the first transistor, whereby a second current is generated in the second transistor. The second current is proportional to the first current. The second current is provided to the memory cell, whereby the second current programs the memory cell.

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

Abstract: A multiple doped channel in a multiple doped gate junction field effect transistor. In accordance with a first embodiment of the present invention, a junction field effect transistor (JFET) circuit structure comprises a vertical channel. The vertical channel comprises multiple doping regions. The vertical channel may comprise a first region for enhancement mode operation and a second region for depletion mode operation.

Abstract: A semiconductor component includes a semiconductor body having a substrate of a first conduction type and a first layer of a second conduction type that is located above the substrate. A channel zone of the first conduction type is formed in the first layer. A first terminal zone of the second conduction type is configured adjacent the channel zone. A second terminal zone of the first conduction type is formed in the first layer. Compensation zones of the first conduction type are formed in the first layer.

Abstract: A CMOS image sensor includes a photo sensing device for generating photo charges, a floating diffusion region for storing the photo charges generated by the photo sensing device therein, a transfer transistor connected between the photo sensing device and the floating diffusion region for transferring the photo charges generated by the photo sensing device to the floating diffusion region, a reset transistor connected between a supply voltage terminal and the floating diffusion region for discharging the charges stored in the floating diffusion region to reset the floating diffusion region, a drive transistor for acting as a source follower buffer amplifier in response to an output signal from the photo sensing device, a switching transistor connected to the drive transistor for performing an addressing operation, and a charge control device connected between the photo sensing device and the transfer transistor for controlling the amount of charges stored in the photo sensing device.

Abstract: The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel regions are first opened for N+ source/drain implant and P-channel regions are then opened for P+ source/drain implant. Prior to the N+ source/drain implant, the wafer receives a patterned first spacer etch. During this first spacer etch, the photosensor region is covered with resist. Prior to the P+ source/drain implant, a masked second spacer etch is performed. Again the photosensor region is protected with photoresist. In such a manner, spacers are formed on the gates of both the N-channel and P-channel transistors but in the photodiode region the spacer insulator remains.

Abstract: A method of forming a magnetic random access memory (MRAM) using a sacrificial cap layer on top of the memory cells and the structure resulting therefrom are described. A plurality of individual magnetic memory devices with cap layers are fabricated on a substrate. A continuous first insulator layer is deposited over the substrate and the magnetic memory devices. Portions of the first insulator layer are removed at least over the magnetic memory devices and then the cap layers are selectively removed from the magnetic memory devices, thus exposing active top surfaces of the magnetic memory devices. The top surfaces of the magnetic memory devices are recessed below the top surface of the first insulator layer. Top conductors are formed in contact with the active top surfaces of the magnetic memory devices. In an illustrated embodiment, spacers are also formed along the sides of the magnetic memory devices before the first insulator layer is deposited.

Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.

Abstract: A ferroelectric memory comprises a first transistor connected between N1 and N2 nodes, a second transistor connected between the N2 node and an N3 node, a first transistor connected between P1 and P2 nodes, a second transistor connected between the P2 node and a P3 node, a first wiring formed in a first wiring layer to interconnect the N1 node and the P1 node, a second wiring formed in the first wiring layer to interconnect the N3 node and the P3 node, a third wiring formed in a second wiring layer different from the first wiring layer to interconnect the N2 node and the P2 node, a first capacitor whose first electrode is connected to the first wiring, and a second capacitor whose first electrode is connected to the second wiring. Second electrodes of the first and second capacitors are both connected to the N2 node or the P2 node.

Abstract: High quality epitaxial layers of GaN can be grown overlying large silicon wafers (200) by forming an amorphous layer (210) on the substrate. The amorphous layer dissipates strain and permits the growth of a high quality GaN layer (208). Any lattice mismatch between the GaN layer and the underlying substrate is taken care of by the amorphous layer.

Abstract: An electronic device incorporating a tubular shaped carbon molecule supported by a substrate, which molecule is provided with source and drain electrodes, as well as a gate electrode, wherein the gate electrode is a metallic electrode. The metallic electrode has a surface layer of oxide, preferably native oxide. The metallic electrode is preferably aluminium, zinc and copper.

Abstract: Field effect devices having a gate controlled via a nanotube switching element. Under one embodiment, a non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and each in electrical communication with a respective terminal. A channel region of a second semiconductor type of material is disposed between the source and drain region. A gate structure is disposed over an insulator over the channel region and has a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the gate structure and the terminal corresponding to the gate structure. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the gate structure and its corresponding terminal.

Abstract: The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.

Abstract: Memory cells having two electrodes and a layer arranged in between and including an active material which contains hexakisbenzylthiobenzene, dichlorodicyano-p-benzoquinone and optionally a polymer are provided. Furthermore, a process for the production of the cells according to the invention is provided, as well as the novel use of a composition which can be used as active material for the memory cells.

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, a plurality of memory cells formed on the semiconductor substrate, a plurality of first assist gates extending toward the memory cell, a connection portion connecting end portions of the first assist gates, a second assist gate extending toward the memory cell, a first select transistor controlling whether to apply a voltage to an area under the first assist gate, a second select transistor controlling whether to apply a voltage to an area under the second assist gate, and an impurity region. The insulating film formed under an intersection area of the connection portion and the impurity region has a thickness larger than the insulating film formed under the first and second assist gates. A non-volatile semiconductor memory device capable of ensuring a writing speed as well as reliability can thus be obtained.

Abstract: A split gate memory cell can include a first gate electrode and a second gate electrode. The split gate memory cell can also include a first diffusion region underlying a trench in a semiconductor substrate, wherein the trench has a sidewall, and the first diffusion region lies closer to the first gate electrode than the second gate electrode. The split gate memory cell can further include a second diffusion region lying outside the trench, wherein the second diffusion region lies closer to the second gate electrode than the first gate electrode. The split gate memory cell can still further include a charge storage layer adjacent to the sidewall of the trench, wherein the charge storage layer includes discontinuous storage elements. Methods of forming and using the split gate memory cell are also disclosed.

Abstract: A semiconductor device according to a exemplary embodiment of the present invention includes a reverse spacer exposing a part of an epitaxial silicon layer on a silicon substrate, a gate oxide layer on at least the epitaxial silicon layer and a gate polysilicon layer on the gate oxide layer and at least part of the reverse spacer, and source/drain terminals including a first doped (shallow junction) region in the silicon substrate at a position exterior to the exposed epitaxial silicon layer and a second doped (deep junction) region neighboring the first doped region. The semiconductor device can thus have an epitaxial silicon channel of nanometer size, an ultra-shallow junction, and a deep junction.

Abstract: In the case of the semiconductor component (1) according to the invention, the source regions (S), the body regions (B) and, if appropriate, the body contact regions (Bk) are in each case arranged in mesa regions (M) of adjacent trenches (30). In the edge region (R) of the cell array (Z) the insulation (GOX, FOX) of the underlying trench structures (30) by an insulating oxide layer (FOX) is comparatively thick and formed in the form of a field oxide (FOX) or thick oxide (FOX).

Abstract: An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the inside device region and divided in segments by insulated trench-shaped gates to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, an inner region defined in and insulated from the dummy base region, and a connection part to electrically connect the inner region to the emitter electrode.

Abstract: A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p+-type semiconductive region and in contact with the p+-type semiconductive region and an n?-type single crystal silicon layer and that has an impurity concentration lower than the p+-type semiconductive region. An n-type semiconductive region is formed in the n?-type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n?-type single crystal silicon layer.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lower end surface. A source region, a drain region, and a channel-forming region between the source and drain regions are all formed in the semiconductor substrate body. trench isolation insulator islands surround the source and drain regions as well as the channel-forming region. The channel-forming region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is also provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements.

Abstract: A semiconductor device includes a dielectric layer, a semiconductor layer provided above the dielectric layer, a gate dielectric layer provided above the semiconductor layer, a gate electrode provided above the gate dielectric layer, a source region and a drain region provided in the semiconductor layer, a body region other than the source region and the drain region in the semiconductor layer, and a body contact region that divides the source region in a plurality of areas and joins to the body region, wherein the body contact region is formed of a compound of a semiconductor of the semiconductor layer and a metal.

Abstract: An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously-elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate.

Abstract: A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.

Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.

Abstract: Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.

Abstract: A semiconductor device capable of integrally controlling thresholds of gate electrodes of transistors present in a region of one-conductivity-type and transistors present in a region of an reverse-conductivity-type while suppressing noise propagation is provided. A digital circuit region 123 and an analog circuit region 121 are provided on a P—Si substrate 101. P-wells 103 and 193 and N-wells 105 and 195 are provided in the analog circuit region 121. P-wells 107 and 197 and N-wells 109 and 199 are provided in the digital circuit region 123. A mesh-like deep N-well 111 is provided to contact with lower surfaces of the P-well 103 and the N-well 105. A mesh-like deep N-well 113 is provided to contact with lower surfaces of the P-well 107 and the N-well 109.

Abstract: Transistors and methods of fabricating transistors are disclosed. A disclosed method comprises forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; depositing a silicon epitaxial layer over the inversion epitaxial layer; forming a trench through the silicon epitaxial layer by removing the hard mask; forming reverse spacers on the sidewalls of the trench by filling the trench with an insulating layer and etching the insulating layer; forming a gate electrode over the reverse spacers; forming pocket-well regions and LDD regions in the silicon substrate by performing ion implantations; forming spacers on the sidewalls of the gate electrode; forming source and drain regions in the silicon substrate by performing an ion implantation; and forming a silicide layer on the gate electrode and the source and drain regions.

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 ?m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack within inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.

Abstract: A sensor device for use in an automobile as an airflow sensor is composed of a silicon substrate in which a cavity is formed and a base plate bonded to the silicon substrate. An upper end of the cavity is closed with a thin membrane including a sensor element such as a temperature sensor element, while a lower end of the cavity is closed with the base plate. An air passage having a small cross-section is formed through the base plate, so that the cavity communicates with the outside air through the air passage. The thin membrane is prevented from being damaged by collision with foreign particles included in the airflow because the air in the cavity functions as a damper. The air passage may be made in the silicon substrate in parallel to its surface without using the base plate.

Abstract: An MTJ MRAM cell element, whose free layer has a shape induced magnetic anisotropy, is formed between orthogonal word and bit lines. The bit line is a composite line which includes a high conductivity current carrying layer and a soft adjacent magnetic layer (SAL). During operation, the soft magnetic layer concentrates the magnetic field of the current and, due to its proximity to the free layer, it magnetically couples with the free layer to produce two magnetization states of greater and lesser stability. During switching, the layer is first placed in the less stable state by a word line current, so that a small bit line current can switch its magnetization direction. After switching, the state reverts to its more stable form as a result of magnetostatic interaction with the SAL, which prevents it from being accidentally rewritten when it is not actually selected and also provides stability against thermal agitation.

Abstract: An N well is disposed in the upper surface of a P type substrate, a gate insulating film and a gate electrode are disposed thereon, and the gate electrode is connected to a gate terminal. Two p+ diffusion regions are placed in two areas in the surface of the N well sandwiching the gate electrode, and the p+ diffusion regions are connected to a ground potential wiring. Further, an n+ diffusion region is disposed in the surface of the N well, and is connected to a well terminal. Accordingly, capacitance is generated between the gate electrode and the N well of a varactor element. When the potential of the gate terminal is decreased, the two p+ diffusion regions absorb positive holes serving as minority carriers from a channel region.