Abstract: The present invention discloses an illumination device for illuminating users of a multimedia communication terminal. In particular, the illumination device includes high power white LEDs together with a reflector and a diffuser integrated in, or connected to, the terminal. Preferably, the light intensity and the position and angle relative to the terminal are controllable through a user interface.

Abstract: A lamp housing includes a base (21), at least two frame members (23) and at least two frame holding members (24). The base includes an upper surface for deposing at least one lamp (20). The frame members are respectively attached to two opposite ends of the base so as to hold the lamp. The frame holding members are each fixed on a corresponding one of the frame members so as to fix the frame members together with the lamp.

Abstract: A bottom-lighting type backlight module includes a frame, a light guide member and a plurality of linear light sources. The frame includes a base and a plurality of sidewalls extending from the periphery of the base to define an opening. The light guide member is disposed on the opening of the frame, the light guide member having a prism surface away from the base of the frame. The light sources are arranged in the frame under the light guide member. The base of the frame defines a plurality of projections extending out from thereof towards the opening along a direction perpendicular to the light sources, and a plurality of curving surfaces are defined by the base of the frame between two adjacent projections, each curving surface facing the adjacent light source. The present backlight module may have good optical uniformity and high brightness without the help of light diffusion plate.

Abstract: A backlight assembly includes a frame, a light source, and at least one optical film. The light source is disposed on the frame. The optical film has at least one positioning flange. The positioning flange includes at least two contact edges configured to abut against at least one edge of the frame in at least two directions to hold the optical film in place relative to the frame.

Abstract: A securing apparatus for holding chamber covers onto a chamber base of a lamp is disclosed. The chamber may provide access to a night light bulb held in place by a clip passing through the bottom of said chamber. The securing apparatus comprises a locking sleeve with an integral check-ring designed to engage a threaded coupling mounted on a neck tube of the lamp. The locking sleeve is designed with a threaded lower end, which when engaged with the threaded coupling forces the bottom of the check-ring to engage the top of the cover when the cover is in place on the chamber base. Only the length of the locking sleeve needs to be changed to accommodate various depths of chamber covers, providing an economical way to adjust the general aesthetics of the lamp by varying only the look of the cover.

Abstract: A converter circuit having a first and a second converter element is specified, with each converter element having a DC voltage circuit and in each case one converter element phase (u1, v1, w1) of the first converter element being connected to a respective converter element phase (u2, v2, w2) of the second converter element. Furthermore, a transformer is provided, with the secondary windings of the transformer being connected to the connected converter element phases (u1, v1, w1, u2, v2, w2) of the first and second converter elements.

Abstract: A system and method for delivering regulated power and current to an output load has a flyback transformer having a primary winding and a secondary winding. The secondary winding delivers stored energy to the output load. An oscillator circuit is provided for generating a periodical signal. A switching circuit is coupled to the flyback transformer and the oscillator circuit for energizing the primary winding to a reference current level each cycle of the oscillator circuit. The oscillator circuit has an integrator for deriving a time integral of a voltage at the primary winding. The oscillator circuit has a peak detector coupled to the integrator for holding a peak value of the time integral. The oscillator circuit further has a ramp generator for producing a ramp signal. A comparator is provided for comparing the peak value with the ramp signal and generating the periodical signal whenever the ramp signal exceeds the peak value.

Abstract: A DC converter comprises a single primary circuit which is coupled to each of a plurality of output circuits in respective time periods, the coupling being provided by switching in the output circuits. Each output circuit produces a respective output voltage and a respective feedback signal which is coupled as a control signal to the primary circuit during the respective time periods, so that each output voltage is regulated substantially independently of each other output voltage. The time periods for the different output circuits can be equal or different, and can be dynamically changed depending on error voltages of the output circuits.

Abstract: A DC-DC flyback converter, includes a three-winding transformer; a primary power circuit having a first MOSFET connected to a first winding of the transformer; a secondary power circuit connected to a second winding of the transformer terminals; and a self-driven circuit connected to a third winding of the transformer. The secondary power circuit includes a synchronous rectifier in the form of a second MOSFET and the self-driven circuit further includes a delay drive circuit, an isolation differential circuit, a negative removal circuit having a third MOSFET and a synchronous rectifier trigger switch-off circuit for switching the synchronous rectifier to an off condition.

Abstract: The present invention provides a switching control circuit having a valley voltage detector to achieve the soft switching and improve the efficiency of a power converter. The switching control circuit includes a control circuit coupled to the feedback signal to generate a switching signal. Through an output circuit, the switching signal drives a switching device for switching a transformer and regulating the output of the power converter. The valley voltage detector is coupled to an auxiliary winding of the transformer for generating a control signal in response to the voltage of the transformer. The control signal is used for enabling the switching signal. The switching signal further turns on the switching device in response to a valley voltage across the switching device.

Abstract: A power system for providing an output power to a load is provided. The system comprises a generator configured to generate an alternating current input power and an power converter system coupled to the generator and configured to generate an output power and provide the output power to the load through at least one transformer. The system further comprises a converter control system coupled to the converter system and configured to drive the converter system in an interleaved pattern to reduce harmonic components in the output power and the alternating current input power.

Abstract: The present invention provides_a power converter that can be used to interface a generator (4) that provides variable voltage at variable frequency to a supply network operating at nominally fixed voltage and nominally fixed frequency and including features that allow the power converter to remain connected to the supply network and retain control during supply network fault and transient conditions. The power converter includes a generator bridge (10) electrically connected to the stator of the generator (4) and a network bridge (14). A dc link (12) is connected between the generator bridge (10) and the network bridge (14). A filter (16) having network terminals is connected between the network bridge (14) and the supply network. A first controller (18) is provided for controlling the operation of the semiconductor power switching devices of the generator bridge (14).

Abstract: A rectifier circuit includes first and second input terminals for receiving a rectangular wave input voltage, and first and second output terminals for providing a rectified dc output voltage. A first switch is coupled between the first input terminal and a first node, the first node being coupled to the first output terminal. A second switch is coupled between the second input terminal and the first node. A third switch is coupled between the first input terminal and a second node, the second node being coupled to the second output terminal. A fourth switch is coupled between the second input terminal and to the second node. The first switch and fourth switch are gated on when the input voltage is of a first polarity; and the second switch and the third switch are gated on when the input voltage is of a second polarity opposite the first polarity so as to provide an output voltage having a magnitude substantially equal to the magnitude of the input voltage.

Abstract: An electronic apparatus having a load including: a power supply unit supplying a driving voltage to the load; an inverter unit switching the driving voltage; and a control voltage supply unit outputting a first control voltage lower than a reference voltage applied to one terminal of the inverter unit, and a second control voltage higher than the reference voltage, thus controlling the inverter unit. Thus, the electronic apparatus and power circuit are capable of improving a control voltage applied to an inverter unit to reduce the switching loss of the inverter unit.

Abstract: An apparatus for a power supply with brownout protection and the method thereof are proposed. As a brownout condition occurs, the apparatus informs at least one microprocessor to process the shutdown process timely. The apparatus includes a power factor correction (PFC) circuit, and a bus capacitor generating a bus voltage by receiving an input voltage via the PFC circuit, and a PWM circuit generating multiple output voltages for the microprocessor, and a supervisor circuit generating a power-good signal in response to a proportional bus voltage, and a brownout circuit for disabling the boosting operation of the PFC circuit under a brownout condition. When the boosting operation is disabled, the bus voltage starts to fall. As the proportional bus voltage is lower than a threshold voltage, the supervisor circuit generates the power-good signal. Therefore, the microprocessor can process the shutdown procedure timely.

Abstract: This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field effect transistor, to the first field effect transistor during the operation mode of the first circuit, and applies a second source bias voltage, which reversely biases between the source and the body of the first field effect transistor, to the first field effect transistor during the standby mode of the first circuit. During the standby mode of the first circuit, the leakage current that flows through the first FET is reduced by means of the reverse bias effect produced by applying the second source bias voltage to the source of the first FET.

Abstract: A semiconductor memory device includes memory cell arrays, word lines, bit lines, column gates, sense amplifiers, and an error correcting circuit. The memory cell array includes first regions and a second region. The first region includes first element isolating regions which have stripe shapes along the bit lines. The memory cell is formed on an element region between the adjacent element isolating regions. The first regions are arranged in plurality along the word line direction. The second region is provided adjacent to the first region in a direction along the word lines. The second region includes a second element isolating region whose width along the word line direction is greater than that of the first element isolating region. Addresses of the bit line adjacent to the second region are different from one another among the memory cell arrays.

Abstract: An apparatus for generating a DBI signal in a semiconductor memory apparatus includes a data switching detection unit that detects whether or not previous data is consistent with current data and outputs a detection signal according to a detection result, and a DBI detection unit that outputs a DBI signal according to a difference in charge sharing level using the detection signal. Therefore, it is possible to minimize current consumption. Further, since there is no effect due to resistance skew of a transistor, an error in DBI signal generation and an error in data transfer accordingly can be prevented. Therefore, it is possible to improve the reliability of a system to which a semiconductor memory apparatus is applied.

Abstract: A semiconductor memory device comprises a cell array including bit lines arranged at a uniform pitch; and a plurality of bit line selection transistors connected to respective bit line ends for selectively connecting the bit line to a sense amp. The bit line selection transistors are translationally arrayed in a direction perpendicular to the bit line at an average array pitch greater than eight times the pitch of the bit lines.

Abstract: Provided are a memory array using a mechanical switch, a method for controlling the same, a display apparatus using a mechanical switch, and a method for controlling the same. The memory array comprises a plurality of word lines, a plurality of bit lines intersecting each other with the plurality of word lines, and a plurality of the mechanical switches. The mechanical switch comprises a gate electrode, a drain electrode, and a source electrode.

Abstract: A phase change memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. The phase change bridge may extend over the generally coplanar surfaces and across the gap. The phase change bridge has a higher transition temperature bridge portion and a lower transition temperature portion. The lower transition temperature portion comprises a phase change region which can be transitioned from generally crystalline to generally amorphous states at a lower temperature than the higher transition temperature portion. A method for making a phase change memory cell is also disclosed.

Abstract: One-time programmable, non-volatile field effect devices and methods of making same. Under one embodiment, a one-time-programmable, non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each of the source, drain, and gate has a corresponding terminal. An electromechanically-deflectable, nanotube switching element is electrically coupled to one of the source, drain and gate and has an electromechanically-deflectable nanotube element that is positioned to be deflectable in response to electrical stimulation to form a non-volatile closed electrical state between the one of the source, drain and gate and its corresponding terminal.

Abstract: This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, arranged between the bit line and the first word line and between the bit line and the second word line respectively at least on a region where the bit line and the first and second word lines intersect with each other. The bit line, the first word line and the first ferroelectric film constitute a first ferroelectric capacitor while the bit line, the second word line and the second ferroelectric film constitute a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor constitute a memory cell.

Abstract: A data carrier system includes: a first memory, which is a ferroelectric memory; a second memory; a polarization canceling circuit for canceling polarization of the first memory in accordance with an instruction given thereto; and a control circuit for making data access to the first and second memories and controlling operation of the polarization canceling circuit. Upon receipt of a first instruction, the control circuit saves data stored in the first memory to the second memory and then gives an instruction for canceling polarization to the polarization canceling circuit, while upon receipt of a second instruction, the control circuit writes the data saved to the second memory back into the first memory.

Abstract: A ferroelectric random access memory (FRAM) device includes a memory cell array including a plurality of FRAM cells connected to a first bit line and a reference cell connected to a second bit line. The device also includes a sense amplifier circuit configured to evaluate an amount of charges induced in a FRAM cell at a first mode and sense data stored in the FRAM cell at a second mode, wherein the sense amplifier circuit comprises a reference voltage generator configured to output an externally applied voltage as a reference voltage at the first mode, and output the reference voltage in response to a voltage applied to the second bit line from the reference cell and a voltage charged to an offset node at the second mode, and an amplifier circuit configured to sense and amplify a difference between a voltage applied to the first bit line from a selected FRAM cell and the reference voltage.

Abstract: Circuits for writing, reading, and erasing a programmable metallization cell are disclosed. The programming circuits compensate for parasitic capacitance and/or parasitic resistance. The parasitic resistance and/or capacitance is compensated for using a feedback loop or a time current filter. Various circuits also measure a switching speed of the programmable metallization cell.

Abstract: A memory cell arrangement includes a set of word lines and bit lines and at least one chain of series-connected memory elements which is electrically connected to one of the bit lines. The memory elements each include a resistive memory cell, which can be switched between a low-resistance ON state and a high-resistance OFF state, and a transistor which is electrically connected to the resistive memory cell in a parallel circuit. The ON resistance of the transistor, which has been turned on, of a memory element is smaller than the ON resistance of the memory cell which has been switched to its low-resistance ON state. Each transistor in a respective chain is electrically connected to one of the word lines.

Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

Abstract: A static random access memory (SRAM) cell includes a SRAM circuit and a programmable resistor connected to a storage node of the SRAM circuit. The SRAM circuit can be any type of SRAM circuit, such as a 3T, negative differential resistance (NDR) transistor-based circuit, or a 6T (conventional SRAM) circuit. The programmable resistor can be formed in a metal layer above the SRAM circuit to minimize the area requirements for the memory cell. Just before shutdown of the SRAM cell, the resistance state of the programmable resistor is changed (if necessary) based on the data value stored at the storage node. The programmable resistor provides a non-volatile indication of the stored data value at the time of power off. Then, when power is restored to the SRAM cell, a data value based on the resistance state of the programmable resistor is written back into the SRAM circuit.

Abstract: A semiconductor memory device is provided, which comprises an analog switch, a first inverter, a second inverter, and a clocked inverter. A first terminal of the analog switch is electrically connected to a first data line. A second terminal of the analog switch is electrically connected to an input terminal of the first inverter, an output terminal of the second inverter, and an input terminal of the clocked inverter. An output terminal of the first inverter is electrically connected to an input terminal of the second inverter. An output terminal of the clocked inverter is electrically connected to a second data line. Each of the analog switch and the clocked inverter is electrically connected to at least one word line. The word line electrically connected to the analog switch is different from the word line electrically connected to the clocked inverter.

Abstract: The magnetic fields generated by the electric current flowing through the respective lines are pulled into a magnetic yoke whereby the magnetic fields are concentrated on a magnetoresistive element including the magnetosensitive layer. Namely, the opposite magnetic fields are brought close to each other in the magnetosensitive layer in reading of information to cancel each other efficiently.

Abstract: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change bridge positioned between and electrically coupling the opposed sides of the electrodes to one another. The phase change bridge has a length, a width and a thickness. The width, the thickness and the length are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the width and the length of the phase change bridge are each less than the minimum photolithographic feature size.

Abstract: A system and method form a nanodisk that can be used to form isolated data bits on a memory disk. The imprint stamp is formed from first and second overlapping patterns, where the patterns are selectively etched. The selective etching leaves either pits or posts on the imprint stamp. The pits or posts are imprinted on the memory disk, leaving either pits or posts on the memory disk. The pits or posts on the memory disk are processed to form relatively small and dense isolated data bits. Instability of the isolated data bits caused by outside magnetic and thermal influences is substantially eliminated.

Abstract: A semiconductor memory device including a memory cell array and a sense amplifier, wherein the memory cell array includes: a plurality of information cells, in each of which either one of multi-level data is written; a first reference cell with the same structure and the same connection state as the information cell, in which a reference data level is written for generating a first reference current; and a second reference cell, which serves for generating a second reference current used for setting the lowest data level of the multi-level data and for setting the reference data level of the first reference cell.

Abstract: A semiconductor storage device in which a read sense circuit stable for the fluctuation in manufacturing process and environmental conditions can be realized and the read access time can be shortened is provided. A sense circuit for reading a memory cell characterized in that a flowing current is varied depending on stored data and a voltage applied through a word line includes: an inverter; a first capacitor provided so as to be electrically connected between an input of the inverter and a bit line to which the memory cell is connected; a first transistor which short-circuits an input and an output of the inverter; a second capacitor for supplying charge to the first capacitor; and second transistors, wherein an input potential of the inverter is increased or decreased according to the current of the memory cell and is then amplified to be latched as a logic value.

Abstract: In a memory cell array, a plurality of memory cells which store data in the form of n values (n is a natural number which is not smaller than 2) which are in first and second to nth states are arranged in a matrix form. Before a write operation of storing data in a first memory cell in the memory cell array, when at least one second memory cell which is adjacent to the first memory cell is in the first state and does not reach a first threshold voltage, a control circuit performs a write operation in the second memory cell up to the first threshold voltage.

Abstract: A nonvolatile memory includes a memory cell array in which a plurality of memory cells are connected to a plurality of wordlines and a plurality of bitlines respectively intersecting at a right angle with the plurality of wordlines; a selector for selecting one of the bitlines which is connected to first one of the memory cells in which actual data is stored; and a transfer circuit for connecting with a reference bitline which is connected to second one of the memory cells in which a reference level is stored. The nonvolatile memory further includes an amplifier section, connected to the selector and the transfer circuit, for reading out and amplifying levels of the bitline and the reference bitline and comparing the actual data with the reference level; and a charger for charging the bitline selected by the selector.

Abstract: The use of a Nitride layer or a silicon-nodule layer capable of location-specific (LS) charge storage, allow easy vertical scaling and implementation of NOR and NAND NVM array and technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element and if charge is stored in potential wells of discrete silicon-nodules, or Carbon Bucky-ball layers, an Oxide silicon-nodule Oxide storage element, or an Oxide Bucky-ball Oxide layer is used as the storage element. The problem of location-specific NAND memory is the inability to erase the cells with repeatable results. A novel erase method, Tunnel Gun (TG) method, that generate holes for consistent erase of LS storage elements and typical NAND Cells that erase by the disclosed method and programmed by either by Fouler-Nordheim (FN) tunneling or Low Current Hot Electron (LCHE) method are disclosed.

Abstract: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).

Abstract: A high-voltage charge pump circuit includes a charge pump circuit. A first high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high-voltage output circuit is configured to set the output voltage of the charge pump at a second voltage level selected for walkout of device junctions, the second voltage level being higher than the first voltage level. A third high-voltage output circuit is configured to set the output voltage of the charge pump at a third voltage level selected for guardband programming and erasing, the third voltage level being lower than the second voltage level and higher than the first voltage level. Selection circuitry selectively couples one of the first, second, and third high-voltage output circuits to the output of the high-voltage charge pump circuit.

Abstract: A semiconductor device includes a memory cell array, first word lines, second word lines and interconnection switching region. The memory cell array includes electrically rewritable nonvolatile memory cells. Each first word line is connected in common to memory cells of a corresponding row. Second word lines correspond to the respective first word lines. The second word lines are formed of a second interconnection of a layer different from that of the first interconnection. An interconnection switching region is provided between the first word lines and the second word lines. The interconnection switching region connect selected portions of the first interconnection and the second interconnection. The interconnection switching region has a multilayered interconnection structure in which the first word lines cross the second word lines to change at least part of layout positions.

Abstract: The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level1).

Abstract: An integrated circuit (10) having non-volatile memory (NVM) (14) includes a threshold selector (28) which selects a first one of a plurality of read current/voltage thresholds during a first portion of a program/erase cycle, and which selects a second one of a plurality of read current/voltage thresholds during a second portion of said program/erase cycle, wherein the first one of a plurality of read current/voltage thresholds and the second one of a plurality of read current/voltage thresholds are different. The first portion of the program/erase cycle occurs in time before the second portion of the program/erase cycle. The second one of the plurality of read current/voltage thresholds is less than the first one of the plurality of read current/voltage thresholds.

Abstract: A non-volatile memory device includes first and second memory cell blocks, each including a plurality of memory cells and including a local drain select line, a local source select line, and local word lines. A block selection unit connects given local word lines to global word line, respectively, in response to a block selection signal. A first bias voltage generator is configured to apply at least first and second erase voltages to the global word lines during an erase operation, the first erase voltage being applied to the global word lines during a first erase attempt of the erase operation, the second erase voltage being applied to the global word lines during a second erase attempt, where the second erase attempt is performed if the first erase attempt did not successfully perform the erase operation. The first and second erase voltages being positive voltages. A bulk voltage generator applies a bulk voltage to a bulk of the memory cells during the erase operation.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. One embodiment includes a printed circuit board, comprising: at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.

Abstract: The present invention provides a method for testing an electrical property of one or more functionally separate transistors located within an active region that is common with other transistors, a method for characterizing the leakage current of at least one of a plurality of functionally separate transistors located in a common active region of a circuit, and a test structure for testing one or more functionally separate transistors located within a common active region. The method for testing the electrical property, among other steps, includes providing a pair of functionally separate transistors (110) located within a common active region, and biasing a terminal (135) between the pair (110) relative to gates (125, 155) of the pair (110) and terminals (130, 160) outlying the pair (110) to obtain a leakage current associated with the pair (110).

Abstract: A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first and a second input terminal. A switching circuit is configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.

Abstract: There is provided a nonvolatile semiconductor memory device and its writing method capable of controlling an increase in threshold voltage due to effects of adjacent memory cells and performing stable readout operations even if miniaturization of semiconductor memory devices proceeds further. The device comprises a memory cell array 411 having memory cells in a row and column directions, a row selection circuit 412, a column selection circuit 411, and a control circuit 405 for exercising writing control on a selected memory cell by an external command input. The control circuit performs a threshold voltage control for writing a memory cell selected as a writing target to a first predetermined threshold voltage when receiving a first external write command, and performs another threshold voltage control for writing the selected memory cell to a second predetermined threshold voltage different from the first threshold voltage when receiving a second external write command.