Abstract: A circuit arrangement for reading out data time delayed from a semiconductor memory comprises a common data input at which read data, which are read out of a semiconductor memory, are present and a data buffer FIFO for buffering the read data. The buffer FIFI comprises a plurality of FIFO modules each comprising a plurality of individual FIFO cells. Each FIFO module can be addressed via respective allocated first input and output pointers and each FIFO cell can be addressed via respective allocated second input and output pointers. The circuit arrangement further comprises a controllable read latency generator generating the first and second output pointers for driving the FIFO modules and FIFO cells with a read latency predetermined with reference to the first and second input pointers, respectively, and a common data output at which the read data are present time-delayed in dependence on the predetermined read latency.

Abstract: Disclosed is a semiconductor memory device configured to delay an input signal in accordance with a clock signal having a clock period. The semiconductor memory device comprises a reference signal generator and a delay circuit. The reference signal generator configured to generate a reference signal in accordance with the clock signal. The reference signal indicates a reference delay time representing the clock period. The delay circuit configured to delay input signal for a delay time to generate a delayed signal in accordance with the reference signal. The delay time is obtainable by multiplying the reference delay time by a positive integer.

Abstract: A source driver control device and method. The source driver control device includes a memory, a first write controller, a second write controller and a write clock signal generator. The memory receives display data corresponding to an image and stores the display data in response to a write clock signal. The first write controller generates a first write enable signal in response to a vertical back porch and a horizontal back porch. The second write controller generates a second write enable signal, which is enabled for each write cycle of storing the display data in the memory, in response to the first write enable signal. The write clock signal generator generates the write clock signal in a period in which the second write enable signal is enabled. The write cycle corresponds to a multiple of a reference write cycle. The source driver control device and method can reduce power consumed when the display data is written in the memory.

Abstract: A semiconductor memory device (M) includes a memory array (MA) having a plurality of memory cells, a redundancy array (RA) having a plurality of memory cells, a non-volatile redundancy information memory (NVR) having a plurality of memory cells for storing redundancy information, and a redundancy control unit (RU) for selecting either memory cells in the memory array (MA) or memory cells in the redundancy array (RA). In one example, the non-volatile redundancy information memory (NVR) is connected directly to the redundancy control unit (RU) by means of at least one sense amplifier (SA).

Abstract: A semiconductor memory device and a method of expanding a valid output data window are described. The semiconductor memory device includes a memory cell array and an output circuit. The memory cell array generates read data having a plurality of bits. The output circuit outputs the, read data sequentially in response to a clock signal in a normal mode. On the other hand, the output circuit selectively outputs the bits of the read data by latching bits to be tested among bits of the read data, and by electrically disconnecting bits not to be tested among bits of the read data in response to a plurality of switch control signals in a test mode. Therefore a valid data window of an output data may be expanded.

Abstract: A memory controller capable of handling precharge-to-precharge restrictions is disclosed. Upon commencement of a write operation, the location of the corresponding write precharge command is tracked from a timing standpoint. A determination is then made as to whether or not a subsequent read precharge command will collide with any pending write precharge command. In a determination that a subsequent read precharge command will collide with any pending write precharge command, the issuance of this read precharge command is delayed in order to avoid any collision; also, a specific time interval between this read precharge command and subsequent read precharge commands is maintained.

Abstract: A device including a command decoder to receive a compound command, a timer to begin operating if the compound command includes an activate command and a precharge command, the timer to begin operating at substantially the same time as the activate command is issued, and control logic coupled to the command decoder to precharge bit lines no earlier than when the timer reaches a target time period.

Abstract: A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read action, an information via the bit line, and routing, during the read action, a virtual voltage supply line to a supply potential of the memory device to supply voltage to memory cells of the memory device assigned to the bit line. The precharging device of the bit line is activated/deactivated as a function of the potential of the virtual voltage supply line.

Abstract: A precharge circuit prevents voltage dropping of a local input/output line in a semiconductor memory apparatus. The precharge circuit includes at least one pair of pull-up and pull-down precharge circuits. When a local input/output line precharge signal is enabled, a precharge voltage to be applied to each of the precharge circuits is supplied to a local input/output line and a local input/output line-bar. The pull-up precharge circuit has P-type MOS transistors, and the pull-down precharge circuit has N-type transistors. With this configuration, dropping of precharge voltage levels of local input/output lines can be prevented, thus improving reliability of the memory apparatus.

Abstract: An object is to provide a semiconductor device capable of reducing an area of the semiconductor device, reading data reliably, and simplifying replacement of data. A memory cell and a data line are controlled with a reset signal, so that data can be reliably outputted in the semiconductor device. In addition, an element of data holding unit is included, and the data holding unit includes a plurality of memory cells. The area can be reduced by using such a memory cell. A transistor is not connected to GND, thereby simplifying the replacement of data in the memory cell.

Abstract: Disclosed is an apparatus for controlling an enable interval of a signal controlling an operation of data buses which connect a bit line sense amplifier with a data sense amplifier according to a variation of an operational frequency of a memory device. The apparatus comprises a pulse width control section for changing the pulse width of an input signal depending on the operational frequency of the memory device after receiving the input signal, a signal transmission section for buffering a signal outputted from the pulse width control section, and an output section for receiving a signal outputted from the signal transmission section so as to output a first signal for controlling the signal to control the operation of the data buses.

Abstract: A first bit line is connected to a memory cell. A second bit line is connected to a dummy cell having a dummy capacitor, and supplied with an electric potential which is complementary to the electric potential of the first bit line. A sense amplifier compares and amplifies the first and second bit lines. A sense amplifier supply voltage generation circuit supplies the sense amplifier with a sense amplifier supply voltage to be used in the comparison and amplification by the sense amplifier. The sense amplifier supply voltage is supplied to a reference potential generation circuit. When data is read out from the memory cell to the first bit line, the reference potential generation circuit supplies, to the second bit line via the dummy cell, a reference potential which fluctuates with a positive correlation to the fluctuation in sense amplifier supply voltage.

Abstract: There is provided a semiconductor memory device for acceleration in burst mode. The semiconductor memory device has a burst mode for serially reading multiple bits of data in synchronization with both edges of a clock. Multiple memory blocks are geometrically arranged correspondingly to the multiple bits. An address selection circuit selects a memory cell from the memory blocks. Data read from the memory blocks is parallel transmitted to an output circuit. The output circuit first outputs data from a memory block to which data is transmitted fastest among the multiple memory blocks. The output circuit serially outputs data in the fixed order in synchronization with both edges of the clock.

Abstract: A dynamic random access memory has logically identical circuits for providing the same logical control signals. Each set of control signals can have different electrical parameters. One circuit can be optimized for high speed performance, while another circuit can be optimized for low power consumption. The logically identical circuits can include wordline address predecoder circuits, where a high speed predecoder circuit is enabled during a normal operating mode and a slower low power predecoder circuit is enabled for self-refresh operations. During self-refresh operations, the high speed circuit can be decoupled from the power supply to minimize its current leakage.

Abstract: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a shift register configured to receive an oscillation signal that is periodically enabled after a self-refresh signal is enabled, to allow a self-refresh operation to be performed, and delay the received oscillation signal by a unit self-refresh period to output a delayed oscillation signal, a period measurement start signal generator configured to receive the self-refresh signal and the oscillation signal and generate a period measurement start signal for setting a time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period, and a refresh period output unit configured to receive the period measurement start signal and the delayed oscillation signal from the shift register and generate a refresh period output signal that is enabled for a period from a time that the period measurement start signal is enabled to a time that the delayed oscillation si

Abstract: A refresh control circuit and method generates a refresh signal in response to one of a plurality of clock signals and a temperature signal. The clock signals and temperature signal may be synchronized to prevent an incomplete refresh operation at a trip point of a temperature sensor. In one embodiment, a pulse generator may generate a temperature sensor enable signal in response to the clock signals when the clock signals are synchronized. In other embodiments, the temperature signal may be latched to prevent a transition in the refresh signal during a refresh operation. The temperature signal may be latched in response to one of the clock signals or the refresh signal.

Abstract: A memory system is provided. The memory system includes a volatile memory having a number of banks, each bank having a number of rows, and a memory controller configured to direct the volatile memory to engage in an auto-refresh mode, the memory controller further configured to provide a target bank address to the volatile memory. The volatile memory is configured to perform an auto-refresh operation in the auto-refresh mode, the auto-refresh operation being performed on a target bank identified by the target bank address. Remaining banks in the plurality of banks other than the target bank are available for memory access while the auto-refresh operation is being performed on the target bank.

Abstract: After a refresh operation, a word control circuit holds the selection state of a word line selection signal line selected in each memory block corresponding to a refresh address. Further, in response to an access request, the word control circuit unselects only a word line selection signal line of a memory block selected by an external address corresponding to this access request. In each memory block, the word line selection signal line once selected is not unselected until the access request is received, so that the frequency of unselection and selection of the word line selection signal lines can be lowered. Consequently, a charge/discharge current of the word line selection signal lines can be reduced, which can reduce current consumption of a semiconductor memory.

Abstract: An eFuse data alignment verification apparatus and method are provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch units of the write scan chain preferably includes alignment data values. These alignment data values are placed in positions within the sequence of data that, if the sequence of data is properly scanned-into the series of latch units, cause the data values to be stored in the alignment latches. The logic unit receives data signals from the alignment latches and determines if the proper pattern of data values is stored in the alignment latches. If the proper pattern of data values is present in the alignment latches, then the data is aligned and a program enable signal is sent to the bank of eFuses.

Abstract: An address decoder. The address decoder includes a plurality of decoder circuits. Each decoder circuit includes a first stage including a first logic circuit having n?1 inputs, the n?1 inputs being a subset of n inputs conveyed to each decoder circuit. Each decoder circuit further includes a second stage having a second and third logic circuits. Both the second and third logic circuits receive an output provided by the first logic circuit. The second logic circuit also receives the other one of the n bits, while the third logic circuit receives its complement. The second and third logic circuits provide second and third outputs, respectively. The address decoder is configured to assert one of a plurality of address selection outputs by asserting one of the second or third outputs of one of the decoder circuits, while de-asserting both the second or third outputs of the other decoder circuits.

Abstract: An apparatus for controlling bank of a semiconductor memory includes a plurality of banks, a peripheral circuit unit that generates and outputs a bank selection signal and a first address, and a bank controller that generates a second address obtained by correcting the first address to match a bank control timing and outputs the generated second address to a bank corresponding to the bank selection signal among the plurality of banks. Since it is easy to ensure a timing margin, it is possible to completely prevent an address generation error, minimize a layout area, and reduce current consumption.

Abstract: A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array using a bitline from an adjacent, non-active subarray as a reference for a bitline in an active array.

Abstract: In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of a larger device, such as an FPGA. The word-line driver has a feed-back latch for each word-line that ensures that the word-line is not energized when that word-line is not selected for access. By controlling the feed-back latch using a decoded address bit value rather than a pre-charged enable signal as do some prior-art dynamic word-line drivers, the word-line driver prevents undesirable energizing of multiple word-lines. The word-line driver can be implemented using less layout area and less power than some analogous prior-art static word-line drivers.

Abstract: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

Abstract: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

Abstract: Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows various timing specifications to be met when they would otherwise be violated, therefore improving data integrity in the system.

Abstract: A page access circuit of a semiconductor memory device comprises a page address detecting unit configured to detect transition of a page address in response to a page address control signal so as to generate a page address detecting signal, a page control unit configured to control the page address control signal depending on transition of a sense detecting signal for notifying end of operation of a bit line sense amplifier, and a column control unit configured to generate a column selecting signal in response to the page address control signal when the page address detecting signal is activated.

Abstract: A multiple-shaft extruder comprises a core (4) with outward leading channels that can be flown through by a cooling liquid. At least two housing segments (16 to 19) are each provided with a cooling circuit with interconnected cooling bore holes (28), which can be flown through by a cooling liquid, are distributed in the peripheral direction and in an axially parallel manner, and which are located on the section of the housing segments (16 to 19) that faces the process chamber (2).

Abstract: A plurality of bone filler devices receive bone filling material from an apparatus that receives components of the bone filling material in an unmixed condition, mixes the components of the bone filling material, and dispenses the mixed components of the bone filling material through a fitting into each of the plurality of bone filler devices, all while a base supports the apparatus in an upright condition.

Abstract: The invention provides a head-mounted display to visualize a medium through a surface by displaying an image characterizing the medium under the surface provided by a profiling system and referenced in the real environment of the user. An image of the medium under the surface is projected in front of one or both eyes of a person wearing the head-mounted display, in superimposition with the real environment of the user. The head-mounted display comprises a positioning sensor, such as an inertial positioning sensor, for determining its position and orientation in the real environment. As the user moves around the medium, the image of the medium is updated to display the medium as if it could be seen through the surface. In one embodiment of the invention, the image of the medium under surface is displayed in stereoscopy, the user thereby visualizing the medium in three dimensions.

Abstract: Arrangement for arranging the measurement of external pressure in a wristop instrument, such as a sports computer, a diving computer, a wristwatch, or similar. The arrangement in the instrument comprises an instrument body (1),- at least one watertight space inside the instrument body (1), and at least one circuit board (2) situated in the watertight space. A flow path (6) is arranged through the instrument body (1) to the watertight space and this flow path (6) is closed by a membrane (7), which is permeable by a gas, but not by water; and which closes the flow path (6) watertightly. A pressure sensor (3) is situated in the watertight space that is formed.

Abstract: A time zone identifier for a geographic location is generated by receiving a request, including a first information portion in the time zone identifier that represents a time difference between a standard time and a local base time for the geographic location, and, if there exists a rule specifying when the geographic location observes daylight saving time, including a second information portion identifying the rule in the time zone identifier. Otherwise, the second information portion is not included. A computer-readable data structure for a time zone identifier includes a first attribute for the first information portion and a second attribute for the second information portion. A computer system includes a rule repository and a time zone management module.

Abstract: A watch or clock has a face which is divided along its outer perimeter into 24 one-hour increments. The face is divided along an inner perimeter into incremental indicators for portions of each hour. The watch hands are reversed relative to conventional watch or clock faces, with the length of the hour hand exceeding the length of the minute hand.

Abstract: A media playing device and a media playing method are proposed. An interface module of the media playing device is coupled with an external media device and information handshaking is established therebetween such that media contents stored in the external media device can be identified by an identifying module of the media playing device. A user interface is created by a user interface module of the media playing device, which allows a user to input an operating instruction. An information processing module of the media playing device processes media content related information according to the operating instruction inputted by the user. In addition, a charging interface of the media playing device is coupled with a charging terminal of the external media device such that a charging module of the media playing device can charge the external media device when power left in the external media device is not enough.

Abstract: A multilayer optical recording apparatus excellent in high-speed recording and long-term reliability is realized, the apparatus preventing the lowering of a speed of switching recording layers by preventing an increase in contact resistance attributable to wear of a rolling part or of a sliding part of the apparatus. In a multilayer optical recording apparatus using an electrochromic material, a rotary transformer is provided as electromagnetic induction means for supplying power from a power source to a medium.

Abstract: In a multilayer optical disc having information layers conforming to a plurality of different optical disc standards, because the type of each information layer is not recorded in the other information layers, in read and write operations by a compatible optical disc device conforming to a plurality of optical disc standards, every time the information layer being accessed changes, it has been necessary to read the type of the information layer and select a method of generating a tracking error signal adapted to the type of information layer, so access has taken time. In order to solve the above problem, in the optical multilayer disc according to the present invention, having information layers conforming to a plurality of different optical disc standards, in an area in one of the information layers, information about the other information layers is recorded. The time required to access the other information layers can be reduced by using this information to select a tracking error signal generating method.

Abstract: Payment-based audiovisual playback system characterized by comprising a microprocessor unit, primarily including storage means for storing inter alia in digital form the visual and sound information to be used, and associated, through a number of interfaces, with display means for sound playback which provide a multimedia environment. The unit is controlled by a multitask operating system including a library of integrated tools and services in the storage means. The system is also associated, through an interface, with a telecommunications modem and is connectable to an audiovisual information distribution network by a telecommunications modem and telecommunications links, the telecommunications functions also being managed by the multitask operating system.

Abstract: In one embodiment, the recording medium includes a user data area on which one or more recording ranges are allocated and a management area. The method includes receiving a command to record the data on a closed recording range. The closed recording range has no recordable position. An open recording range having a recordable position is selected from one or more open recording ranges on the user data area, and the data is recorded starting from the recordable position of the selected open recording range.

Abstract: An apparatus and a method for providing secure time, an apparatus and a method for securely reproducing contents using the secure time, and a method of securely transmitting data using the secure time. The apparatus for providing the secure time includes a clock whose time can be changed, a time difference storing unit storing a time difference between the correct time and the time of the clock, a time difference setting unit performing a time difference setting process of calculating a time difference and storing the time difference in the time difference storing unit when the time of the clock is changed, and a time providing unit providing the correct time by using the time of the clock and the time difference. Advantages of user convenience and cost savings can be obtained through the use of a single clock whose time can be freely changed by a user. A secure clock that can provide the correct time can be embodied as a software program.

Abstract: Provided is an optical information recording and reproducing apparatus for recording and reproducing information using holography by irradiating a spatial modulator with a light beam from a first laser light source, separately generating information light and reference light sharing an optical axis, and condensing the generated light beam onto the information recording medium by an objective lens including a driving unit for moving the objective lens, in which the driving unit moves the objective lens in parallel to the light beam in accordance with the incident angle of light passing through the center of the spatially modulated light beam with respect to the information recording medium. The apparatus enables a stable recording and reproduction performance operation even in the case where a relative tilt occurs between an information recording medium and an optical pickup without enlarging an apparatus.

Abstract: The invention relates to an actuator for a scanning device for scanning optical discs which has a focus lens fixed in a lens holder and a damper base permanently connected to a support. The actuator is equipped with a coil and magnet arrangement, arranged on a support, for fine positioning of the focus lens, wherein a frame is connected to the damper base with elastically flexible suspension means arranged on both sides of this arrangement and of a longitudinal axis of the actuator. It achieves the object of constructing such an actuator in such a manner that it is also suitable for small optical discs. For this purpose, the lens holder is arranged at a distance from the longitudinal axis and at the same time on a side of the actuator facing away from it and facing a receptacle for the optical discs, wherein the direction of movement of the scanning device with the actuator is located transversely to the longitudinal axis and radially with respect to the disc.

Abstract: An overhang type objective-lens actuator includes an objective lens for focusing laser light onto an optical disk, a substantially tongue-shaped lens holder formed of a magnesium alloy and having a circular opening in which the objective lens is mounted, the circular opening being provided near a front end of the lens holder, a fixed unit disposed such as to face a bottom face and a rear end face of the lens holder, a plurality of suspension wires for suspending the lens holder, the suspension wires being fixed at one end to the lens holder and at the other end to the fixed unit, a plurality of coils and a plurality of magnets for driving the lens holder in a tracking direction, a focus direction, and a tilting direction, and a plurality of damper weights bonded to an outer peripheral surface of the lens holder.

Abstract: A small-sized optical disc drive includes one voice coil motor magnet within which a tracking coil and two focusing coils are disposed such that the tracking coil straddles the two poles of permanent magnets that are adjacently disposed. The two focusing coils are disposed on either side of the tracking coil, with each of the two focusing coils being only disposed over one of the permanent magnets.

Abstract: The recording medium 12 is radiated with light beam from the second light source to obtain servo signal from the reflected light. At least one of the relay lenses 8 in the relay optical system is moved perpendicularly to the optical axis according to the servo signal to follow-up moving direction of the recording medium. The light beam from the second laser light source merges with an optical system from the first laser light source to the recording medium 12 between at least one of the relay lenses 8 and the spatial light modulator 3.

Abstract: A method of testing an optical information medium and an optical information medium testing apparatus compare a voltage of a tracking error signal generated based on return light from the optical information medium received by an optical pickup and a reference voltage set in advance and judge that a fault is present on the optical information medium when the voltage of the tracking error signal is equal to or greater than the reference voltage.

Abstract: An optical disc drive having a lens position motor (24) for control of a lens position relative to a track on a disc (10) and a second (“sledge”) motor (25) for control of the position of the first motor and of the lens radially relative to the disc. An alternating signal is generated (56) and applied to the lens position motor to modulate the control of the lens position motor. In this manner, the control loop that controls the lens position motor can have higher bandwidth and therefore greater responsiveness during rough searching or at initialization. For example, where the control circuit controlling the first motor has a lowpass filter (65) with a cut-off frequency, this cut-off frequency can be selected relative to the frequency of the alternating signal.

Abstract: A track-jump control system and method are provided. The track-jump control system applied in an optical disc drive comprises a signal generator, a protection device, a velocity estimator, and a controller. The signal generator receives the signal from the PUH and generates a tracking signal and a position signal. The protection device receives the position signal and when the position signal represents the PUH pass a predetermined position of the optical disc, the protection device generates a protection signal. The velocity estimator estimates the velocity of the PUH according to the tracking signal, and then generates a velocity signal. The controller receives the velocity signal and the protection signal, protects the velocity signal according to the protection signal, and generates a control signal to control the track-jump according to the protected velocity signal.

Abstract: Within a seek control method for moving an optical spot onto an arbitrary track, by moving the optical spot into a radial direction of an optical information recording medium, which is formed with lands and grooves, spirally, on an information recording surface thereof, calculation is made on time from staring of seek operation up to completion of pulling the optical spot onto a target track, calculating is made an amount of rotation of the optical information recording medium within that time, which is calculated in the above, determination is made on whether the pulling operation can be conducted or not within a pull-in escape region on a land/groove exchange portion of a tack on the information recording surface of the optical information recording medium, upon the amount of rotation which is calculated in the above, and a starting position of the pulling operation is changed so that the pulling operation can be executed escaping from said pulling escape region, upon basis of result of the determination, t

Abstract: A tracking control method controls an optical disk drive to access an optical disk having a plurality of groove tracks and land tracks, which are alternately interlaced with each other. The tracking control method includes the following steps. First, detecting a track position of the optical disk where the optical disk drive accesses. Then, predicting at least one distance count according to the track position. Finally, generating a switch signal for controlling the optical disk drive to use different accessing powers to access the groove/land tracks according to the distance count. Wherein the track position is located at a current track of the tracks and the distance count represents a length between a start point of the current track and a start point of a following track next to the current track.