Patents Issued in June 21, 2007
  • Publication number: 20070138471
    Abstract: A liquid crystal display device and a fabricating method thereof for securing aperture ratio are disclosed. In the liquid crystal display device, a gate line is formed. A data line crosses the gate line. A thin film transistor is provided at an intersection of the gate line and the data line. A semiconductor pattern is overlapped with the data line under the data line, and includes an active layer of the thin film transistor. A step coverage does not exist between an etched edge surface of the semiconductor pattern disposed at a lower portion of the data line and an etched edge surface of the data line.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 21, 2007
    Inventors: Kyoung Lim, Ji Jung
  • Publication number: 20070138472
    Abstract: An exemplary method for fabricating a thin film transistor (TFT) array substrate includes: providing an insulating substrate; forming a plurality of gate electrodes and a plurality of reflective patterns on the insulating substrate using a first photo-mask process; forming a gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, and a source/drain metal layer on the insulating substrate having the gate electrodes and the reflective patterns; forming a plurality of source electrodes and a plurality of drain electrodes on the doped amorphous silicon layer; depositing a passivation layer on the source electrodes, the drain electrodes and the gate insulating layer; and forming a pixel electrode on the passivation layer.
    Type: Application
    Filed: December 18, 2006
    Publication date: June 21, 2007
    Inventors: Tzu-Min Yan, Chien-Ting Lai
  • Publication number: 20070138473
    Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.
    Type: Application
    Filed: December 29, 2006
    Publication date: June 21, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Yasuhiko Takemura, Toshimitsu Konuma, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi
  • Publication number: 20070138474
    Abstract: Gate lines are formed on a substrate. A gate insulating layer, a semiconductor layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited, and the upper film and the lower film are patterned to form data lines and drain electrodes. A photoresist is formed, and the upper film is patterned using the photoresist as an etch mask to expose contact portions of the lower film of the drain electrodes. Exposed portions of the extrinsic a-Si layer and the intrinsic a-Si layer are removed, and then the photoresist and underlying portions of the extrinsic a-Si layer are removed. A passivation layer is formed and patterned along with the gate insulating layer to form contact holes exposing the contact portions of the lower film, and pixel electrodes are formed to contact the contact portions.
    Type: Application
    Filed: March 1, 2007
    Publication date: June 21, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-Gyu Kim, Sang-Soo Kim
  • Publication number: 20070138475
    Abstract: The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted, stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.
    Type: Application
    Filed: February 8, 2007
    Publication date: June 21, 2007
    Inventors: Hidehito Kitakado, Ritsuko Kawasaki, Kenji Kasahara
  • Publication number: 20070138476
    Abstract: A thin film transistor array substrate is provided. The thin film transistor array substrate includes a substrate; a gate pattern of a gate electrode and a gate line connected to the gate electrode on the substrate; a main gate insulating film formed of an organic material to cover the gate pattern; a semiconductor pattern overlapping the gate line such that the main gate insulating film is disposed between semiconductor patter and the gate line; a source/drain pattern on the semiconductor pattern. The source/drain pattern has a data line crossing the gate line with the main gate insulating film therebetween, a source electrode and a drain electrode, Here, the source electrode, the drain electrode and the semiconductor pattern define a thin film transistor disposed at the intersection between the gate line and the data line.
    Type: Application
    Filed: April 25, 2006
    Publication date: June 21, 2007
    Inventors: Gee Chae, Jae Heo
  • Publication number: 20070138477
    Abstract: A semiconductor device having a light-emitting element with excellent light-emitting characteristics is provided.
    Type: Application
    Filed: December 11, 2006
    Publication date: June 21, 2007
    Inventor: Tatsuya Honda
  • Publication number: 20070138478
    Abstract: An organic light emitting diode display may have a power supply line that is coplanar with a first pixel electrode of an organic light emitting element. The power supply line, first source and drain electrodes of a first thin film transistor (TFT), second source and drain electrodes of a second TFT, a data line, and an upper electrode of a storage capacitor constitute source/drain wire lines. In addition to the power supply line, any one(s) of or all of the source/drain wire lines may be coplanar with the first pixel electrode.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 21, 2007
    Inventors: Hyun-Chul Son, Moo-Soon Ko, Woong-Sik Choi, Ji-Yeon Baek
  • Publication number: 20070138479
    Abstract: The invention provides a light emitting device using transistors manufactured by the conventional process while reducing an area occupied by capacitors, whereby variations in luminance of light emitting elements caused by variations in gate voltage Vgs of the transistors are suppressed, and a luminance decay of the light emitting elements due to the degradation of light emitting materials and variations in luminance can also be suppressed.
    Type: Application
    Filed: February 15, 2007
    Publication date: June 21, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yu Yamazaki, Aya Anazai, Ryota Fukumoto, Mitsuaki Osame
  • Publication number: 20070138480
    Abstract: A highly reliable semiconductor display device is provided. The semiconductor display device has a channel forming region, an LDD region, and a source region and a drain region in a semiconductor layer, and the LDD region overlaps with a first gate electrode, sandwiching a gate insulating film.
    Type: Application
    Filed: February 28, 2007
    Publication date: June 21, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hideomi Suzawa, Koji Ono, Tatsuya Arao
  • Publication number: 20070138481
    Abstract: Gate lines are formed on a substrate. A gate insulating layer, a semiconductor layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited, and the upper film and the lower film are patterned to form data lines and drain electrodes. A photoresist is formed, and the upper film is patterned using the photoresist as an etch mask to expose contact portions of the lower film of the drain electrodes. Exposed portions of the extrinsic a-Si layer and the intrinsic a-Si layer are removed, and then the photoresist and underlying portions of the extrinsic a-Si layer are removed. A passivation layer is formed and patterned along with the gate insulating layer to form contact holes exposing the contact portions of the lower film, and pixel electrodes are formed to contact the contact portions.
    Type: Application
    Filed: March 1, 2007
    Publication date: June 21, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-Gyu Kim, Sang-Soo Kim
  • Publication number: 20070138482
    Abstract: A silicon carbide semiconductor device, includes: 1) a silicon carbide substrate; 2) a silicide electrode configured to be formed by depositing a contact parent material on the silicon carbide substrate in such a manner as to cause a solid phase reaction, the silicide electrode being a lower carbon content silicide electrode including: i) silicon, and ii) carbon smaller than the silicon in mol number; and 3) an upper conductor film deposited to the silicide electrode.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 21, 2007
    Inventor: Satoshi Tanimoto
  • Publication number: 20070138483
    Abstract: A conducting polymer composition containing a siloxane material of Formula (1) below and a conducting polymer, and an electronic device including a layer formed using the conducting polymer composition: where A and a are the same as described in the detailed description of the invention. The electronic device including the layer formed using the conducting polymer composition has excellent electrical characteristics and long lifetime.
    Type: Application
    Filed: July 6, 2006
    Publication date: June 21, 2007
    Inventors: Tae-Woo Lee, Yi-Yeol Lyu, Jong-Jin Park
  • Publication number: 20070138484
    Abstract: A light-emitting device is provided, which includes a substrate, a light-emitting element configured to emit light having a first wavelength, the light-emitting element having a pair of electrodes and being formed above the substrate, a metal layer interposed between the substrate and the light-emitting element and having a planar configuration, and a wavelength converting layer formed on the metal layer. The periphery of the metal layer is at least partially constituted by a plurality of projected portions and a plurality of recessed portions. The plurality of projected portions locates outside of the light-emitting element. The wavelength converting layer absorbs at least part of the light emitted from the light-emitting element and converts the first wavelength, thereby light having a second wavelength differing in wavelength from the first wavelength is emitted.
    Type: Application
    Filed: November 20, 2006
    Publication date: June 21, 2007
    Inventors: Masahiro Yamamoto, Yasushi Hattori, Naomi Shida, Kei Kaneko, Genichi Hatakoshi
  • Publication number: 20070138485
    Abstract: An exemplary flat panel display subassembly (1) includes a chassis (14), and a shielding structure (16) detachably secured to the chassis. The chassis includes a location bridge (144) at an outer surface thereof, and an opening (147) defined adjacent the location bridge.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 21, 2007
    Inventors: Xian-Lei Meng, Pong-Ping Xia
  • Publication number: 20070138486
    Abstract: An optical semiconductor element includes: a surface-emitting type semiconductor laser that emits laser light; a photodetecting element formed above the surface-emitting type semiconductor; a first electrode of a first polarity formed on the surface-emitting type semiconductor laser; a second electrode of a second polarity different from the first polarity formed on the photodetecting element; and an additional electrode that covers the first electrode and the second electrode.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 21, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yasutaka Imai, Tsuyoshi Kaneko, Atsushi Sato
  • Publication number: 20070138487
    Abstract: A semiconductor light emitting device having high reflectivity and a high electrical contact property between a light reflection layer and a semiconductor layer is provided. The semiconductor light emitting device is formed by laminating a semiconductor layer, a base layer and a light reflection layer in this order. The semiconductor layer is formed by laminating a buffer layer, a GaN layer, an n-type contact layer, an n-type cladding layer, an active layer, a p-type cladding layer and a p-type contact layer in this order. The base layer is formed on a surface of the p-type contact layer, and is made of a transition metal with Ag (silver) with a thickness of 1 nm to 10 nm inclusive. The light reflection layer is formed on a surface of the base layer, and is made of Ag with a predetermined material.
    Type: Application
    Filed: November 29, 2006
    Publication date: June 21, 2007
    Inventors: Yoshiake Watanabe, Tomonori Hino, Toshimasa Kobayashi, Hironobu Narui
  • Publication number: 20070138488
    Abstract: The invention relates to a light-emitting arrangement, having:—at least one light-emitting diode chip (1),—a multi-layer board (17) having a base (5) of a thermally well conducting material, in particular of metal, and—an electrical insulating and thermally conducting connection layer (2) between the emission surface of the light-diode chip (1) and the board (17).
    Type: Application
    Filed: November 3, 2004
    Publication date: June 21, 2007
    Applicant: Tridonic Optoelectronics GmgH
    Inventors: Stefan Tasch, Hans Hoschopf
  • Publication number: 20070138489
    Abstract: A semiconductor light-emitting device is fabricated in a nitride materials system and has an active region comprising two or more quantum well layers. Each quantum well layer is separated from a neighbouring quantum well layer by a respective barrier layer. The or each barrier layer has a thickness that is at least 13 times as great as the thickness of any one of the quantum well layers. This increases the output power of the device.
    Type: Application
    Filed: November 21, 2006
    Publication date: June 21, 2007
    Inventors: Stewart Hooper, Valerie Bousquet
  • Publication number: 20070138490
    Abstract: The present invention provides a semiconductor light emitting device capable of easily realizing stable output characteristics within a wide temperature range. The semiconductor light emitting device includes a semiconductor laser element, and a semiconductor photodiode having an absorption layer disposed on a semiconductor substrate, a second conductivity type region formed in a cap layer and the absorption layer, and a transmissive reflection film disposed on the back side of the semiconductor substrate. The semiconductor photodiode is mounted with the epitaxial layer side down, and the transmissive reflection film is irradiated with a laser beam emitted from the semiconductor laser element so that light reflected from the transmissive reflection film is used as output light, and transmitted light is received by the semiconductor photodiode and used for controlling the output of the semiconductor laser element.
    Type: Application
    Filed: December 7, 2006
    Publication date: June 21, 2007
    Inventors: Youichi Nagai, Yasuhiro Iguchi, Hiroshi Inada
  • Publication number: 20070138491
    Abstract: There is provided a nitride semiconductor light emitting device having a light emitting portion coated with a coating film, the light emitting portion being formed of a nitride semiconductor, the coating film in contact with the light emitting portion being formed of an oxynitride film deposited adjacent to the light emitting portion and an oxide film deposited on the oxynitride film. There is also provided a method of fabricating a nitride semiconductor laser device having a cavity with a facet coated with a coating film, including the steps of: providing cleavage to form the facet of the cavity; and coating the facet of the cavity with a coating film formed of an oxynitride film deposited adjacent to the facet of the cavity and an oxide film deposited on the oxynitride film.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 21, 2007
    Inventors: Yoshinobu Kawaguchi, Takeshi Kamikawa
  • Publication number: 20070138492
    Abstract: There is provided a nitride semiconductor light emitting device having a light emitting portion coated with a coating film, the light emitting portion being formed of a nitride semiconductor, the coating film in contact with the light emitting portion being formed of an oxynitride. There is also provided a method of fabricating a nitride semiconductor laser device having a cavity with a facet coated with a coating film, including the steps of: providing cleavage to form the facet of the cavity; and coating the facet of the cavity with a coating film formed of an oxynitride.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 21, 2007
    Inventors: Takeshi Kamikawa, Yoshinobu Kawaguchi
  • Publication number: 20070138493
    Abstract: A light receiving module M comprises a photodiode 1, an IC chip 2, a light permeable and electrically insulating sealing resin member 4 for sealing the photodiode 1 and the IC chip 2, a lens 43 provided at a surface of the sealing resin member 4 facing the photodiode 1, and a light impermeable and conductive coating5 for covering the sealing resin member 4 with the lens 43 being exposed. The coating 5 is connected to the ground and is made of a conductive resin, while being formed with a vertical wall 51 surrounding the lens 43.
    Type: Application
    Filed: January 24, 2005
    Publication date: June 21, 2007
    Applicant: ROHM CO., LTD.
    Inventors: Kazumi Morimoto, Nobuo Asada
  • Publication number: 20070138494
    Abstract: The invention provides a light-emitting device and a method of illumination. The light-emitting device includes one or more semiconductor layers, a reflective bottom surface, and a top surface coupled to semiconductor layer. The semiconductor layers include an active region where a primary light is generated. The relative position of the top surface, the reflective bottom surface and the active region is adjusted to substantially transmit the primary light through the sides of the light-emitting device.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 21, 2007
    Applicant: LUMILEDS LIGHTING U.S., LLC
    Inventors: Mark Pugh, Gerard Harbers, Robert West
  • Publication number: 20070138495
    Abstract: A plurality of AC_LED units are coupled and disposed on a single chip to form an AC_LED system in single chip with three metal contacts to be driven by three-phase voltage sources. Alternatively, an AC LED system in single chip with four metal contacts is also disclosed to be driven by four-phase voltage sources.
    Type: Application
    Filed: December 8, 2006
    Publication date: June 21, 2007
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ming-Te Lin, Wen-Yung Yeh, Chia-Chang Kuo, Hsi-Hsuan Yen, Sheng-Pan Huang
  • Publication number: 20070138496
    Abstract: An exemplary light emitting diode (LED) (21) includes a light emitting crystal grain (211) and a case frame (212). The case frame includes a substrate (2121) and a plurality of sidewalls (2122) extending from the substrate. The sidewalls cooperatively define a first opening (2124) therebetween opposite to the substrate. One of the sidewalls has a second opening (2125) defined therein. The light emitting crystal grain is located in the case frame. Light beams emitting from the first opening are used to illuminate a display panel. Light beams emitting from the second openings are used to meet other special demands. Therefore, the light emitting diode can meet diversified illumination demands of various modern electronic devices.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 21, 2007
    Inventors: San-Dan Zhao, Liao-Liao Zhu, Zheng-Xiao Chen
  • Publication number: 20070138497
    Abstract: A light emitting die package includes a substrate, a reflector plate, and a lens. The substrate has traces for connecting an external electrical power source to a light emitting diode (LED) at a mounting pad. The reflector plate is coupled to the substrate and substantially surrounds the mounting pad, and includes a reflective surface to direct light from the LED in a desired direction. The lens is free to move relative to the reflector plate and is capable of being raised or lowered by the encapsulant that wets and adheres to it and is placed at an optimal distance from the LED chip(s). Heat generated by the LED during operation is drawn away from the LED by both the substrate (acting as a bottom heat sink) and the reflector plate (acting as a top heat sink).
    Type: Application
    Filed: February 8, 2007
    Publication date: June 21, 2007
    Inventor: Ban Loh
  • Publication number: 20070138498
    Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.
    Type: Application
    Filed: January 30, 2007
    Publication date: June 21, 2007
    Applicant: Tessera Technologies Hungary Kft.
    Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
  • Publication number: 20070138499
    Abstract: An object of the present invention is to provide a Group III nitride semiconductor device exhibiting improved crystallinity and a good performance. The inventive Group III nitride semiconductor device comprises a substrate, and a plurality of Group III nitride semiconductor layers provided on the substrate, wherein a first layer which is in contact with the substrate is composed of silicon-doped AlxGal-xN (0?×?1). Also, the inventive Group III nitride semiconductor device comprises a substrate, and a plurality of Group III nitride semiconductor layers provided on the substrate, wherein a first layer which is in contact with the substrate is composed of AlxGal-xN (0?×?1), and the difference in height between a protrusion and a depression which are present at the interface between the first layer and a second layer provided thereon is 10 nm or more and is equal to, or less than, 99% the thickness of the first layer.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 21, 2007
    Applicant: SHOWA DENKO K.K.
    Inventor: Tetsuo Sakurai
  • Publication number: 20070138500
    Abstract: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge wiring (28) is formed between the LEDs (1) and between the LEDs (1) and electrodes (32). The LED arrays are arranged zigzag to form a plurality of LEDs (1) to produce a high drive voltage and a small drive current. Two LED arrays are connected in inverse parallel, and therefore an AC power supply can be used as the power supply.
    Type: Application
    Filed: February 12, 2007
    Publication date: June 21, 2007
    Applicants: NITRIDE SEMICONDUCTORS CO., LTD.
    Inventors: Shiro Sakai, Jin-Ping Ao, Yasuo Ono
  • Publication number: 20070138501
    Abstract: A semiconductor device has a thyristor including a first region of a first conduction type, a second region of a second conduction type opposite to the first conduction type, a third region of the first conduction type, and a fourth region of the second conduction type, in sequential junction, and has a gate electrode at the third region, wherein the second region is formed in a semiconductor substrate, and the first region is formed over the second region. A part of the region of a thyristor is thus provided with a laminate structure, whereby a reduction in element area can be achieved, and an enhanced punch-through resistance can be attained.
    Type: Application
    Filed: December 11, 2006
    Publication date: June 21, 2007
    Applicant: Sony Corporation
    Inventors: Taro Sugizaki, Motoaki Nakamura, Motonari Honda
  • Publication number: 20070138502
    Abstract: A vertical thyristor adapted to an HF control, including a cathode region in a P-type base well, a lightly-doped P-type layer next to the base well, a lightly-doped N-type region in the lightly-doped P-type layer, a Schottky contact on the lightly-doped N-type region connected to a control terminal, and a connection between the lightly-doped N-type region and the P-type base well.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 21, 2007
    Applicant: STMicroelectronics S.A.
    Inventors: Christophe Mauriac, Samuel Menard
  • Publication number: 20070138503
    Abstract: In one embodiment, a semiconductor package structure includes a plurality of upright clips having ends with mounting surfaces for vertically mounting the package to a next level of assembly. A semiconductor chip is interposed between the upright clips together with one or more spacers.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 21, 2007
    Inventors: Stephen Germain, Francis Carney, Bruce Huling
  • Publication number: 20070138504
    Abstract: A method for manufacturing a diode-connected transistor includes forming a silicon layer on a substrate, a first insulation film on the silicon layer, and a gate electrode on the first insulation film. The method also includes forming a source region, a channel region, and a drain region in the silicon layer and forming a second insulation film on the gate electrode. A source electrode and a drain electrode are formed on the second insulation film and are coupled to the source region and the drain region, respectively. The method further includes coupling the drain electrode to the gate electrode through a contact hole that is vertically above the channel region.
    Type: Application
    Filed: February 15, 2007
    Publication date: June 21, 2007
    Inventors: Keum-Nam Kim, Ul-Ho Lee
  • Publication number: 20070138505
    Abstract: In a method for making a low-defect single-crystal GaN film, an epitaxial nitride layer is deposited on a substrate. A first GaN layer is grown on the epitaxial nitride layer by HVPE under a growth condition that promotes the formation of pits, wherein after growing the first GaN layer the GaN film surface morphology is rough and pitted. A second GaN layer is grown on the first GaN layer to form a GaN film on the substrate. The second GaN layer is grown by HVPE under a growth condition that promotes filling of the pits, and after growing the second GaN layer the GaN film surface morphology is essentially pit-free. A GaN film having a characteristic dimension of about 2 inches or greater, and a thickness normal ranging from approximately 10 to approximately 250 microns, includes a pit-free surface, the threading dislocation density being less than 1×108 cm?2.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 21, 2007
    Applicant: Kyma Technologies, Inc.
    Inventors: Edward Preble, Lianghong Liu, Andrew Hanser, N. Williams, Xueping Xu
  • Publication number: 20070138506
    Abstract: A self-aligned enhancement mode or depletion mode nitride based metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first oxide layer that in comprised of gallium oxides or indium oxides compounds (30) positioned immediately on top of the nitride compound semiconductor structure, and a second insulating layer comprised of either (a) oxygen and rare earth elements, (b) gallium oxygen and rare earth elements, or (c) gallium+indium and rare earth elements positioned immediately on top of said first layer. Together the lower indium oxide or gallium oxide layer and the second insulating layer form a epitaxial oxide gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14) that is based on the nitride family of compound semiconductors.
    Type: Application
    Filed: November 17, 2004
    Publication date: June 21, 2007
    Inventor: Walter Braddock
  • Publication number: 20070138507
    Abstract: A method of fabricating an enhancement mode semiconductor device comprises providing a compound semiconductor substrate, epitaxially growing on the substrate a first portion of a buffer, the first portion including gallium arsenide (GaAs), growing a second portion of the buffer, the second portion including a high V/III ratio and high aluminum (Al) mole fraction aluminum gallium arsenide (AlGaAs), and epitaxially growing a stack of compound semiconductor layers on the buffer. An enhancement mode semiconductor device is then formed in the stack.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 21, 2007
    Inventors: Elizabeth Glass, Olin Hartin, Haldane Henry, Philippe Jamet, Lisa Zhang, Michael Pelczynski
  • Publication number: 20070138508
    Abstract: A monostable to bistable transition logic element (MOBILE)-based delayed flip-flop circuit with a non-return-to-zero (NRZ)-mode output is constructed by including a parallel connection structure of a resonant-tunneling-diode (RTD) and a HEMT (High-Electron-Mobility-Transistor) used as a data input terminal and a series connection structure of the RTD and the HEMT used as a clock input terminal.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 21, 2007
    Inventors: Hyung Tae Kim, Kwang Seok Seo
  • Publication number: 20070138509
    Abstract: An electrooptical device includes a substrate and an electronic component mounted on the substrate with an adhesive. The substrate has terminals arranged thereon and wiring lines connected to the terminals and extending in a column direction. The terminals are divided into at least one first terminal group and at least one second terminal group that does not overlap the first terminal group in the column direction. The terminals of the first terminal group are shifted from each other in a row direction so that the adjacent terminals overlap each other in the column direction. The terminals of the second terminal group are shifted from each other in the row direction so that the adjacent terminals overlap each other in the column direction.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 21, 2007
    Applicant: SANYO EPSON IMAGING DEVICES CORPORATION
    Inventor: Hiroyuki ONODERA
  • Publication number: 20070138510
    Abstract: A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased.
    Type: Application
    Filed: November 17, 2006
    Publication date: June 21, 2007
    Inventor: Hirofumi Uchida
  • Publication number: 20070138511
    Abstract: A method and system for a high current semiconductor memory cell provides a semiconductor memory cell with two current carrying structures. At least one of the current carrying structures is segmented and formed of narrow wire segments from one or more levels coupled to wider connective squares of another level. The wire segments may be a conductive material and the connective squares a refractory material. The short length wire segments may include a length less than the average grain size of the material of which they are formed.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 21, 2007
    Inventors: Anthony Oates, Denny Tang
  • Publication number: 20070138512
    Abstract: A semiconductor substrate manufacturing method, including: forming, on an active surface side of a semiconductor base material, a first semiconductor layer whose etch selectivity is higher than that of the semiconductor base material; forming over the first semiconductor layer a second semiconductor layer whose etch selectivity is lower than that of the first semiconductor layer; forming a support hole so as to expose the semiconductor base material by partially removing and opening the second and first semiconductor layers around an element region; forming a support formation layer on the active surface side of the semiconductor base material by filling the support hole and covering the second semiconductor layer; forming, through etching, an opening surface that exposes part of end portions of a support and the first and second semiconductor layers located under this support, leaving a region including at least part of a region for the support hole and the element region; forming a cavity between the second
    Type: Application
    Filed: December 14, 2006
    Publication date: June 21, 2007
    Applicant: Seiko Epson Corporation
    Inventor: Kei Kanemoto
  • Publication number: 20070138513
    Abstract: Provided is an input device capable of driving X electrodes and Y electrodes provided in a plurality of detection regions by a common X driver and a common Y driver and detecting a coordinate of an operation body in the detection regions by a simple circuit configuration. By the common X driver 11, X electrodes X1 to X6 in a first detection region 1 and X electrodes X11 to X16 in a second detection region 2 are simultaneously selected and supplied with a potential. By a common Y driver 12, Y electrodes Y1 to Y8 in the first detection region 1 and Y electrodes Y11 to Y18 in the second detection region 2 are simultaneously selected and supplied with a potential. A first detection electrode S1 is provided in the first detection region 1 and a second detection electrode S2 is provided in the second detection region 2.
    Type: Application
    Filed: December 18, 2006
    Publication date: June 21, 2007
    Applicant: ALPS ELECTRIC CO., LTD.
    Inventors: Tadamitsu Sato, Shuzo Ono
  • Publication number: 20070138514
    Abstract: An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 21, 2005
    Publication date: June 21, 2007
    Inventor: Peter Chang
  • Publication number: 20070138515
    Abstract: A dual field plate MESFET and method of forming a dual field plate MESFET are provided. The MESFET includes a gate electrode and a drain electrode, with the gate electrode and drain electrode formed on a substrate. The MESFET further includes a gate side field plate at the gate electrode and a drain side field plate in proximity to the drain electrode and extending over a burnout improvement region in the substrate.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 21, 2007
    Inventor: Thomas Winslow
  • Publication number: 20070138516
    Abstract: A semiconductor memory (26) having a plurality of memory cells (25), the semiconductor memory (26) having a substrate (1), at least one wordline (2) and first (3) and second lines (4). Each memory cell (25) of the plurality of memory cells (25) includes a fin (15) of semiconductor material, the fin (15) having a top surface (5), first (6) and second (7) opposing sidewalls and first (8) and second (9) opposing ends. The fin (15) extends along a first direction (X). Each memory cell (25) also includes a charge-trapping layer (11) disposed on the first (6) and second (7) sidewalls of said fin (15), a patterned first insulating layer (10) disposed on the top surface (5) of the fin (15), wherein the first insulating layer (10) abuts the top surface (5) of the fin (15) and the charge-trapping layer (11). Each memory cell (25) also includes a first doping region (12) coupled to the first end (8) of said fin (15) and a second doping region (13) coupled to the second end (9) of the fin (15).
    Type: Application
    Filed: December 15, 2005
    Publication date: June 21, 2007
    Inventor: Lars Bach
  • Publication number: 20070138517
    Abstract: A field-effect transistor includes a semi-insulating substrate, a source electrode, a drain electrode, a gate electrode, the electrodes being provided on the semi-insulating substrate, and a buried gate region which is provided under the gate electrode and in which an impurity is doped, wherein a concave slit is provided in the semi-insulating substrate, the slit being located between the gate electrode and the drain electrode and being adjacent to the buried gate region at the side of the drain electrode.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 21, 2007
    Inventor: Kazuki Nomoto
  • Publication number: 20070138518
    Abstract: An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.
    Type: Application
    Filed: February 16, 2007
    Publication date: June 21, 2007
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Masao Inoue
  • Publication number: 20070138519
    Abstract: The invention concerns a semiconductor component and an associated production process having a silicon-bearing layer, a praseodymium oxide layer and a mixed oxide layer arranged between the silicon-bearing layer and the praseodymium oxide layer and containing silicon, praseodymium and oxygen. It is possible because of the mixed oxide layer on the one hand to improve the capacitance of the component and on the other hand to achieve a high level of charge carrier mobility without the necessity for a silicon oxide intermediate layer.
    Type: Application
    Filed: August 20, 2004
    Publication date: June 21, 2007
    Inventor: Hans-Joachim Mussig
  • Publication number: 20070138520
    Abstract: A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 21, 2007
    Applicant: AGFA-GEVAERT
    Inventors: Luc Leenders, Michel Werts