Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.

Abstract: An apparatus and a method for producing passive components on an integrated circuit device. The integrtated circuit device has post wafer fabrication integrated passive components situated on the opposite substrate side of the device's integrated circuitry. Electrical contact pads of the passive components are configured to be coupled to the electronics package contact pads to complete the electronic package.

Abstract: A semiconductor device according to the present invention comprises a silicon substrate, a gate electrode formed on a main surface of the silicon substrate with a gate insulation film therethrough, a sidewall spacer formed so as to cover a side surface of the gate electrode and including at least two layers of a silicon oxide film as a lowermost layer and a silicon nitride film formed thereon, a source region and a drain region formed in the main surface of the silicon substrate so as to sandwich the gate electrode, a protection film formed so as to cover an end surface of the silicon oxide film without extending below said silicon nitride film, the end surface being on a side of said source region and said drain region, and a metal silicide layer formed in the source region and the drain region on a side of said protection film away from said gate electrode.

Abstract: The top ends of polysilicon gate electrodes with different gate lengths are formed so as to be equally high and lower than the top end of the side wall. A metal film is formed so as to cover the polysilicon gate electrodes, followed by silicidation by thermal treatment. Since the top ends of the polysilicon gate electrodes are formed lower than the top end of the side wall, a silicon side reaction is not accelerated even in the case of a fine gate length, and proceeds in a one-dimensional manner. As a result, full-silicide gate electrodes having a uniform metal composition ratio can be stably formed even using the polysilicon gates with different gate lengths.

Abstract: In a memory cell array are arranged a plurality of cell units having memory cells and selection gate transistors to select the memory cell. A first selection gate line includes a control gate of the selection gate transistors. A second selection gate line is formed above the first selection gate line. The first selection gate line has a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order. The first inter-gate insulating film has a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other. A contact material is formed on the first selection gate line, and electrically connects the first selection gate line and the second selection gate line with each other. The contact material is arranged on the first selection gate line on which the first opening portion is not arranged.

Abstract: An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.

Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer.

Abstract: A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (PMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

Abstract: Silicon oxide (210) is grown on a silicon region (130). At least a portion (210N) of the silicon oxide (210) adjacent to the silicon region (130) is nitrided. Then some of the silicon oxide (210) is removed, leaving the nitrided portion (210N). Additional silicon oxide is thermally grown on the silicon region (130) under the nitrided silicon oxide portion (210N). This additional silicon oxide and the nitrided portion (210N) form a silicon oxide layer (140) having a high nitrogen concentration adjacent to a surface opposite from the silicon region (130) and a low nitrogen concentration elsewhere. Another nitridation step increases the nitrogen concentration in the silicon oxide layer (140) adjacent to the silicon region, providing a double peak nitrogen profile.

Abstract: There is provided a semiconductor device which is capable of solving a problem of threshold control in CMOS transistor, accompanied with combination of a gate insulating film having a high dielectric constant and a metal gate electrode, and significantly enhancing performances without deterioration in reliability of a device. The semiconductor device includes a gate insulating film composed of a material having a high dielectric constant, and a gate electrode. A portion of the gate electrode making contact with the gate insulating film has a composition including silicide of metal M expressed with MxSi1-X (0<X<1), as a primary constituent. X is greater than 0.5 (X>0.5) in a p-type MOSFET, and is equal to or smaller than 0.5 (X?0.5) in a n-type MOSFET.

Abstract: A micromechanical sensor and a method for manufacturing same are described. A secure diaphragm restraint, independent of fluctuations in the cavern etching process due to the process technology, and a free design of the diaphragm are made possible by designing a suitable connection of the diaphragm in an oxide layer created by local oxidation. The micromechanical sensor includes, for example, a substrate, an external oxide layer formed in a laterally external area in the substrate, a diaphragm having multiple perforation holes formed in a laterally internal diaphragm area, a cavern etched in the substrate beneath the diaphragm, whereby the diaphragm is suspended in a suspension area of the external oxide layer which tapers toward connecting points of the diaphragm and the diaphragm is situated in its vertical height between a top side and a bottom side of the external oxide layer.

Abstract: This describes a starting structure and method for forming a micro-mechanical device. These devices have several uses in both government and commercial applications. The starting structure can be sold or supplied to others who will then make a final product, or it can be used directly to make a final product. An appropriate use of this starting structure is to make deformable devices useful in an inkjet printing device.

Abstract: Nanoscale acceleration and vibration sensors comprise a thin beam attached to a first substrate, being generally suspended over the first substrate by a cantilevered attachment. The thin beam functions as a second substrate for a coating that has a resistivity that varies with strain in the beam. The coating comprises an ordered array of conductive nanoparticles coupled to the substrate either by a thin polymeric layer or a columnar spacer that is a molecular species. The polymer or columnar spacers preferably have a thickness that is at least two times the diameter of the conductive nanoparticles. A circuit to measure the resistance of the coating is formed on or with the beam substrate. The sensor may deploy an array of beam having different dimensions to represent a range of resonant frequencies that can be simultaneously detected and resolved. The sensor may deploy multiple beams of the same dimensions to provide redundancy in the case of partial device failure.

Abstract: According to some embodiments, a conducting layer is formed on a first wafer. An insulating layer is formed on a second wafer. The insulating layer includes a cavity and a conducting area may be formed in the second wafer proximate to the cavity. The side of the conducting layer opposite the first wafer is bonded to the side of the insulating layer opposite the second wafer. At least some of the first wafer is then removed, without removing at least some of the conducting layer, to form a conducting diaphragm that is substantially parallel to the second wafer. In this way, an amount of capacitance between the diaphragm and the conducting area may be measured to determine an amount of pressure being applied to the diaphragm.

Abstract: An image sensor package includes a substrate having an upper surface, which is formed with a chip region and first electrodes located on the periphery of the chip region, and a lower surface. A chip is mounted on the chip region of the upper surface of the substrate. A frame layer is arranged on the upper surface of the substrate to surround the chip. Four posts are arranged on the upper surface of the substrate and are located on the angle the frame layer. A plurality of wires are electrically connected the bonding pads of the chip to the first electrodes of the substrate. A transparent layer is mounted on the four posts to cover the chip.

Abstract: An image sensor module package includes a substrate having an upper surface, which is formed with a chip region and first electrodes located on the periphery of the chip region, and a lower surface. A chip is mounted on the chip region of the upper surface of the substrate. A frame layer is arranged on the upper surface of the substrate to surround the chip. Four posts are arranged on the upper surface of the substrate and are located on the angle the frame layer. A plurality of wires are electrically connected the bonding pads of the chip to the first electrodes of the substrate. A transparent layer is mounted on the four posts to cover the chip. A lens holder is mounted on the frame layer, and is formed with an internal thread. And a lens barrel is formed with an external thread screwed on the internal thread of the lens holder.

Abstract: In a capacitor and a capacitor array configured for reducing an effect of parasitic capacitance, the capacitor array can have a matrix configuration that includes a plurality of unit capacitors. The unit capacitors include a lower electrode and an upper electrode that constitute a plate capacitor, as well as shielding structures which enclose the capacitor. The unit capacitors are connected by an upper electrode connecting line with a first direction to constitute a plurality of capacitor columns, wherein the unit capacitors are also arranged in rows, in a second direction perpendicular to the first direction, and wherein lower electrode lead lines are disposed between the capacitor columns, the lower electrode lead lines being connected to the respective lower electrodes of each of the unit capacitors.

Abstract: A backlit photodiode array includes a semiconductor substrate having first and second main surfaces opposite to each other. A first dielectric layer is formed on the first main surface. First and second conductive vias are formed extending from the second main surface through the semiconductor substrate and the first dielectric layer. The first and second conductive vias are isolated from the semiconductor substrate by a second dielectric material. A first anode/cathode layer of a first conductivity is formed on the first dielectric layer and is electrically coupled to the first conductive via. An intrinsic semiconductor layer is formed on the first anode/cathode layer. A second anode/cathode layer of a second conductivity opposite to the first conductivity is formed on the intrinsic semiconductor layer and is electrically coupled to the second conductive via.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: Light sensors in an imager having sloped features including, but not limited to, hemispherical, v-shaped, or other sloped shapes. Light sensors having such a sloped feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for absorption there.

Abstract: A spatial light modulator includes a first region and a second region. A light-absorbing layer contacts at least a portion of the second region. The light absorbing layer includes a first layer and a second layer, the second layer having a reflectivity less than about 75%.

Abstract: Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.

Abstract: A semiconductor device includes a semiconductor substrate, a first memory cell transistor, a first select gate transistor, a second memory cell transistor, a second select gate transistor, a contact plug, silicon oxide films, and plasma films which are formed as the same layer as the silicon oxide films and are provided above upper surfaces of the first and the third gate electrodes.

Abstract: An inductor integrated chip and fabrication method thereof is provided. The inductor integrated chip includes a wafer; an inductor bonded on a surface of the wafer; a circuit element formed on the surface of the wafer and coupled to a first end of the inductor; a packaging wafer connected to the surface of the wafer and packaging the inductor and the circuit element; and a connecting electrode formed on the packaging wafer and connected to a second end of the inductor. The method includes forming an inductor and a circuit element on a surface of a wafer, wherein the circuit element is coupled to a first end of the inductor; forming a connecting electrode on a packaging wafer; and packaging the inductor and the circuit element by joining the wafer and the packaging wafer so as to connect the connecting electrode with a second end of the inductor.

Abstract: A phase change memory (PCM) cell and fabricating method thereof are provided. A phase change layer is etched into a tapered structure, and then a dielectric layer on the phase change layer is planarized, until a tip of the tapered structure is exposed for contacting a heating electrode. Therefore, when the area of the exposed tip of the phase change layer is controlled to be of an extremely small size, the contact area between the phase change layer and the heating electrode is reduced; thereby the operation current is lowered.

Abstract: A semiconductor module includes: a semiconductor element (13) having a working unit (11) and a guard ring unit (12); and heat radiation members (15, 14) arranged on an upper surface and a lower surface of the semiconductor element for cooling the semiconductor element. A passivation film (20) covers the guard ring but does not cover the working unit. The upper heat radiation member (15) is made of a flat metal plate connected to the working unit without contact with the passivation film. The upper heat radiation member is connected to the lower heat radiation member (14) in the thermo-conducting way.

Abstract: Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

Abstract: Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least one chalcogenide glass layer. The invention also relates to methods of forming such a memory device.

Abstract: A semiconductor device includes a substrate, a first fin disposed on the substrate and having first and second sidewalls opposite to each other, an isolation layer surrounding the sidewalls of the first fin, and a first gate pattern crossing the first fin, extending into the isolation layer, and covering the first sidewall of the first fin. A top surface of the isolation layer adjacent the second sidewall is located substantially at or above the level of a top surface the first fin.

Abstract: A wafer processing device is disclosed that includes a processing chamber, which is surrounded by a housing, an arrangement of inlet openings within the processing chamber, which are provided to dispense a liquid, and a rotatable holding device for wafers. Whereby the wafers are disposed in a wafer carrier, which is fixed to the holding device, in which a coating of a fluoropolymer, preferably PTFE, is provided on all parts of the wafer processing device coming into contact with liquid.

Abstract: A wafer processing apparatus is fabricated by depositing a film electrode onto the surface of a base substrate, the structure is then overcoated with a protective coating film layer comprising at least one of a nitride, carbide, carbonitride or oxynitride of elements selected from a group consisting of B, Al, Si, Ga, refractory hard metals, transition metals, and combinations thereof. The film electrode has a coefficient of thermal expansion (CTE) that closely matches the CTE of the underlying base substrate layer as well as the CTE of the protective coating layer.

Abstract: A field hardened industrial device is described with a housing of the device having electrically conductive walls surrounding a cavity with an open end. An electronics assembly is adapted to fit within the cavity. The device includes a circuit card assembly, which is a multi-layered printed wiring board with pass-through electrical connections and an embedded ground plane electrically coupled to the housing to shield the electronics assembly from electromagnetic interference and to provide environmental protection to the electronics assembly.

Abstract: An apparatus and method for incorporating discrete passive components into an integrated circuit package. A metal layer is formed over a surface of a substrate. A layer of photosensitive material is then formed over the metal layer. Using standard photolithographic processing, a pattern is formed with the photosensitive material to expose at least one region of the metal layer. The remaining photosensitive material protects the underlying metal during metal etching. The substrate is then subjected to a metal etching process to remove the metal that is not protected by the photosensitive material. The remaining photosensitive material is then removed from each remaining area of the metal layer. The discrete passive components can then be attached to the formed metal lands.

Abstract: A heat fixture is adapted to support a leadframe, and the leadframe includes a die pad and a plurality of leads. The heat fixture includes a fixture body and an isolating element. The fixture body is adapted to support the leads of the leadframe. The isolating element is mounted on the fixture body and adapted to support the die pad of the leadframe, wherein the thermal conductivity of the isolating element is less than that of the fixture body.

Abstract: A semiconductor device includes a semiconductor chip and an adhesive sheet adhered to a lower surface of the semiconductor chip, the adhesive sheet including a deformation prevention layer for suppressing deformation of the semiconductor chip. The adhesive sheet includes an adhesive layer, a base layer formed under the adhesive layer, and a deformation prevention layer interposed between the base layer and the adhesive layer, the deformation prevention layer suppressing deformation of the semiconductor chip. A deformation prevention sheet is further formed on a lower surface of the semiconductor chip. Methods of forming a semiconductor device and a multi-stacked package include adhesive sheets.

Abstract: A semiconductor package which includes a plurality of leads embedded in a ceramic body, a semiconductor device electrically coupled to the leads, and a molded housing encapsulating at least the semiconductor device.

Abstract: A lead assembly including a connector connecting structure having a plurality of separable portions and a plurality of leads. Each of the leads defined that they have a first end, a second end, a lead axis defined by the first and the second end, and an offset portion disposed between the first end and the second end. The offset portion being offset from the lead axis and adapted to be displaced downwardly with respect to the lead axis and bonded to a contact. The leads are preferably integral with the connecting structure. The connecting structure may be arranged outwardly of the leads, or may include parts interdispersed between groups of leads. The groups of leads may or may not correspond to individual units incorporating a microelectronic element.

Abstract: A device with a beam structure includes a substrate, an anchor and a cavity which are provided on and over the substrate, respectively, and a beam structure which is provided on the anchor and over the cavity, extends in a first direction and includes a plurality of convex portions and a plurality of concave portions, each of the convex portions having such a stress gradient as to provide a convex warp, and each of the concave portions having such a stress gradient as to provide a concave warp. The convex portions and the concave portions are alternately repeatedly arranged.

Abstract: A semiconductor die featuring vertical rows of bonding pad structures is disclosed. The rows of bonding pad structures are located vertically in the Y direction, or traversing the width of the semiconductor die. A vertical row of bonding pad structures is located on each side of the semiconductor die while a third vertical row of bonding pad structures is located in the center of the semiconductor die. A first set of wire bonds connect each bonding pad structure located on the sides of the semiconductor die to a conductive lead structure located on a ceramic package. A second set of wire bonds connect each bonding pad structure located in the center of the semiconductor die to a lead on chip (LOC) structure located on the semiconductor die.

Abstract: In one embodiment, a semiconductor package includes a conductive slug and columnar leads in spaced relationship thereto. The columnar leads are coupled to an electronic device attached to the slug, and are exposed at least on one side of the package opposite the die attach slug. The die attach slug is further exposed to provide a package configured in a slug up orientation.

Abstract: A package includes a device and a package substrate. The device includes a plurality of electrical pads, and has a periphery that defines a footprint. The package substrate, further includes a first substrate surface to which the device is attached, a second substrate surface, and a set of electrical contacts attached to the second substrate surface.

Abstract: A stackable chip assembly is disclosed, as are different embodiments relating to same. The chip assembly preferably includes at least two substrates with components mounted on each. The substrates are preferably situated with respect to one another such that components on one substrate extend towards the other substrate and vice versa. The components of each substrate preferably extend or are interspersed between each other. Different connections between the substrates are disclosed, as well as methods of constructing such chip assemblies. In addition, a high G-force testing fixture is also disclosed for use in testing chip packages or the like.

Abstract: An electro-optical device includes a substrate, a plurality of external connection terminals provided on the substrate, an electronic component mounted on the substrate and having a plurality of terminals, and a plurality of wires that electrically connect the plurality of external connection terminals to the plurality of terminals of the electronic component. A constant-potential wire is provided in the vicinity of locations of connections of at least some of the plurality of wires with the respective terminals of the electronic component.

Abstract: In order to achieve electromagnetic and/or thermal isolation between components in close proximity to each other on a common module substrate, an alternate package and method for manufacturing the package is provided. Inventive methods utilize a grounded, metal-coated overmold for a IC module package that can provide an alternate thermal path to heat sink high power components generating excess heat energy and/or provide general electromagnetic shielding and isolation between two integrated circuits in very close proximity that are susceptible to electromagnetic interference. A dielectric layer conformably covers semiconductor dies mounted on a substrate. On some semiconductor dies, a portion of the dielectric layer is removed from the back surface of the semiconductor dies to allow direct contact between the exposed back surface of the dies and a metallization layer forming part of the overmold. This direct contact allows heat energy to be drawn away from the dies.

Abstract: A package structure with a plurality of chips stacked on each other includes a substrate, a first chip and second chip. The substrate has a dielectric layer, a metal layer having a conducting trace area and a shielding area formed on the dielectric layer, and a solder mask formed on the conducting trace area. The first chip and the second chip are electrically connected to the conducting trace area and arranged on the solder mask respectively. The first chip has a package body connected with one surface of the metal layer for arranging the first chip between the solder mask and the shielding area of the metal layer. The second chip has a package body connected with the other surface of the metal layer for arranging the second chip between the solder mask and the shielding area of the metal layer.

Abstract: A semiconductor device, includes a supporting board; and a semiconductor element mounted on a first main surface of the supporting board. The supporting board includes a first electrode formed on the first main surface, a second electrode formed on a second main surface, and an opening or notch forming part. A first electrode pad of the semiconductor element faces and is connected to the first electrode of the supporting board. A second electrode pad of the semiconductor element and the second electrode of the supporting board are electrically connected via the opening or notch forming part.

Abstract: A printed circuit board includes multiple layers on which electrically conductive traces reside, where at least two of the electrically conductive traces each has a first portion formed on one layer of the printed circuit board and a second portion formed on another layer of the printed circuit board. The printed circuit board also includes a thru-hole via that includes at least two electrically conductive portions electrically isolated from each other, such that each of the electrically conductive portions connects electrically to both the first and second portions of a corresponding one of the electrically conductive traces.

Abstract: A stack package may include a plurality of individual packages arranged in a stack. Each individual package may have a circuit substrate disposed on the upper and lower surfaces of a semiconductor chip. Through bonding wires, a lower circuit substrate may be electrically connected to the semiconductor chip, and an upper circuit substrate may be electrically connected to the lower circuit substrate. An upper package in the stack may be mechanically and electrically connected to the upper circuit substrate of a lower package in the stack through conductive bumps. The semiconductor chip may be surrounded by the upper and the lower circuit substrates, and molding resins. The individual packages may have the same conductive bump layout.

Abstract: In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.

Abstract: A composite flow board for a fuel cell is disclosed, which includes a first substrate, a second substrate and at least one third substrate. The first substrate is made of plasticized material in the form of a plate. The first substrate includes one or more concave portions spaced apart from one another. The concave portions are formed on a surface of the first substrate. The second substrate is made of well-adhesive material in the form of a framework. The second substrate includes four frames and a hollow portion. The space inside the hollow portion is used to contain the first substrate, and the first substrate is connected with the four frames. The third substrate is made of metal in the form of a thin layer. The third substrate is shaped to the concave portions, and is attached to the concave portions.