Abstract: A method, apparatus and system with a semiconductor package including a thermal interface material dam enclosing a volume of thermal interface material.

Abstract: An electronic device has a substrate, a conductive layer and a substrate mounted portion. The substrate has a circuit portion used from 60 GHz to 80 GHz. The conductive layer is provided directly on a face of the substrate that is opposite side of the circuit portion. The face having the circuit portion of the substrate is mounted face down on the substrate mounted portion. A thickness of the conductive layer is a thickness where a sheet resistance of the conductive layer is ¼ to 4 times of a resistance component of an impedance of the substrate.

Abstract: A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die.

Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.

Abstract: A semiconductor package in which heat is easily dissipated and a semiconductor chip is not damaged during a molding process, and a method of manufacturing the same. The semiconductor package with a heat dissipating structure includes a substrate, a semiconductor chip, which is mounted on the substrate and electrically connected with the substrate by bonding means, a heat slug which is adhered to the semiconductor chip and formed of a thermally conductive material, and a heat spreader partially exposed to the outside of the semiconductor package, and which is formed on the heat slug to be spaced a buffer gap apart from the heat slug.

Abstract: A printed circuit board includes at least two conductive traces, each having a first portion and a second portion. The printed circuit board also includes a cross-over section that includes two electrically conductive portions, each connecting electrically to the first and second portions of a corresponding one of the conductive traces, such that the conductive traces in their first portions lie on opposite sides of each other as they do in their second portions.

Abstract: A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

Abstract: An apparatus and method for incorporating discrete passive components into an integrated circuit package. A first surface of a substrate is coated with a material to mechanically protect the first surface. A first metal layer and then an insulating layer are formed on a second surface of the substrate. Selected areas are removed from the insulating and a second metal layer is formed over the insulating layer and the exposed metal layer. Selected areas of the second metal layer are removed to form a plurality of structures, including at least one of a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which an electronic component may be attached. An electronic component may be attached to at least one of the structures. The resulting integrated circuit die may be incorporated into an electronic package.

Abstract: Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the die is substantially parallel to the surface area of the substrate. The face of the die is aligned with at least a portion of the component layer, and terminals of the die are connected to the substrate.

Abstract: An embedded semiconductor chip structure and a method for fabricating the same are proposed. The structure comprises: a carrier board, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings in the same; a plurality of semiconductor chips received in the through openings of the carrier board. Subsequently, cutting is processed via the through trenches. Thus, the space usage of the circuit board and the layout design are more efficient. Moreover, shaping time is also shortened.

Abstract: A multi-stacked package includes a first package, a second package and a combining member. The second package supports the first package, and is electrically connected to the first package and has at least one joint hole. The combining member extends from the first package to below the second package to pass through the joint hole so that the combining member is partially exposed to improve the coherence between the first package and the second package.

Abstract: An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. An opening is formed in the protective layer to expose at least three sides of each of the paired bond pads. The protective layer includes at least one independent residual portion located in the opening and between the paired bond pads, such that an electronic component is mounted on the independent residual portion and electrically connected to the bond pads. A groove without a dead space is formed between the electronic component and the carrier, such that a molding compound for encapsulating the electronic component can flow through the groove to fill the opening and a space under the electronic component and encapsulate the at least three sides of each of the bond pads.

Abstract: Thick-film capacitors are formed on ceramic interconnect substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are fired at high temperatures.

Abstract: A semiconductor device (1; 25) has a vertical semiconductor component (2), a first metalization (8) and a second metalization (13). The second metalization (13) has an integral film with a first end (14) with a first contact area (17), an intermediate region (15) and a second end (16) with a second contact area (19). The first contact area (17) is arranged on the rear side (6) of the semiconductor component (2) and the second contact area (19) is essentially arranged in the plane of the external contact area (12) of the first metalization (8) and provides an external contact area (12). The first contact area (17) and the second contact area (19) are arranged on opposite surfaces of the film of the second metalization (13).

Abstract: A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor active region, a semiconductor contact layer, at least one metal migration semiconductor barrier layer, and a metal contact. The metal migration semiconductor barrier layer may be embedded within the semiconductor contact layer. Furthermore, the metal migration semiconductor barrier layer may be located underneath or above and in intimate contact with the semiconductor contact layer. The metal migration semiconductor barrier layer and the semiconductor contact layer form a contact structure that prevents metals from migrating from the metal contact into the semiconductor active layer during long-term exposure to high temperatures.

Abstract: An electronic device or a process of forming an electronic device can include a first electrode configured to achieve low Lbackground or include a black layer. An electronic device can include a substrate including a user surface. The electronic device can also include a first electrode that includes a first layer, a second layer, and a third layer. The second layer can lie between the first and third layers, and the first electrode can be configured to achieve low Lbackground. The electronic device can further include a second electrode lying farther from the user surface as compared to the first electrode. In another embodiment, a first electrode can include a first layer and a second layer. The second layer can set the work function of the electrode, and the second layer can be a black layer. Processes can be used to form the electronic devices.

Abstract: In a semiconductor device having a multilayer interconnection structure, wires are formed by a damascene process, at least part of electrode pads includes a first conductive layer having a region provided for an electrical connection with an external unit. Herein, the first conductive layer is formed on a passivation film that is formed a semiconductor substrate and is indispensable for the multilayer interconnection structure.

Abstract: A pad structure of a semiconductor device includes a plurality metal layers formed on a semiconductor substrate. An uppermost metal layer includes grooves.

Abstract: Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR?Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R? are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.

Abstract: The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer formed on the first inter-layer insulation layer and patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer filled into the second opening to form an interconnection line contacted to the pad.

Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

Abstract: A method for forming a metal interconnection structure in a semiconductor device is provided. In one embodiment, first and second diffusion barrier layers are sequentially formed, and then an aluminum pad is formed on the diffusion barrier layers. The first diffusion barrier layer may be made of titanium-silicon-nitride. In addition, the second diffusion barrier layer may be made of titanium, titanium-nitride, or titanium/titanium-nitride.

Abstract: A capped chip is provided which includes a chip having a front surface, a plurality of conductive features exposed at the front surface and a cap. The cap has an inner surface facing the front surface of the chip, an outer surface opposite the inner surface, and a through hole extending from the outer surface to the inner surface. A conductive interconnect extends at least partially through the through hole. The interconnect includes a conductive article which occupies a substantial portion of a volume of the interconnect and the interconnect further includes a flowable conductive medium which joins the conductive article to at least one of the plurality of conductive features of the chip or to the cap.

Abstract: A semiconductor device includes: multi-layer interconnection substrate having signal distribution interconnection and power supply line; and semiconductor circuit blocks installed on the multi-layer interconnection substrate for performing required operations. The multi-layer substrate includes: a third interconnection layer having interconnections extending in a first direction; a second interconnection layer having interconnections extending in a second direction which is different to the first direction; and a first interconnection layer having interconnections extends in a direction orthogonal to the first direction.

Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20 and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.

Abstract: A system may include a microprocessor die, an integrated circuit package substrate, and a die disposed between the microprocessor die and the integrated circuit package substrate. In some embodiments, the integrated circuit package substrate defines a first cavity, and the die is disposed at least partially within the first cavity.

Abstract: An integrated circuit package includes a semiconductor chip having a passivation layer forming the top surface of the semiconductor chip and a metal pad formed on the passivation layer and a discrete electronic device having a first terminal formed on a first surface and a second terminal formed on a second surface opposite the first surface of the discrete electronic device where the first surface of the discrete electronic device is attached to the metal pad using a conductive adhesive structure. The semiconductor chip and the discrete electronic device are encapsulated in an encapsulation material. An electrical connection is formed between the metal pad and one of a bond pad of the semiconductor chip or a package post of the integrated circuit package. In one embodiment, the metal pad is an aluminum pad and a metal line connects the metal pad to a bond pad of the semiconductor chip.

Abstract: A method of forming a contact structure and a contact structure. The contact structure includes a contact location, and contact elements disposed substantially on the contact location, at least one such contact element including a deformable center and a conducting layer covering at least a part of the deformable center.

Abstract: A semiconductor device includes a semiconductor substrate, a first metal film on a back surface of the semiconductor substrate, a second metal film on the first metal film, and a third metal film on the second metal film. The first metal film forms an alloy with a solder. The second metal film causes isothermal solidification of the solder. The third metal film improves solder wetting properties or inhibits oxidation. Further, in a method for die-bonding a semiconductor device, a specific metal is diffused into a solder, when the solder melts, to transform the solder into a high melting point alloy, thereby causing isothermal solidification of the solder. The specific metal is different from the metal of the solder.

Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

Abstract: The present invention provides a peel strength simulating apparatus which simulates peel strength between a semiconductor integrated circuit chip and a resin package bonded to each other. The apparatus includes a storage section which stores plural types of parameters. The apparatus also includes a parameter specifying section which specifies a changeable parameter whose numerical value is changeable from the plural types of parameters stored in the storage section and specifies change priorities when specifying plural types of changeable parameters. The apparatus further includes a simulating section which repeats simulation of the peel strength until the peel strength exceeding a predetermined threshold value is obtained while changing the numerical values of the specified changeable parameters according to the specified priorities.

Abstract: A power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and a functional chip including a plurality of voltage islands. The supply control and partition chip includes a plurality of first electrical connections to the functional chip including the plurality of voltage islands. The supply control and partition chip includes a plurality of second electrical connections to the substrate carrier. Power applied to predefined ones of the first electrical connections to the functional chip are selectively switched on and off by the supply control and partition chip.

Abstract: A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.

Abstract: A bonding pad structure in a semiconductor device includes a first metal layer formed over an underlying interlayer insulating film over a semiconductor substrate, a first interlayer insulating film formed over the first metal layer, first via holes formed in the first interlayer insulating film and set apart from each other at non-uniform intervals, first vias filling the first via holes and one or more residual portions of a first via layer forming the first vias, and a second metal layer formed over the first vias and said one or more residual portions of the first via layer. The residual portions are formed together with and between the first vias due to the non-uniform intervals between the first vias.

Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate, a semiconductor die with a first surface opposing the substrate and a second surface, a metal layer formed on the second surface of the semiconductor die, and a mold layer formed on the substrate. In some embodiments, the mold layer is substantially coplanar with the metal layer to improve package performance. Other embodiments are described and claimed.

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

Abstract: An electronic component, in particular an ignition coil, has an encapsulating compound which is formed by a mixture of an A component containing epoxy resin, a flexibilizator, additives, and fillers, and a B component containing at least one curing agent. The flexibilizator is formed from a material from the group of elastic thermoplastics and elastomers and is embedded in an epoxy matrix. To manufacture such an electronic component, the encapsulating compound is formed by mixing the A component with the B component, which contains at least one curing agent and optionally an accelerator, the A component being previously produced by mixing the epoxy resin with the flexibilizator, the additives, and the filler.

Abstract: The present invention pertains to an electroconductive paste for a solar cell electrode, which includes a first silver powder with a crystallite size of 58 nm, a second silver powder with a different crystallite size from that of the first silver powder, glass frit, and resin binder. The present invention also provides a solar cell having an electrode containing the aforementioned electroconductive paste.

Abstract: A method and system for generating olfactory and tactual effects in combination with the visual and auditory effects in motion pictures. When a film is being projected, olfactory signals are detected by the multi-channel device in the film projector and are transmitted to an odor-control electromagnetic valve, which sends the pressurized odor to the multi-functional emission box via pressure relief valve until the odor is released into the inside of cinema in synch with the development of the film plots. During film projection, tactual signals are detected by the multi-channel device of the film projector and are transmitted to a water-control electromagnetic valve, which sends water to a sprinkler head or a fog-spraying head to simulate the effects of raining, sneezing, and other effects in synch with the development of film plots. Tactual signals can also be used to actuate vibrators installed in audience seats to produce the effects of shaking and bumping.

Abstract: The invention provides passive aerating apparatus for accelerating the breathing or aerating process of a liquid such as wine in a vessel such as a decanter. The passive aerating apparatus comprises a gas permeable portion formed in a sidewall of the vessel. The gas permeable portion is composed of silicone, silicone hydrogel, silicone-acrylate or fluoro-silicone-acrylate. The vessel may further or alternatively be configured to substantially block ultraviolet light.

Abstract: A closed evaporative cooling tower includes a heat dissipating tube coil unit, a water supply device, an air supply device, an intake segregated flow pipe, and a discharge combined flow pipe. It is mainly to cover a porous material, which can absorb water, on the surface of metal tube in the air flow channel of the heat dissipating tube coil unit. To use a water supply device to supply water intermittently, so that water can be absorbed on the porous material. To use an air supply fan to blow air through the porous material quickly to evaporate water so as to the heat of the medium to be cooled (such as water) in the metal tube to get heat exchange effect. In addition, the porous material has moisture absorption and moisture reservation function, so water can be supplied periodically, and the secondary cooling system of traditional closed cooling tower is nit required. It has the features of energy conversation, small volume and cost reduction.

Abstract: A microchannel collimating array may be fabricated by casting an elastic sheet onto a substrate containing a plurality of pedestals. The elastic sheet may be cured, and then pulled away from the substrate, leaving the elastic sheet with a plurality of tubes at the locations of the pedestals. The plurality of tubes may collimate light incident on the elastic sheet.

Abstract: A method of in-mold coating utilizing an injection molding machine oriented to a horizontal parting line. At the beginning of the cycle the mold opens and a charge of liquid coating solution is deposited onto the lower mold insert. A ophthalmic wafer is deposited on the coating to spread it across the insert surface. The mold is closed and a pre-cure phase elapses before the thermoplastic resin is injected into the mold cavity above the wafer. The process provides coated and functionally enhanced lenses upon ejection from the molding machine.

Abstract: A method for in-mold coating of an injection molded thermoplastic lens that resides in an injection molding machine oriented to a horizontal parting line. An optical lens is initially formed by injecting molten thermoplastic resin into an edge-gated lens-forming cavity held closed under a primary clamp force. The mold is opened at a time when the lens is rigid enough to retain its shape. An unpressurized full metered charge of coating is applied onto the center of the lens. The coating is co-molded by ramping up the clamp force from zero to a secondary clamp force less than the primary clamp force to compress the coating into a uniformly thick, fringe-free layer.

Abstract: A method to produce in-mold coated lenses, and the coated lenses produced by the method. A cliché with a measured amount of thermoset acrylate-based coating solution is provided on, or adjacent to, the parting line of an injection molding machine. An inflatable silicone bladder is dipped into the cliché to pickup a thin film of coating. The bladder is transported along a vertical axis or plane or other path to press the coating against the heated mold insert. The bladder pauses while the coating pre-cures and the bladder is peeled off, leaving the coating on the mold insert. The mold is closed and a thermoplastic resin is injected into the mold cavity to form a coated ophthalmic lens.

Abstract: A composition adapted for use in an in-situ coating process for coating an optical surface for ophthalmic applications. A coating composition according to the present invention includes at least one multifunctional acrylate compound which is cured onto a heated surface with controlled coating distribution in an ophthalmic injection mold. For example, the composition may include an acrylic base cured with an initiator, e.g., t-butyl perbenzoate, and may further include at least one catalyst and at least one metal salt. An acrylic base according to the present invention may include a combination of monofunctional and/or multifunctional acrylate and/or methacrylate compounds.

Abstract: A process for removing extractables from biomedical devices, particularly ophthalmic biomedical devices, involves contacting the device with a mixture of first and second extractants. The first extractant is an organic compound having a flash point above 38° C., and the second extractant is an organic compound having a flash point below 38° C.

Abstract: A process for producing polymeric biomedical devices, such as contact lenses, involves casting a monomeric mixture including a diluent; and subsequently removing extractables from the devices by contacting the devices with the an additional volume of the diluent.

Abstract: An apparatus for releasing a molded lens from a deformable mold includes a shear ring for temporarily retaining an annular portion of the deformable mold outside a periphery of the lens and a plunger for deforming an annular section of the deformable mold within the periphery of the lens. The apparatus can be employed to release a non-hydrated hydrogel lens from a deformable mold section.