Abstract: A multi-function circuit has as single input/control pin, to which respectively different values of a control input may be applied. A multi-function signal generation section is coupled to the single input/control pin and is operative to controllably generate a plurality of respectively different functional outputs, including a decoded address bit-representative output, a soft-start oscillator signal output, and a reset output, in response to application of respectively different values of the control input.

Abstract: Transition delays in a level shift circuit are equalized by generating a first signal related to the state of the input signal, a second signal inversely related to the state of the input signal, and a third signal that is reciprocal to the second signal. Upon transition of the input signal from a high state to a low state, the third signal is selected for controlling the output until the first signal attains a high state. The first signal is selected for controlling the output when it has reached a high state after the input signal transition. The first signal remains selected upon transition of the input signal from a high state to a low state. Thus, output delays are equalized and reduced to the shortest delay.

Abstract: A semiconductor circuit comprising a vertical transistor is disclosed. A differential amplifier circuit comprises a pair of amplification transistors, wherein the pair of amplification transistors comprises a first amplification transistor adapted to receive, amplify, and output a differential input signal. The first amplification transistor is a first vertical transistor comprising a first top and a first bottom, and the first top is a first drain of the first vertical transistor and the first bottom is a first source of the first vertical transistor. The differential amplifier circuit further comprises a current source electrically disposed between the pair of amplification transistors and a second power supply to form a current path between a first power supply and the second power supply.

Abstract: A circuit device for variously controlling a current drive capacity of a semiconductor IC device as required by the user. A circuit device, capable of preventing a semiconductor IC device from failing to drive an external device, preventing an operational speed of the semiconductor IC device from being reduced, and preventing noise from being transferred to the external device.

Abstract: A current supply circuit is disclosed, which comprises a first circuit configured to generate a first current having a positive dependence with respect to a power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, a second circuit configured to generate a second current having a positive dependence greater than that of the first current with respect to the power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, and a third circuit configured to subtract the second current form the first current to generate a third current having a negative dependence with respect to the power supply voltage.

Abstract: Disclosed herein are duty cycle adjustment circuits to control the duty cycle in a clock signal. In some embodiments, a circuit is provided comprising a clock driver to drive a differential clock signal through a clock path. A feedback circuit is coupled (i) to the clock path to monitor offset in the clock signal, and (ii) to the clock driver to digitally control the clock driver offset based on the monitored clock signal offset. Other embodiments are disclosed herein.

Abstract: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

Abstract: Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.

Abstract: The phase interpolator includes two adjustable delays 30 and 31, phase comparator 32 which detects a phase difference between a signal delayed by the adjustable delay 30 and a signal delayed by the adjustable delay 31, an integrator 33 which integrates the outputs of the phase comparator 32 and multipliers 34-1 and 34-2 which set a control voltage for the adjustable delays 30 and 31. The feedback loop comprising phase comparator 32 and integrator 33 controls a delay amount of the adjustable delay 30 thereby securing a phase relation between {ACK1, ACK2} and ICK to achieve a stable ICK phase.

Abstract: This invention provides a comparator circuit which outputs a stable waveform without oscillation even if a gradient of a change of a comparison input signal is small and determines a magnitude of the comparison input signal within a predetermined threshold value regardless of the increase/decrease direction of the comparison input signal.

Abstract: A signal output circuit that can decrease the current consumption while securing the base current of an output transistor of an NPN type bipolar transistor includes an output transistor of the NPN type bipolar transistor, a ground side output control transistor of which turning ON turns OFF the output transistor, a base current supply resistive element for supplying current to the base of the output transistor, a power supply side output control transistor which is disposed between the base current supply resistive element and the base of the output transistor, a ground side current bypass transistor which turns ON and OFF in the same way as the ground side output control transistor according to the input signal so that turning ON allows the current of the base current supply resistive element to flow, and a current limitation resistive element which is disposed between the ground side current bypass transistor and the base current supply resistive element.

Abstract: A semiconductor device of the present invention includes a comparator (1) which includes two input terminals (N1), (N2), and compares the voltage values between the power supply voltage which is inputted to one side input terminal and the reference voltage which is inputted to the other side input terminal, a resister element (2) which connects the signal line (L1) which is connected the input terminal (N1) of the comparator (1) and the signal line (L2) which is the input terminal (N2) of the comparator (1), and a capacitance element (3) one end of which is connected to a power supply terminal for applying a power supply and the other end of which is connected to one input terminal of the comparator (2). Thereby, a step variation of a power supply voltage can be detected without depending on the power supply voltage before the voltage variation.

Abstract: A sampling circuit includes an input voltage source; a first switch having an input operatively connected to the input voltage source; a sampling capacitor operatively connected to an output of the first switch; an operational amplifier having an inverting input operatively connected to the sampling capacitor; a second switch operatively connected across the inverting input of the operational amplifier and an output of the operational amplifier; and a second capacitor operatively connected to the output of the first switch. The first switch has a variable parasitic capacitance, and the second capacitor has a substantially more linear capacitance than the variable parasitic capacitance and is in parallel with the variable parasitic capacitance. A combined variable parasitic capacitance and capacitance of said switch capacitor is more linear than the variable parasitic capacitance of the first switch.

Abstract: An apparatus and method for operation of a differential capacitance transducer, including generating substantially opposing polarity excitation drive signals by operation of a pair of drive signal generators, applying the excitation drive signals to a pair of sense capacitors of a differential capacitance sensor, sensing a differential capacitance at a common junction between the pair of sense capacitors; and individually controlling the drive signal generators for trimming a null bias of the sense capacitor pair at the common junction.

Abstract: A series of gate drive circuits for MESFETs are provided. The gate drive circuits are intended to be used in switching regulators where at least one switching device is an N-channel MESFET. For regulators of this type, the gate drive circuits provide gate drive at the correct voltage to ensure that MESFETs are neither under driven (resulting in incorrect circuit operation) nor over driven (resulting in MESFET damage or excess current or power loss).

Abstract: A frequency divider comprising a first flip-flop (M1, M2, M3, M4) having a first clock input (CI) for receiving a clock signal, the flip-flop further comprising a first set input (Q4) and a first non-inverted output (Q1). The frequency divider further comprises a second flip-flop (M?, M?, M?, M?) having a second clock input (CI) for receiving a second clock signal that is substantially in anti-phase with the clock signal inputted into the first clock input (CI), a second set input coupled to the first non-inverted output (Q1), a second non-inverted output (Q2) and a second inverted output (Q2), the second inverted output (Q2) being coupled to the first set input (Q4).

Abstract: The parallel circuit of an inductor L1 and a resistor R1 is connected between a power supply voltage VDD and the drain of a MOS transistor TR1 as a load, and the parallel circuit of am inductor L2 and a resistor R2 is connected between a power supply voltage VDD and the drain of a MOS transistor TR2 as a load.

Abstract: Provided is a semiconductor integrated circuit device including a reset signal generating circuit for detecting a plurality of power source voltages in which a consumption current is low and a circuit area is small. The semiconductor integrated circuit device includes the reset signal generating circuit. The reset signal generating circuit includes a plurality of voltage detecting circuits whose consumption currents are not changed even when a power source voltage significantly changes, in which output signal terminals of the voltage detecting circuits are connected with gate electrodes of a plurality of N-channel enhancement MIS transistors connected in series with an output node of a current mirror circuit to simultaneously perform an amplification and a logical operation on output signals of the voltage detecting circuits, to thereby realize low power consumption even in a wide operating voltage range and with a reduced circuit area.

Abstract: Circuits for implementing a thermometer code in a mixed-signal fashion are provided. Each of a set of outputs can be digital or analog in a transition region. The mixed signals can be used to control delay elements in a delay line for application in DLLs or PLL or clock de-skew circuits, or can be used to control voltage controlled oscillators. Two sets of driver elements are connected to the set of mixed signal outputs and in a first control state, one of the sets drives the mixed-signal outputs sequentially to off states, while in another control state, the other of the sets drives the mixed-signal outputs sequentially to on states. Any mixed-signal that is not completely driven to its on or off state will generate an analog output.

Abstract: A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.

Abstract: According to an embodiment of the present invention, a clock synchronization apparatus includes a delay-correcting circuit which is supplied with an initial voltage, compares a phase of an external clock with a phase of an internal clock output from a clock synchronizing unit, generates a control signal for correcting the phase of the internal clock on the basis of a difference between the phases of the external clock and the internal clock, and supplies the control signal to a replica delay unit of the clock synchronizing unit.

Abstract: An exemplary method for adjusting clock phase of a monitor includes: setting a reference threshold voltage, when an input voltage of image signals is greater than the reference threshold voltage, a scaler begins to receive clock phases generated by a Phase Locked Loop; dividing the clock phase into a plurality of equal periods, recording a corresponding input voltage at each point dividing two adjacent period, and setting the corresponding input voltage as a threshold voltage of the next period; recording a quantity of the clock pulses in each period; evaluating whether a period of the clock phase is a regular period according to whether the quantity of clock pulse in the period is equal to a reference quantity or not, while the input voltage is generating retardation; and selecting the input voltage of the image signals corresponding to a regular period as a threshold voltage of the scaler.

Abstract: The clock generator for semiconductor memory apparatus which includes: a first divider; a first delay unit; a second divider; a second delay unit; a duty-cycle corrector; a third divider; a third delay unit; a phase comparator; and a delay time setting unit. The clock generator for semiconductor memory apparatus exactly performs phase correction and duty cycle correction using frequency-divided clocks. Therefore, it is possible to generate reliable clocks and to improve the operational performance of a system using the clock generator.

Abstract: A duty-cycle generator including, in one embodiment, a duty-cycle adjustment circuit and a delay processor. The duty-cycle adjustment circuit is adapted to receive an input clock signal having an input duty cycle, generate first and second versions of the input clock signal having different amounts of delay, and combine the first and second versions of the input clock signal to generate an output clock signal having an output duty cycle different from the input duty cycle. The delay processor is adapted to generate at least one control signal for controlling operations of the duty-cycle adjustment circuit based on a comparison of a characteristic of the output clock signal with a corresponding characteristic of a target output clock signal.

Abstract: A flip-flop circuit arrangement having a total of four differential amplifiers (1, 2, 3, 4), which are connected to one another to produce a D flip-flop, is specified. According to the suggested principle, the two shared emitter nodes (E1, E2) of the differential amplifiers (1, 2, 3, 4) are connected via a switch pair (S1, S2) to supply potential and are activated by a differential input clock signal at a control input (CN, CP). The present flip-flop circuit is operable using especially low supply voltage (VCC) and is preferably suitable for constructing frequency dividers or shift registers.

Abstract: A flip-flop which eliminates a reset wiring to prevent complication of a wiring in an LSI or to increase the number of channels used for a signal wiring, an integrated circuit using the same, and a flip-flop resetting method, are provided. The flip-flop performing a reset operation by detecting a change in a power supply voltage includes a state retaining node that stores a HIGH level voltage or a LOW level voltage, and a reset signal generation circuit that detects a change in a power supply voltage exceeding a predetermined value to generate a reset signal for resetting a data storing state of the state retaining node.

Abstract: A flip-flop device for storing and outputting a data value includes a controllable memory element configured to be open as a function of a control pulse, a feedback means for comparing a data value present at the memory element and the data value output by the memory element, and for outputting a comparison signal, and a control pulse generator for generating the control pulse as a function of the comparison signal, so that the control pulse generator is put in an activated state when the comparison signal is high, so as to then, in the activated state, open the memory element in response to a clock event. The memory element will then be closed again when the comparison signal indicates that the same values are present at the output and at the input of the memory element.

Abstract: A circuit arrangement including a data input for applying a data signal, a set input for applying a set signal and an output for providing an output state. The output is coupled to the data input and to the set input in such a manner that the output state provided is set only when an input state of the data signal and the output state differ from one another and the set signal changes to a prescribed state.

Abstract: A True Single Phase Clock flip-flop is configured to operate in an evaluating and a hold mode. The flip-flop comprises an input stage having an input node and a first output node. The flip-flop further comprises a middle stage having a second output node and an output stage having a third output node. The flip-flop further comprises a reset functional block which is switchable between an activated and a deactivated mode. Said reset functional block resets said flip-flop when activated and is configured to synchronous exit out of reset when switched from its activated to its deactivated mode so that an output signal of said flip-flop is only up-dated when said flip-flop changes to its next evaluating mode.

Abstract: An integrated circuit includes clock deskew circuitry. The deskew circuitry includes multiple loop circuits to align a received clock with a data eye, and to reduce the effects of clock drift caused by voltage and temperature variations.

Abstract: Embodiments relate to a delay chain that may reduce skew between input and output signals. In embodiments, the delay chain may include N inverters connected to each other in series between an input terminal and an output terminal (N is a positive even number integer). A gate of the PMOS transistor of an inverter arranged in the odd order from the input terminal of the N inverters may be connected to the input terminal commonly. A gate of the NMOS transistor of the inverter arranged in the even order from the input terminal of the N inverters may be connected to a reverse input terminal (IN/) commonly, which outputs a reverse signal of the input terminal.

Abstract: Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.

Abstract: A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock destination nodes via a clock network. Clock distribution may be disabled as needed to save power. The first feedback loop is active irrespective of whether clock distribution is enabled. The delay through the clock network may drift due to temperature and supply-voltage fluctuations, which introduces phase errors in the distributed clock signals. A second feedback loop is activated when clock distribution is enabled to compensate for this drift.

Abstract: A semiconductor device can accurately control the timings of various signals used in the semiconductor device using a simple configuration.

Abstract: A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit which combines a rising clock with a signal to be generated in response to a rising output enable signal and a falling clock to generate a rising data output clock, and a falling data output clock generating unit which combines the falling clock with a signal to be generated in response to a falling output enable signal and the rising clock to generate a falling data output clock.

Abstract: A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g.

Abstract: A level shift circuit operates normally when amplitude of input signal is small and amplitude of output signal is large. First and second terminals receive an input signal and its complementary signal having a first amplitude. Third and fourth terminals output an output signal and its complementary signal having a second amplitude, which is larger than the first amplitude. Output circuit comprises first and second transistors of first polarity respectively connected between first power supply and fourth and third terminals, respectively. Third and fourth transistors of second polarity, respectively, are connected between second power supply and fourth and third terminals, respectively, having control ends connected to the third and the fourth terminals, respectively. First current control circuit controls so that a current driving the fourth terminal flows through the first transistor according to the input signal and the complementary signal of the output signal.

Abstract: Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

Abstract: A quadrature mixer circuit and an RF communication semiconductor integrated circuit capable of suppressing variations in secondary distortion while reducing the current consumption are provided. In a quadrature mixer circuit, even if local signals different by 90 degrees inputted to the bases of I transistors and Q transistors have large amplitudes, interference is suppressed by I resistors, Q resistors, and capacitors. Also, since the capacitors are provided, changes in bias current values can be suppressed. Accordingly, variations in secondary distortion can be suppressed. Furthermore, the capacitors combine current outputs of a differential circuit formed of I transistors and the resistor and a differential circuit formed of Q transistors and the resistor. Therefore, current consumption can also be reduced.

Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.

Abstract: Electronic circuits use low-cost depletion-mode JFET to serve as power switch. Since depletion-mode JFET has smaller conductive resistance and is majority carrier device, the energy loss is less when current flows through the depletion-mode JFET, and faster switching speed is obtained, thereby enhancing the efficiency of the electronic circuits.

Abstract: A temperature detection circuit includes a temperature dependent voltage generation circuit for generating a temperature dependent voltage VR, a bandgap circuit for generating a temperature independent voltage VBG, and a comparator for comparing the temperature dependent voltage VR generated in the temperature dependent voltage generation circuit with the temperature independent voltage VBG generated in the bandgap circuit, and based on the above comparison result, outputting a temperature detection signal which indicates the high-low relationship between the temperature dependent voltage VR and the temperature independent voltage VBG.

Abstract: The invention relates to integrated electronic circuits, and notably to those comprising analog functions. The invention relates more particularly to a starter circuit designed to ensure the automatic start-up of a biasing circuit following an interruption in the operation of the latter.

Abstract: To save power consumption in a semiconductor integrated circuit 2A increased due to a leak current caused by a variation in a manufacturing process, temperature, and a power supply voltage. A semiconductor integrated circuit 2A, a leak current detection circuit 3, a comparison operation circuit 4 and an applied voltage output circuit 5A are provided. The semiconductor integrated circuit 2A has a circuit body 21 including a plurality of functional MOSFETs for performing predetermined functional operations, and a monitor circuit 22A including a plurality of monitor NMOSFETs 23 for monitoring properties of the functional MOSFETs. The leak current detection circuit 3 detects leak data corresponding to leak currents from the monitor NMOSFETs 23, and outputs the detected leak data. The comparison operation circuit 4 extracts, from a plurality of pieces of leak data, one piece of leak data minimizing a leak current in the circuit body 21, and outputs the extracted leak data as applied voltage data.

Abstract: Through operated alternately between a charging phase and a discharging phase, a charge pump converts an input voltage source into a drive voltage for being supplied to a light emitting diode. A current setting unit determines a reference current. A current regulating unit has a current regulating terminal and a feedback detecting terminal. The current regulating terminal is coupled to the light emitting diode so as to control a current flowing through the light emitting diode to be proportional to the reference current. The feedback detecting terminal provides a feedback signal representative of a current regulation characteristic voltage. Based on a difference between the feedback signal and a reference voltage source, an error amplifier generates an error signal. A variable resistance unit is coupled between the input voltage source and the charge pump for adjusting a variable resistance in response to the error signal.

Abstract: A multi-mode charge pump drive circuit has a multi-mode charge pump, a switch control circuit, a current regulation circuit, an error amplifier, a variable resistance unit, and a mode selection circuit. The multi-mode charge pump is operated with a plurality of modes, each of which provides a different multiplicative ratio for converting an input voltage source into a drive voltage. The switch control circuit applies a switch control signal to the multi-mode charge pump. The switch control signal has a slew rate of edge for determining a transition span of the interchange between charging and discharging phases. The mode selection circuit controls the multi-mode charge pump to selectively operate with one of the plurality of modes. When the mode selection circuit changes the mode of the multi-mode charge pump, the mode selection circuit applies a mode change signal to the switch control circuit so as to reduce the slew rate of edge.

Abstract: A charge pump is disclosed. The charge pump comprises a plurality of first voltage boosting circuits (VBCs), each comprising a first output node and a precharge circuit adapted to precharge the first output node, and at least one second VBC connected in series with the plurality of first VBCs, wherein each of the at least one second VBC does not comprise any precharge circuit.

Abstract: A voltage generator includes: a pumping voltage detecting section configured to detect a level of a pumping voltage in accordance with a reference voltage, that activates a pumping enable signal when the detected level of the pumping voltage is higher than a first voltage, while activating a power source voltage drive signal when the detected level of the pumping voltage is lower than the first voltage. A pumping section generates the pumping voltage through a pumping operation when the pumping enable signal is active. A power source voltage driving section generates the pumping voltage at a level of an external power source voltage when the power source voltage drive signal is active.

Abstract: A pull-out lower limit voltage for setting a voltage level when the gate voltage of the charge transfer transistor is pulled out is supplied to a reset circuit. In order to secure the breakdown voltage margin of the transistor and the capacitor used in a booster cell, a voltage which is not necessarily constant is used as the pull-out lower limit voltage. Accordingly, it is possible to provide a stabilized booster circuit in which an optimal gate voltage level of the charge transfer transistor can be set, overcharging can be suppressed, and the recovery time of the booster circuit can be shortened.

Abstract: A conventional charge pump circuit requires a step-up circuit or the like for turning on or off a transistor. Therefore, it has a problem of an increase in circuit scale, which leads to increases in circuit area and power consumption. One feature is to provide a charge pump circuit including a first transistor, a switch, a first capacitor, a second capacitor, and an inverter, in which one electrode of the first transistor is connected to a first potential, an output side of the inverter is connected to the other electrode of the first transistor and one side of the switch through the first capacitor, the other side of the switch is connected to a second potential through the second capacitor.