Abstract: An integrated circuit temperature sensor includes a sensing circuit operable to determine whether the integrated circuit is currently exposed to one of a relatively low temperature or a relatively high temperature. A selection circuit operates to select a measured voltage across the base-emitter of a bipolar transistor of the integrated circuit if the sensing circuit indicates that the integrated circuit is currently exposed to the relatively low temperature or, alternatively, select a measured delta voltage across the base-emitter of the bipolar transistor of the integrated circuit if the sensing circuit indicates that the integrated circuit is currently exposed to the relatively high temperature.

Abstract: A disclosed constant voltage power supply circuit (1) has an input terminal (Vdd), an output terminal (Vout), a constant voltage power supply unit (2) that generates a constant voltage (Vo1) with a ripple voltage (Vri), and a ripple removing circuit unit (3) for removing the ripple voltage so that a constant voltage (V1) without the ripple voltage is output at the output terminal (OUT). The ripple removing circuit unit comprises a resistor (R1) connected between the constant voltage power supply unit and the output terminal; a ripple voltage detection circuit unit (5) for detecting the ripple voltage and outputting a signal depending on the detected ripple voltage; and a current circuit unit (6, 7) for receiving the signal from the ripple voltage detection circuit unit and supplying a current (io1) to the output terminal or absorbing a current (io2) from the resistor in response to the received signal, so as to cancel the ripple voltage at the output terminal.

Abstract: A method for providing an electrical reference in a circuit includes determining reference control information at a master reference circuit, distributing the reference control information to one or more controlled reference circuits, and, from at least some of the controlled reference circuits, generating one or more electrical references according to the reference control information received at the controlled reference circuit.

Abstract: There is provided a band gap reference voltage generation circuit capable of reducing wake up time during transition from an idle mode to a normal mode and further capable of removing the RF noise of an output voltage.

Abstract: A semiconductor device is disclosed which can perform a stable data inputting operation by overdriving a terminal supplying an internal voltage used as a drive voltage for a write driver such that the internal voltage is maintained in a predetermined range irrespective of a continuous write operation. The semiconductor device includes an internal voltage generator which generates an internal voltage corresponding to a predetermined reference voltage, and outputs the generated internal voltage to an internal voltage supply terminal, an overdriver which overdrives the internal voltage supply terminal for a predetermined period of time in response to an enable state of a control signal, the control signal being enabled in a write operation, and a write driver which is enabled in response to the control signal, to drive data transferred via a global data bus line using a voltage supplied from the internal voltage supply terminal, and to output the driven data to a local data bus line.

Abstract: A CMOS reference voltage source comprises first and second circuit branches connected in parallel between supply terminals, so that the current in one branch is mirrored in the other, and vice versa. The first circuit branch includes a series connection of a first transistor (MP1) of a first conductivity type, a first transistor (MN1) of a second conductivity type and a second transistor (MN2) of the second conductivity type. The second circuit branch includes a series connection of a second transistor (MP2) of the first conductivity type, a third transistor (MN3) of the second conductivity type and a fourth transistor (MN4) of the second conductivity type. The reference voltage is provided at an interconnection node between the third and fourth transistors (MN3, MN4) of the second conductivity type. No resistors or bipolar devices are needed so that a standard CMOS process can be used.

Abstract: A general purpose of the present invention is to stabilize a filter circuit to desired characteristics without increasing its circuit scale. An active filter unit includes a current control unit, a first gm-C filter unit, and a subsequent circuit. Using a signal output from a central control unit as an input, the current control unit outputs adjustment currents for adjusting gm values, corresponding to respective transconductance amplifiers, to the first gm-C filter unit. The subsequent circuit includes a load capacitance which is composed of an active element such as a transconductance amplifier. The first gm-C filter unit includes the plurality of transconductance amplifiers and a control unit which controls the gm values of the transconductance amplifiers. It limits the band of the signal output from a first filter signal selection unit, and outputs the result to the subsequent circuit.

Abstract: A differential amplifier circuit includes a first load coupled to a first reference potential, a first MOS transistor having a drain node coupled to the first load, a second load coupled to the first reference potential, a second MOS transistor having a drain node coupled to the second load, a first constant current source coupled between a second reference potential and the source nodes of the first MOS transistor and the second MOS transistor, a third MOS transistor having a source node coupled to the first load, a fourth MOS transistor having a source node the second load, and a second constant current source coupled between the second reference potential and the drain nodes of the third MOS transistor and the fourth MOS transistor, wherein the first and second MOS transistors are of a first conduction type, and the third and fourth MOS transistors are of a second conduction type.

Abstract: A transconductor for receiving a differential voltage signal and outputting a differential current signal, includes two transconductors for receiving the differential voltage signal and outputting a single-end current signal. An inversion input terminal of one of the two transconductors is connected with a non-inversion input terminal of the other. The transconductor outputs a current signal output from each of the two transconductors as the differential current signal.

Abstract: Provided is a chopper amplifier circuit capable of reducing an offset voltage of a sensor bridge and temperature characteristics of the offset voltage. An offset adjusting voltage generation circuit for generating a voltage equal to an offset voltage of a sensor bridge and an offset temperature characteristics adjusting voltage generation circuit for generating a voltage having temperature characteristics equal to those of the offset voltage are provided. These output voltages are chopper-modulated and subtracted from a chopper-modulated output signal of the sensor bridge.

Abstract: The present invention discloses a method for reducing switching interference in a switching amplifier. The switching amplifier includes a first half circuit having a first modulator and a first driver circuit, a second half circuit having a second modulator and a second driver circuit, a first reference wave generator for a first reference wave, and a second reference wave generator for a second reference wave. A first input signal and a second input signal are inputted to the first modulator and the second modulator, respectively. A first modulated signal and a second modulated signal are generated and inputted to the first driver circuit and second driver circuit, respectively. There is a time delay between the switching points, wherein the time delay is large enough to avoid mutual interference. Therefore, distortion of the output signal can be eliminated while the input signals are small.

Abstract: A switching amplifier of the invention boasts of an enhanced SN ratio in its output and an increased amplitude limit value in its input signal. The switching amplifier has a quantized signal generating section that converts an input signal to generate a quantized signal in the form of a PDM or PWM signal and a constant-current-outputting current amplification section that current-amplifies the quantized signal outputted from the quantized signal generating section. The quantized signal generating section and the current amplification section are formed by the same process. Another switching amplifier of the invention is inexpensive and is not affected by voltage fluctuations in the supply voltage.

Abstract: A device is disclosed that includes an amplification part for a linear transmitter, the amplification part being configured to amplify a transmission signal in accordance with a supply voltage control signal; a generation part configured to generate a power supply signal showing the level of the transmission signal; and a control part configured to output the supply voltage control signal based on the power supply signal. The control part includes a storage part configured to store a series of values of the power supply signal belonging to a time range including a certain point of time; and an output part configured to output a maximum one of a predetermined number of values of the series of values of the power supply signal as the supply voltage control signal at the certain point of time.

Abstract: A double reference wave modulation scheme for filterless power amplifiers is disclosed for reducing EMI and common mode voltages. In the filterless power amplifier, differential outputs for driving load impedance are feedback and corrected based on input audio signals. Reference wave generators generate reference waves. A control logic results pulses in the pair of differential outputs in response to a clock signal or a reference voltage and a cross relationship between the input audio signal and the first and second reference waves. Pulses of one of the differential outputs are not overlapped with pulses of the other of the differential outputs for eliminating common mode noises of the power amplifier.

Abstract: A differential cascode amplifier is disclosed that includes in each branch two transistors connected to form a cascode circuit, and has a cross-compensation (neutralization) with at least one pair of capacitors for compensating a parasitic capacitance of a transistor of each branch, wherein in each case, one capacitor of the pair is equal to the parasitic capacitance of the transistor of the associated branch.

Abstract: In an embodiment, a wireless device receiver chain includes a mixer with a common-gate common-source (CGCS) input stage. Differential signals from an off-chip matching network may be input to the CGCS input stage of the mixer, which downconverts the signals to baseband or some intermediate frequency. The input stage includes a pair of NMOS transistors in a common-gate configuration and a pair of PMOS transistors in a common-source configuration. A potential advantage of the CGCS input stage over the existing CGO transconductance stage configuration is that by adding a common-source stage through the PMOS differential-pair, the transconductance gain is decoupled from the high Q matching network.

Abstract: 1st to nth pairs of transistors (n=an odd number) are connected in parallel, and each pair of transistors has an upper transistor and a lower transistor connected in series. A point between the upper transistor and the lower transistor of a preceding pair of transistors is connected to a gate of the lower transistor of a subsequent transistor, and the point between the upper transistor and the lower transistor of nth pair of transistors is connected to the gate of the first lower transistor. A capacitor is inserted between the lower transistor and a direct power source. A current regulating circuit connected to gates of the upper transistors, wherein the current regulating circuit supplies a gate voltage to each gate of the each upper transistor.

Abstract: There are four differential pairs, where each has first and second legs. The first pair is to receive a first data signal at its first leg, and a second data signal at its second leg. The second pair is to receive a first offset signal at its first leg, and a second offset signal at its second leg. The third pair is to receive the first data signal at its first leg, and the second offset signal at its second leg. The fourth pair is to receive the first offset signal at its first leg, and the second data signal at its second leg. Other embodiments are also described and claimed.

Abstract: An amplifier circuit (100) includes a driver stage ( ) 120 with at least an active device (140) for pre-amplification and output of a pre-amplified signal; and an output stage (160) with at least an active device (180) for further amplification of the pre-amplified signal and output of an amplified signal. A phase shifter (155) shifts the phase of the pre-amplified signal. A detector (190) measures levels of forward and reflected parts of the amplified signal, and a gain and phase control circuit (145) independently and selectively controls and adjusts the phase shifter (155) for optimal amplifier performance and minimal difference between the forward and reflected signals. The gain and phase control circuit also independently and selectively controls and modifies the gain of the active devices (140, 180) of the driver and output stages (120, 160) as a function of the levels of the forward and reflected signals to substantially maintain constant linearity of the amplifier circuit (100) with load variations.

Abstract: An analog multistage amplification circuit for keeping the total gain of analog amplifiers constant while automatically controlling gain of the amplifiers in accordance with an input signal level and improving the S/N ratio of the output signal. The amplification circuit includes an input stage amplifier, an output stage amplifier, a filter connected between the input and output stage amplifiers, an auto gain control circuit for generating a control signal for controlling the gain of the input stage amplifier based on the output signal of the input stage amplifier so that the output signal has a maximum level, and a first gain adjustment circuit for generating an adjustment signal for adjusting the gain of the output stage amplifier so that the total gain of the input and output stage amplifiers is kept constant in accordance with the control signal of the auto gain control circuit.

Abstract: The present invention relates to a power amplifier device having a power amplifier, and an object of the invention is to enable efficient use of the power amplifier without causing any problems in the operation of the power amplifier.

Abstract: A radio frequency power amplifier 1 includes a former-stage transistor 2, a latter-stage transistor 3, and an inter-stage matching circuit 4 for connecting the former-stage transistor 2 and the latter-stage transistor 3. The inter-stage matching circuit 4 includes a high-pass filter circuit including a transfer line m1, a capacitor C1 and a capacitor C2; and a transfer line m2 with which a passage phase of a secondary harmonic signal is 15 degrees or greater.

Abstract: A selective amplifier is disclosed that includes a first transistor, which has a first emitter, a first base, and a first collector, a second transistor, which has a second emitter, a second base, and a second collector, and a matching network. The first transistor is connected in the emitter circuit and the input signal acts on the first base of the first transistor. The second transistor is connected in the base circuit and the output signal can be tapped at the second collector of the second transistor. The matching network is connected directly to the first collector of the first transistor, and the matching network is connected directly to the second emitter of the second transistor.

Abstract: A monolithically integrated microwave frequency high power amplifier device comprises a plurality of transistors connected in a load modulation configuration wherein the number of the transistors that is operational depends on the drive level. The transistors have each a finger type layout, where fingers from different ones of the transistors are interleaved. The sources of the plurality of transistors are typically interconnected, whereas the gates of the transistors have separate connections for connection to separate package leads. Similarly, the drains of the transistors have separate connections for connection to separate package leads. Advantageously, an LC-based passive network performs a power combining operation of the amplifier device.

Abstract: Devices and methods for processing signals using a Burst-Mode TIA that meets EPON and GPON specifications are disclosed herein. A signal provided by a power detector is processed with the appropriate gain by using a gain selector which includes a feedback circuit to choose the gain internally, thereby eliminating the need for an external control. Further embodiments of the invention include power detectors featuring a low-pass filter, a peak detector, and/or an envelope detector. Further embodiments of the invention include a Freeze function circuit for maintaining a current gain. Further embodiments of the invention apply appropriate gains when bursts with substantially different power levels are received consecutively, and prevent the gain from being changed during a burst. In this method, a two-pole low-pass filter with an undamped response function is used.

Abstract: A method of generating a correction signal for a voltage controlled oscillator (VCO) includes receiving a first signal in a correction current generator, changing a state of a first error signal substantially simultaneously with a first changing state of the first signal, receiving a second signal in the correction current generator, changing a state of a second error signal substantially simultaneously with a first changing state of the second signal, changing the state of the first error signal substantially simultaneously with a second changing state of the second signal, changing the state of the second error signal substantially simultaneously with a second changing state of the first signal, combining the first error signal and the second error signal to generate the correction signal substantially equal to a difference between the first error signal and the second error signal and applying the correction signal to a loop filter coupled to a correction signal input of the VCO.

Abstract: A plurality of control voltages V1 to V3 are sequentially applied to a VCO 5 so as to obtain, for each of these control voltages, the operating reference voltages Vref1 to Vref3 for the variable capacitor elements VC51 to VC56 with which the difference between the oscillation frequency of the VCO 5 and the target frequency is minimum. With this operation, the frequency synthesizer of the present invention can not only set the oscillation frequency of the VCO 5 for a single control voltage to a desirable value but also set the control sensitivity at the oscillation frequency of the VCO 5 with varied control voltage to a desirable value.

Abstract: A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

Abstract: A klystron has a plurality of electron beam paths and plural damped disc-shaped cavities. The plurality of electron beam paths cut the cavities and the Klystron amplifier further comprises an annular input cavity and an annular output cavity disposed around the substantially circular external periphery of respective disc-shaped cavities, and in communication with it. The output cavity is arranged to receive RF power from the electron beams, wherein the cavities are arranged to support one of a single resonant rotating wave in a whispering-gallery mode, and a single resonant standing wave in a whispering-gallery mode.

Abstract: An atomic frequency acquisition apparatus includes: a cell enclosing atomic gas therein; a laser light source that oscillates a laser light that enters the cell and excites the atomic gas; and a photodetecting section that detects the laser light that has passed through the cell, wherein the cell has at least a laser light reflection section inside thereof.

Abstract: Variable-frequency oscillators incorporating thin-film bulk acoustic resonators (FBARs) are described. In one aspect, a variable-frequency oscillator includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes a first film bulk acoustic resonator that has a first resonant frequency. The second oscillator circuit is coupled to the first oscillator circuit and includes a second FBAR that has a second resonant frequency different from the first resonant frequency. At least one current source is coupled to the first and second oscillator circuits and is operable to supply a total current. A bias circuit is operable to apply to the first and second oscillator circuits respective biases that control apportionment of the total current to the first and second oscillators.

Abstract: An RC oscillator integrated circuit includes: an active current mirror connected to an external resistor, for receiving a current signal corresponding to a voltage signal applied to the external resistor, performing 1/N-times division of the received current signal according to an input clock signal, and generating a 1/N-times current signal; an oscillation circuit for generating an output voltage corresponding to a charging- or discharging-operation of a capacitor via a current path formed by the active current mirror; a feedback switching circuit for controlling a charging- or discharging-path of the capacitor by a feedback of an output signal Vo of the oscillation circuit; and a divider for generating not only a first clock signal capable of driving the active current mirror according to the output signal of the oscillation circuit, but also a second output clock signal having a compensated mismatch of the active current mirror.

Abstract: There is provided an LC resonance type oscillation circuit with a wide frequency variable range with a small variation of Q and capable of reducing a chip size due to no external parts required, and a communication semiconductor circuit device (high-frequency IC) having the oscillation circuit. In the LC resonance type oscillation circuit, a capacitance element and a switch element are connected in parallel between both terminals of a secondary side inductance element which is placed facing an inductance element constituting the LC resonance circuit and is connected by mutual induction to the inductance element. It is designed so that an equivalent inductance increases as the capacitance element is connected between the both terminals of the secondary side inductance element in a state where the switch element is turned OFF, and that the equivalent inductance decreases as the both terminals of the secondary side inductance element are short-circuited in a state where the switch element is turned ON.

Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitor element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.

Abstract: An amplifier receives an amplitude signal of a polar modulated signal at a base terminal of a transistor and receives a phase modulated carrier signal of the polar modulated signal at the base terminal of the transistor. The amplifier combines the amplitude signal and the phase modulated signal to produce a full complex waveform at a collector terminal of the transistor.

Abstract: A data transmitter uses a transmission line including a ground conductor (305), a signal conductor (201), and an insulating material (3) which insulates them from each other. The insulating material includes a dielectric (320) exhibiting a nonlinear relationship between a generated electric field and dielectric polarization. The effective reactance per unit length of the transmission line changes depending on the signal voltage. Data is transmitted between integrated circuits (102) via the transmission line, achieving data transmission at a higher speed than a conventional one.

Abstract: Systems and methods for generating a high voltage pulse. A series of voltage cells are connected such that charging capacitors can be charged in parallel and discharged in series. Each cell includes a main switch and a return switch. When the main switches are turned on, the capacitors in the cells are in series and discharge. When the main switches are turned off and the return switches are turned on, the capacitors charge in parallel. One or more of the cells can be inactive without preventing a pulse from being generated. The amplitude, duration, rise time, and fall time can be controlled with the voltage cells. Each voltage cell may also includes a balance network to match the stray capacitance seen by each voltage cell. Droop compensation is also enabled.

Abstract: An integrated circuit module comprising integrated coupling transmission structures protruding from the main body of the integrated circuit with extra substrate material removed around and/or under the coupling transmission structures.

Abstract: An embodiment of the present invention provides a power amplifier, comprising tunable impedance matching circuit including a plurality of tunable dielectric varactors and a DC voltage source interface capable of providing voltage to said plurality of saud tunable dielectric varactors.

Abstract: An electromechanical switch includes an actuation electrode, a cantilever electrode, a contact, a suspended conductor, and a signal line. The actuation electrode is mounted to a substrate, the cantilever electrode is suspended proximate to the actuation electrode, and the contact is mounted to the cantilever electrode. The suspended conductor is coupled to the contact and straddles a portion of the cantilever electrode. The signal line is positioned to form a closed circuit with the contact and the suspended conductor when an actuation voltage is applied between the actuation electrode and the cantilever electrode.

Abstract: A phase locked magnetron comprises a cathode and anode and an interaction space in between. The cathode is coupled to an injected locking signal, which prompts the operation of the magnetron to be in phase with the phase of the locking signal. From a magnetron of the type in which the cathode is at a large negative potential, the coupling to the locking signal is by non-contact means, in particular, by extending the cathode into a waveguide in which the locking signal is present. An alternative arrangement is for a magnetron of the type in which the cathode is substantially at ground potential. In this arrangement the coupling is by direct electrical connection to a conductor having the injected locking signal.

Abstract: A phase shifting method and a phase shifter are provided. The phase shifter comprises a first (200) and a second (202) transmission line structure in parallel, the structures having a common input, each structure comprising cascaded forward and backward transmission lines and the same number of components. The component values of the second structure are equal to the component values of the first structure multiplied by a given proportionality constant.

Abstract: An LC filter structure and method for its fabrication, in which multiple shunt capacitors, multiple shunt inductors and multiple coupling inductors are printed on a metal layer formed on a thin dielectric substrate. The capacitors have first electrodes that are formed as spatially separated regions of the metal layer, and a common second electrode formed by a ground plane on the substrate. The shunt inductors are formed as spiral traces connected to the separated regions and to the ground plane, through conductive vias. The coupling inductors are similarly formed as spiral traces in the gaps between the separated regions, the ends of each coupling inductor being connected to respective adjacent regions of the metal layer.

Abstract: Electric circuit device comprises electric element and two conductive plates. The electric element includes two anode electrodes and two cathode electrodes and has relatively low impedance in a frequency range between 1×10?5 to 10 GHz. The one conductive plate has lower impedance than that of the conductive plate comprising the electric element and is connected between two anode electrodes. The other conductive plate has lower impedance than that of the conductive plate comprising the electric element and is connected between two cathode electrodes. As a result, the electric circuit device which has relatively low impedance and is capable of preventing the temperature rise is provided.

Abstract: A dual-band filter (10) is provided. The dual-band filter includes an input line (100), a first transmission line (140), a second transmission line (160), a third transmission line (180), and an output line (120). The input line is used for inputting electromagnetic signals. The first transmission line is electronically connected to the input line. The second transmission line is arranged parallel to the first transmission line. The third transmission line is arranged between, and parallel to, the first transmission line and the second transmission line. The output line for outputting electromagnetic signals, is arranged parallel to the input line, and is electronically connected to the second transmission line.

Abstract: A high frequency filter comprises a first resonator and a second resonator provided inside a layered substrate. The first and second resonators are inductively coupled and capacitively coupled to each other through a first capacitor and a second capacitor connected to each other in parallel. The first capacitor is formed using first and third electrodes and a dielectric layer. The first electrode is connected to the first resonator via a through hole. The third electrode is connected to the second resonator and opposed to the first electrode. The second capacitor is formed using second and fourth electrodes and the dielectric layer. The second electrode is connected to the second resonator via a through hole. The fourth electrode is connected to the first resonator and opposed to the second electrode.

Abstract: Systems and methods are taught for blocking the propagation of electromagnetic waves in parallel-plate waveguide (PPW) structures. Periodic arrays of resonant vias are used to create broadband high frequency stop bands in the PPW, while permitting DC and low frequency waves to propagate. Some embodiments of resonant via arrays are mechanically balanced, which promotes improved manufacturability. Important applications include electromagnetic noise reduction in layered electronic devices such as circuit boards, ceramic modules, and semiconductor chips.

Abstract: A resistor board for attenuating a signal, includes: a first signal section for receiving the signal; a second signal section for outputting the signal; and at least two signal lines disposed between the first signal section and the second signal section. Each of the signal lines includes a first resistor section, a first signal transmission section, and a second resistor section respectively arranged in series. The first resistor section and the second resistor section are formed of a first resistor layer. The first signal transmission section is formed of the first resistor layer and a first metal layer. The resistor board further includes a ground section for attenuating the signal, and a first ground line disposed between the ground section and at least one of the signal lines. The first ground line includes a third resistor section formed of the first resistor layer.

Abstract: As the static magnetic field used in Magnetic Resonance Imaging (“MRI”) instruments increases the resonance frequency also increases. Consequently, the signal lost due to the coil becomes an issue. To compensate for this loss, it is possible to use an active device, such as a diode, a transistor, etc., with the radio frequency coil, MRI arrangement and method according to exemplary embodiments of the present invention to generate negative resistance to cancel the coil loss resistance. In this manner, the efficiency of the RF coil at high frequency can be improved.

Abstract: Complementary inductor structures. The inductor structure may include two or more sub-inductors that have positive coupling to provide a total inductance approximately equal to the sum of the inductance provided by the two or more sub-inductors. Radiation from the two or more sub-inductors may be in different phases to partially, or even totally, cancel and result in a reduced overall radiation, which may reduce electromagnetic interference and/or electromagnetic coupling.