Abstract: A memory packaging structure of mini SD card, the main implementation technology thereof comprises: to perform the pin adjustment to the: memory originally employing TSOP (Thin Small Out-Line Package) packaging structure, eliminating the gap of 0.1 mm to 0.2 mm between the memory and the circuit board, thus completely attached to the circuit board; to leave the top end of the mini SD card open to directly expose the top end of the memory on the surface of the mini SD card, reducing the thickness of a layer of coverage; to cover the pins on the both sides of the memory to hind them, wherein applying glue joint between the auxiliary lateral body and memory pins to enhance the attachment.

Abstract: The present invention provides a semiconductor device which is formed at low cost and has a great versatility, a manufacturing method thereof, and further a semiconductor device with an improved yield, and a manufacturing method thereof. A structure, which has a base including a plurality of depressions having different shapes or sizes, and a plurality of IC chips which are disposed in the depressions and which fit the depressions, is formed. A semiconductor device which selectively includes a function in accordance with an application, by using the base including the plurality of depressions and the IC chips which fit the depressions, can be manufactured at low cost.

Abstract: A three dimensional electronic module is disclosed. Conventional TSOP packages are modified to expose internal lead frame interconnects, thinned and stacked on a reroute substrate. The reroute substrate comprises conductive circuitry for the input and output of electrical signals from one or more TSOPs in the stack to a ball grid array pattern. The exposed internal lead frames are interconnected and routed on one or more side buses on the module to the reroute substrate for connection to external electronic circuitry. Alternatively, internal wire bonds or ball bonds may be exposed in the TSOP packages and routed to the side bus for interconnection to create a BGA scale module. One or more neolayers may also be bonded to a reroute substrate to create a BGA scale module.

Abstract: An integrated circuit package system including a substrate with a top surface and a bottom surface. Configuring the top surface to include electrical contacts formed between a perimeter of the substrate and a semiconductor die. Aligning over the top surface of the substrate a mold plate with a honeycomb meshwork of posts or a stepped honeycomb meshwork of posts and depositing a material to prevent warpage of the substrate between the top surface of the substrate and the mold plate. Removing the mold plate to reveal discrete hollow conduits formed within the material that align with the electrical contacts.

Abstract: Electronic devices and methods for fabricating electronic devices are described. One embodiment includes an electronic device having a first die, the first die having a top surface, a bottom surface, and a plurality of side surfaces. The first die also includes a plurality of metal pads on the top surface extending to an outer edge of the top surface, and a plurality of metal pads on the bottom surface extending to an outer edge of the bottom surface. The first die also includes a plurality of metal regions along the side surfaces, wherein each of the metal regions extends between one of the metal pads on the top surface and one of the metal pads on the bottom surface. Other embodiments are described and claimed.

Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. Combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Abstract: A chip package system is provided including providing a chip having interconnects provided thereon; forming a molding compound on the chip and encapsulating the interconnects; and forming a recess in the molding compound above the interconnects to expose the interconnects.

Abstract: A stacked integrated circuit package-in-package system is provided forming a first device having a first integrated circuit package comprises forming a first substrate with a first integrated circuit thereon, electrically connecting first electrical interconnects between the first integrated circuit and a top side of the first substrate, encapsulating a first top molding compound to cover the first electrical interconnects and a portion of the top side of the first substrate, and encapsulating a first bottom molding compound to cover the first integrated circuit and a bottom side the first substrate, and stacking a second device, having a second integrated circuit package, below the first device with a second top molding compound of the second device providing a space between the first device and the second device, wherein the second device includes the second top molding compound and a second bottom molding compound in a similar manner to the first device.

Abstract: A system and method for combining at least two semiconductor die using multi-layer flex circuitry is provided. A first semiconductor die is attached and preferably electrically connected to a first layer of the flex circuitry while a second semiconductor die is set, at least in part, into a window that extends into the flex circuitry to expose a layer of the flex to which the second die is attached. When the second semiconductor die is a flip-chip device, it is connected through its contacts to the layer of flex exposed in the window and when it is a die with its contact side oriented away from the flex circuitry, it is preferably electrically connected with wire bonds to another conductive layer of the flex circuitry. In preferred modules, the first semiconductor die is preferably a flash memory circuit and the second semiconductor die is preferably a controller.

Abstract: In a substrate including a plurality of first wires to be tested, and a plurality of second wires each defining a capacity with each of the first wires, a method of testing whether said first wires are defective or not, includes (a) applying a voltage to the first wires, and (b) detecting a capacity defined between the first and second wires while the step (a) is being carried out.

Abstract: A package-in-package system is provided including forming a top substrate having a first integrated circuit electrically connected thereto and mounting a second integrated circuit over the first integrated circuit. The system includes forming first electrical connectors on the second integrated circuit and encapsulating the second integrated circuit in a first encapsulant with the first electrical connectors exposed. The system includes mounting the second integrated circuit over a bottom substrate with the first electrical connectors electrically connected thereto and encapsulating the top substrate and the first encapsulant in a second encapsulant.

Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate.

Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.

Abstract: A contact spring applicator is provided which includes an applicator substrate, a removable encapsulating layer and a plurality of contact springs embedded in the removable encapsulating layer. The contact springs are positioned such that a bond pad on each contact spring is adjacent to an upper surface of the removable encapsulating layer. The contact spring applicator may also include an applicator substrate, a release layer, a plurality of unreleased contact springs on the release layer and a bond pad at an anchor end of each contact spring. The contact spring applicators apply contact springs to an integrated circuit chip, die or package or to a probe card by aligning the bond pads with bond pad landings on the receiving device. The bond pads are adhered to the bond pad landings. The encapsulating or release layer is then removed to separate the contact springs from the contact spring applicator substrate.

Abstract: A semiconductor device includes, in first and second power source systems, electrostatic discharge (ESD) protective bonding pads connected by bonding wires to first and second power supply terminals and first and second ground terminals, first and second signal ESD protective element sections that are each connected to first and second signal bonding pads and the ESD protective bonding pads and protect first and second I/O circuits, respectively, and a power source ESD protective element section connected to first and second ESD protective bonding pads. The semiconductor device is capable of minimizing an increase in the chip size while implementing ESD damage countermeasures in which the power supply (or ground) terminal of one power source system serves as the reference potential terminal for the signal terminal of the other power source system.

Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.

Abstract: A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance. A MOSFET (70) has a connecting portion for electrically connecting a surface electrode of a semiconductor pellet and a plurality of inner leads, a resin encapsulant (29), a plurality of outer leads (37), (38) protruding in parallel from the same lateral surface of the resin encapsulant (29) and a header (28) bonded to a back surface of the semiconductor pellet and having a header protruding portion (28c) protruding from a lateral surface of the resin encapsulant (29) opposite to the lateral surface from which the outer leads protrude, wherein the header (28) has an exposed surface (28b) exposed from the resin encapsulant (29); the outer leads (37), (38) are bent; and the exposed of the outer leads (37), (38) are provided at substantially the same height.

Abstract: An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of the bond finger, and a portion of the pedestal are embedded in an resin layer with an exposed portion of the pedestal protruding from the resin layer. A second die is mounted on the first die and electrically coupled to the exposed portion of the pedestal.

Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along one side of a flex circuit. The semiconductor die is disposed along the flex circuitry and preferably is between at least a part of the flex circuitry and the body of the leaded packaged IC. Preferably, the die is attached to a conductive layer of the flex circuitry. The flex circuitry preferably employs at least two conductive layers and the leaded packaged IC and die are preferably connected to one of the conductive layers of the flex circuitry. In preferred modules, the leaded packaged IC is preferably a flash memory device and the semiconductor die is preferably a controller.

Abstract: A dynamic quantity sensor includes a sensor chip (10) having a movable portion (13) at one surface side thereof and a silicon layer (14) at another surface side thereof. The movable portion (13) is displaced under application of a dynamic quantity. The silicon layer (14) is separated from the movable portion (13) through an insulator (15). The dynamic quantity sensor also includes a circuit chip (20) for transmitting/receiving electrical signals to/from the sensor chip (20). The circuit chip (20) is disposed to confront the one surface of the sensor chip (10) through a gap portion (30) and cover the movable portion (13). The sensor chip (10) and the circuit chip (20) are bonded to each other around the gap portion (30) so that a bonding portion (40) is formed to substantially surround the gap portion (30) and thereby seal the gap portion (30).

Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.

Abstract: This invention relates to a hybrid composite material substrate. The substrate includes a conductive layer, an insulating layer, and a dispersion material extending from the conductive layer into the insulating layer.

Abstract: The present invention teaches the recycling of a faulty multi-die memory package by isolating the functional part of the package and using it as a smaller memory package.

Abstract: A semiconductor device includes a substrate, a semiconductor chip having a diaphragm, which vibrates in response to sound pressure variations, and a circuit chip that is electrically connected to the semiconductor chip so as to control the semiconductor chip, wherein the semiconductor chip is fixed to the surface of the circuit chip whose backside is mounted on the surface of the substrate. Herein, a plurality of connection terminals formed on the backside of the semiconductor chip are electrically connected to a plurality of electrodes running through the circuit chip. A ring-shaped resin sheet is inserted between the semiconductor chip and the circuit chip. The semiconductor chip and the circuit chip vertically joined together are stored in a shield case having a mount member (e.g., a stage) and a cover member, wherein connection terminals of the circuit chip are exposed to the exterior via through holes of the stage.

Abstract: An electronic device is provided, in which semiconductor components are structurally identical among one another and have two groups of contact connections arranged on opposite main areas on a printed circuit board. Components are arranged in a manner laterally offset in a direction parallel to the printed circuit board area in such a way that, on opposite main areas, a group of first contact connections of a semiconductor component fitted on one main area is in each case arranged in the same region of the printed circuit board as a group of first contact connections of a semiconductor chip arranged on the opposite main area. Likewise, the groups of second contact connections of the semiconductor chips arranged on opposite main areas in each case attain congruence.

Abstract: A package structure and a fabricating method thereof are provided. The package structure includes a soft board and an optical chip. The soft board has a surface with a bump disposed thereon. The optical chip includes a main body and a conductive pillar. The main body has an active surface and a non-active surface opposite to the active surface. The active surface has a sensing area and a contact pad electrically connected with each other. The non-active surface is attached to the surface. The conductive pillar is disposed inside the main body, and penetrates the active surface and the non-active surface. The conductive pillar has a first end electrically connected to the contact pad and a second end electrically connected to the bump.

Abstract: The present invention provides a connecting module having at least one passive component including a substrate, a connecting wire layout, at least one passive component and a chip-setting area, wherein the connecting wire layout is formed on the substrate, the passive components are formed on the connecting wire layout to electrically connect to the connecting wire layout. The chip-setting areas are formed in the substrate locating at different areas from the connecting wire layout, wherein the size of the passive components can be adjusted to match the needed impedance, and the numbers and the location of the chip-setting areas can be adjusted dynamically for reducing the dimension of the module.

Abstract: A circuit module is disclosed that includes a bare chip and a surface mounting component mounted on a surface of a substrate, and a sealing resin for sealing the bare chip and the surface mounting component. The sealing resin is molded entirely on the surface of the substrate by transfer molding.

Abstract: A method of fabricating a three-dimensional semiconductor device is provided along with a three-dimensional semiconductor device fabricated thereby. The method includes forming a heat conductive plug to channel heat away from devices on a substrate, while high temperature processes are performed on a stacked semiconductor layer. The ability to use high temperature processes on the stacked semiconductor layer without adversely effecting devices on the substrate allows the formation of a high quality single-crystalline stacked semiconductor layer. The high quality single-crystalline semiconductor layer can then be used to fabricate improved thin film transistors.

Abstract: An electronic device wherein an electronic element is electrically connected to a substrate through an interposer and a method of manufacturing the same are disclosed. The electronic device comprises an electronic element and an interposer including an interposer base to which the electronic element is joined and plural post electrodes connected to corresponding electrodes of the electronic element. In the electronic device, the electronic element and the interposer base are integrated with each other by being brought into direct contact with each other, and the post electrodes are formed directly on the corresponding electrodes of the electronic element.

Abstract: An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed in the mold compound to expose a portion of the solder bump. The wafer is singulated into individual die structures at the groove.

Abstract: Electrical connections between different materials. An electrical connection system includes electrical components and an electrical connection between the electrical components. The electrical connection includes a functionally graded material. A method of making an electrical connection between different materials includes the steps of: providing an electrical component which includes a material; providing another electrical component which includes another material; and electrically connecting a functionally graded material between the electrical components. An electrical connection system includes an electrical component and a functionally graded material electrically connected to the electrical component. The functionally graded material provides a gradual transition between at least two dissimilar materials.

Abstract: A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.

Abstract: A pad layout suitable for being applied on a metal interconnection structure of an integrated circuit chip is provided. The pad layout includes a first signal pad, a second signal pad, a first non-signal pad, a second non-signal pad, a first trace, a second trace, a first guard ring and a second guard ring. The second signal pad is located adjacent to the first signal pad. The first non-signal pad is located adjacent to the first signal pad. The second signal pad is located adjacent to the second signal pad. The first guard ring surrounds the first signal pad and is connected to the first non-signal pad through the first trace. The second guard ring surrounds the second signal pad and is connected to the second non-signal pad through the first trace.

Abstract: A semiconductor device 1 is a semiconductor device of the BGA type, and includes a semiconductor chip 10, a resin layer 20, an insulating layer 30, and an external electrode pad 40. The resin layer 20 is constituted by a sealing resin 22 and an underfill resin 24, and covers the semiconductor chip 10. The insulating layer 30 is formed on the resin layer 20. The external electrode pad 40 is formed in the insulating layer 30. This external electrode pad 40 extends through the insulating layer 30. One surface S1 of the external electrode pad 40 is exposed in the surface of the insulating layer 30, and the other surface S2 is located in the resin layer 20. A concave portion 45 is formed in the surface S2 of the external electrode pad 40. The resin composing the resin layer 20 enters into the concave portion 45.

Abstract: A circuit board for flip-chip packaging is provided which can achieve the connection reliability of a semiconductor device and the circuit board. The circuit board for flip-chip packaging includes, on a surface of a substrate (6), wiring patterns (1), connection pads (2) for flip-chip packaging, and a solder resist (3) having openings (4) formed on the connection pads (2). In the circuit board, conductive members (5) are formed in the openings (4).

Abstract: A chip has a wafer portion of a first coefficient of thermal expansion, the wafer portion including at least one via defined by a peripheral sidewall, an insulating region having second average coefficient of thermal expansion, located within the via and covering at least a portion of the peripheral sidewall to a first thickness, a metallic region having a third average coefficient of thermal expansion, located within the via and covering the insulator to a second thickness, the first thickness and second thickness being selected such that expansion of the combination of the insulator and the metal due to heat will match the expansion of the wafer portion as a result of the combined effect of the first and second thicknesses and their respective second and third average coefficients of thermal expansion.

Abstract: An electronic device (1) has a base plate (2) and an electronics housing (3) connected thereto, with a bond contact bearer (5). The latter rests on the base plate (2) via a supporting body (6) in such a manner that the supporting body (6) exerts a pretension force onto the bond contact bearer (5). Due to the support of the bond contact bearer (5) in the close vicinity, its position is well defined during the bonding procedure. A secure bond is the result.

Abstract: A structure of Ball Grid Array package (BGA) is provided. The plurality of bumps are attached on a substrate when processed the surface mount technology (SMT) may get stronger support, avoid the assembly structure disintegration when bearing an external force. When user uses a semi-conductor module, the assembly structure will not be damaged by external force.

Abstract: An integrated circuit package having metallic members intruding into solder balls. The integrated circuit package includes an integrated circuit, an encapsulant, a plurality of solder balls and a plurality of metallic members. A plurality of bonding pads is disposed on an integrated circuit. The encapsulant is made of an insulation material and covers the integrated circuit. A plurality of slots is formed on a bottom surface of the encapsulant. The solder balls are respectively disposed in the slots on the bottom surface of the encapsulant and protrude from the bottom surface of the encapsulant. Each metallic member has a first end, which is electrically connected to a bonding pad of the integrated circuit, and a second end, which protrudes from the bottom surface of the encapsulant and is bent to intrude into a corresponding one of the solder balls to fix the solder ball.

Abstract: A semiconductor package with improved solder joint reliability, and a method of fabricating the same are provided. The semiconductor package comprises a printed circuit board (PCB) having a plurality of interconnection layers formed on its surface, and having a plurality of through holes connected to the interconnection layers. An adhesive member is attached to an upper surface of the PCB, and a semiconductor chip is electrically connected to the interconnection layers and mounted on an upper surface of the adhesive member. A solder connecting part fills each through hole so as to form a mechanically strong connection that is resistant to breakage during thermal transients and physical impacts.

Abstract: The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an annealing of three metal layers of Pd, Ge and Cu; and, the contact resistance of the ohmic contact is adjusted by the thicknesses of the three layers.

Abstract: A metal wiring forming method in a semiconductor device can include forming an interlayer insulating film on a lower metal wiring, the first interlayer insulating film having a non-planar upper surface; forming a stop layer on the interlayer insulating film and over the lower metal wiring; forming an interlayer insulating film pattern on the stop layer, wherein an upper surface of the interlayer insulating film pattern and an upper surface of the stop layer are substantially coplanar; removing a portion of the stop layer to form a stop layer pattern, wherein a portion of the interlayer insulating film over the lower metal wiring is exposed by the stop layer pattern; and etching the exposed portion of the interlayer insulating film to form a via hole therethrough, wherein the lower metal wiring is exposed by the via hole.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: A circuit board device with a fine conductive structure is proposed. A circuit board having at least a circuit layer is provided and the circuit layer has at least one electrically conductive pad. At least one first dielectric layer is formed on surfaces of the circuit board and the circuit layer and has at least one opening to expose the electrically conductive pad of the circuit layer. At least a first fine conductive structure made of conductive material with high ductility is formed in the opening of the first dielectric layer and is electrically connected to the electrically conductive pad of the circuit layer. The top surface of the first fine conductive structure is higher than, level with or lower than the surface of the first dielectric layer. Moreover, a conductive pad may be further formed on the top surface of the first fine conductive structure.

Abstract: An electronic component includes a substrate, and a capacitor unit on the substrate. The capacitor unit has a laminate structure including a first electrode layer provided on the substrate, a second electrode layer opposed to the first electrode layer, and a dielectric layer disposed between the first and the second electrode layers. The first electrode layer has a multilayer structure including an adhesion metal layer joined to the dielectric layer. The adhesion metal layer is provided with an oxide coating on a side of the dielectric layer.

Abstract: A semiconductor device according to an embodiment of the present invention has: a semiconductor substrate; an interlayer insulating film formed above the semiconductor substrate; a protective film formed on the interlayer insulating film, the protective film having a higher density than that of the interlayer insulating film; at least one of a wiring and a dummy wiring formed in the interlayer insulating film and the protective film; and a separation wall formed within the interlayer insulating film so as to surround a low density region to separate the low density region from other regions, a sum of covering densities of the wiring and the dummy wiring being lower than a predetermined prescribed value in the low density region.

Abstract: A mold type semiconductor device includes a semiconductor chip including a semiconductor part; a metallic layer; a solder layer; and a metallic member connecting to the semiconductor chip through the metallic layer and the solder layer. The solder layer is made of solder having yield stress smaller than that of the metallic layer. Even when the semiconductor chip is sealed with a resin mold, the metallic layer is prevented from cracking.

Abstract: In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

Abstract: A method for fabricating a circuit board with a conductive structure and the same are proposed. A buffer metal layer is formed on an electrically connecting pad of a circuit layer of a circuit board in advance. A conductive structure is then formed on the buffer metal layer to form the conductive structure of the present invention and is connected to the circuits located in the different layers of the circuit board. The combining strength of the conductive structure and the electrically connecting pad is reinforced by the buffer metal layer as the buffer metal layer has high ductility. The long-term electrical quality and stability are also enhanced.