Abstract: A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. In the epitaxial layers, P type buried diffusion layers and P type diffusion layers are formed, which form isolation regions. In this event, the P type buried diffusion layers are formed by being expanded from a surface of a first epitaxial layer. By use of this structure, lateral expansion widths of the P type buried diffusion layers are reduced. Thus, the device size of an NPN transistor can be reduced.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.

Abstract: The present invention provides a production method for a FinFET transistor arrangement, and a corresponding FinFET transistor arrangement.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)>(X0/Y0).

Abstract: Disclosed is a static random access memory (SRAM), which includes first and second access transistors composed of metal oxide semiconductor (MOS) transistors, first and second drive transistors composed of MOS transistors, and first and second p-channel thin film transistors (TFTs) used as pull-up devices. The SRAM includes a ground potential layer disposed as a common source of the first and second drive transistors, and formed by implanting a dopant into a semiconductor substrate, a power supply potential layer connected with sources of the first and second p-channel TFTs, and an insulating layer formed on the substrate and interposed between the ground potential layer and the power supply potential layer.

Abstract: In order to provide an anisotropic conductive sheet which can be applied to more finely and more narrowly pitched electrodes and also to provide spring electrodes applied for the anisotropic conductive sheet, the spring electrodes manufactured as follows. A part having a bending leaf spring shape is formed out of a monocrystal silicon by anisotropic etching and gold is plated on the surface of the part so as to obtain a silicon spring electrode 1. The silicon spring electrodes 1 are inserted in through holes formed on a silicone rubber sheet and fixed to the through holes.

Abstract: A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

Abstract: Embodiments relate to a gate structure of a semiconductor device and a method of manufacturing the gate structure. An oxide layer may be formed on a silicon substrate before a gate insulating layer is formed. The oxide layer may be etched to form an opening exposing a channel area of the silicon substrate. After forming the gate insulating layer in the opening, a gate conductive layer may be deposited and etched to form a gate. The oxide layer may be continuously etched such that the oxide layer remains at both edge portions of the gate insulating layer. The oxide layer formed at both edge portions of the gate insulating layer may protect the gate insulating layer during a gate etching process, and may improve a reliability of the semiconductor device.

Abstract: Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

Abstract: A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region.

Abstract: An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.

Abstract: Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized. Nanodetector devices are described.

Abstract: A micro-electromechanical device includes a semiconductor substrate and an arm coupled to the substrate. The arm is pivotable out-of-plane relative to the substrate and at least a portion of the arm is deformable. The deformable portion of the arm deforms as the arm pivots relative to the substrate.

Abstract: An apparatus and method for a micromachined mechanical switch device having first and second cooperating electrical switch contacts formed by respective first and second patterns of robust carbon nanotube thin film structures for forming intermittent electrical contact between the first and second conductors in response to the applied force urging the first and second cooperating patterns of carbon nanotube thin film structures together into momentary or substantially permanent physical contact.

Abstract: Disclosed are wired implantable integrated CMOS-MEMS sensors and fabrication methods. A first ceramic substrate comprising a biocompatible material such as fused silica is provided. A polysilicon layer is formed on the first substrate. An integrated circuit is fabricated adjacent to the surface of the first substrate. A passivation layer is formed on the integrated circuit. A conductive area is formed on the passivation layer that provides electrical communication with the integrated circuit. A feedthrough is formed through the first substrate that contacts the conductive area and provides for external electrical communication to the integrated circuit. A second ceramic substrate or cap comprising a biocompatible material is fused to the first substrate so as to form a cavity that encases the integrated circuit and form a sensor.

Abstract: A lower cost range-finding image sensor based upon measurement of reflection time of light with reduced fabrication processes compared to standard CMOS manufacturing procedures. An oxide film is formed on a silicon substrate, and two photo-gate electrodes for charge-transfer are provided on the oxide film. Floating diffusion layers for taking charges out from a photodetector layer are provided at the ends of the oxide film, and on the outside thereof are provided a gate electrode for resetting and a diffusion layer for providing a reset voltage.

Abstract: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages.

Abstract: A method and apparatus for improving the planarity of a recessed color filter array when the recessed region or trench depth exceeds the thickness of the color filter film. The method includes the steps of coating the entire wafer with an additional coating material after applying the CFA, then planarizing that resist layer using CMP and then using a dry etch to transfer that planar surface down as far as required to achieve a planar color filter with a uniform thickness.

Abstract: A compact camera module mainly includes an image sensor chip, a module case and a lens module. The image sensor chip has an active surface, a back surface and a plurality of side surfaces, wherein a sensor region is formed in the active surface. A plurality of lateral contact fingers is formed on the side surfaces. The image sensor chip is plugged in a cave of the module case, a plurality of electrically contact components disposed on inside walls of the cave electrically connect the lateral contacting fingers. The lens module is mounted on the module case to seal the image sensor chip. Because the electrically contact components can replace the bonding wires to electrically connect the lateral contacting fingers, the compact camera module can be reworked and tiny.

Abstract: It is an object of the invention to provide an improved solid image-pickup device which is compact in size and low in production cost. The solid image-pickup device is so formed that its semiconductor substrate has on its surface an image-pickup area having a plurality of light sensors arranged thereon. A transparent plate having the same shape and the same size as those of the semiconductor substrate when viewed as a plan view is bonded to the surface of the semiconductor substrate. A plurality of bonding pads are formed on the surface of the semiconductor substrate and arranged around the image-pickup area. Further, a plurality of through holes are formed through the semiconductor substrate, extending from the lower surfaces of the bonding pads to the back surface of the semiconductor substrate. An insulating film is tightly attached to the inner surface of each of the through holes, while another insulating film is tightly attached to the back surface of the semiconductor substrate.

Abstract: Methods for Implementation of a Switching Function in a Microscale Device and for Fabrication of a Microscale Switch. According to one embodiment, a method is provided for implementing a switching function in a microscale device. The method can include providing a stationary electrode and a stationary contact formed on a substrate. Further, a movable microcomponent suspended above the substrate can be provided. A voltage can be applied between the between a movable electrode of the microcomponent and the stationary electrode to electrostatically couple the movable electrode with the stationary electrode, whereby the movable component is deflected toward the substrate and a movable contact moves into contact with the stationary contact to permit an electrical signal to pass through the movable and stationary contacts. A current can be applied through the first electrothermal component to produce heating for generating force for moving the microcomponent.

Abstract: A PN-junction temperature sensing apparatus for applying input signals to a semiconductor device and measuring temperature-dependent output signals has an odd number of current sources (1, 2, n) switches (5, 6, 7) with selectable outputs to connect the current sources (5, 6, 7) with a thermal sensor (12) or a sink diode (13) and an A/D converter (17) to digitize the measured voltage of the thermal sensor (12). A digital processor (18) controls the switches (5, 6, 7) and stores the digitized voltage values in a memory. Provided algorithms allow the usage of these values to provide a calibrated measurement of temperature and also sensor life estimation.

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: A semiconductor device according to this invention includes: two level shift switches (28A and 28B) each having first and second electrodes, a control electrode, a signal output electrode, and a first semiconductor region forming a transistor device section (28a,28b) which intervenes between the first electrode and the signal output electrode and is brought into or out of conduction according to a signal inputted to the control electrode and a resistor device section (Ra,Rb) which intervenes between the signal output electrode and the second electrode, the first semiconductor region comprising a wide bandgap semiconductor; and a diode (23) having a cathode-side electrode, an anode-side electrode, and a second semiconductor region comprising a wide bandgap semiconductor.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a damage layer formed in a substrate, a first doped well formed in the substrate, and a second doped well formed in the substrate proximate to the first doped well. The damage layer extends within the substrate to intersect the first and second doped wells. The damage layer may be formed by ion implantation followed by growth of an epitaxial layer to segregate the active device regions from the damage layer.

Abstract: A semiconductor integrated circuit device with higher integration density and a method of fabricating the same are provided. The semiconductor integrated circuit device may include trench isolation regions in a semiconductor substrate that define an active region and a gate pattern that is used for a higher voltage and formed on the active region of the semiconductor substrate. Trench insulating layers may be formed in the semiconductor substrate on and around edges of the gate pattern so as to be able to relieve an electrical field from the gate pattern. The depths of each of the trench insulating layers may be defined according to an operating voltage. Source and drain regions enclose the trench insulating layers and may be formed in the semiconductor substrate on both sides of the gate pattern. Therefore, the semiconductor integrated circuit device may have a higher integration density and may relieve an electrical field from the gate pattern.

Abstract: The present invention relates to electrical fuses that each comprises at least one thin film transistor. In one embodiment, the electrical fuse of the present invention comprises a hydrogenated thin film transistor with an adjacent heating element. Programming of such an electrical fuse can be effectuated by heating the hydrogenated thin film transistor so as to cause at least partial dehydrogenation. Consequentially, the thin film transistor exhibits detectible physical property change(s), which defines a programmed state. In an alternative embodiment of the present invention, the electrical fuse comprises a thin film transistor that is either hydrogenated or not hydrogenated. Programming of such an alternative electrical fuse can be effectuated by applying a sufficient high back gate voltage to the thin film transistor to cause state changes in the channel-gate interface. In this manner, the thin film transistor also exhibits detectible property change(s) to define a programmed state.

Abstract: The inductance of a monolithic planar inductor is distributed into smaller inductor portions. The smaller inductor portions are provided in a cascode configuration in a manner that causes inductor to function as a differential inductor device. The node between the immediate inductor portions is a common-mode point of the inductor device, which is typically connected to the signal ground. The nodes at the outer ends of the inductor portions are differential outputs, e.g. output nodes of an amplifier device at the interface of the device itself and the following device (e.g. input stage of a mixer). Some of the inductor portions are arranged to be symmetrically bypassed or shortcut in relation to the common point in one or more steps for operation in one or more higher radio frequency band. By means of the switchable symmetric shortcut, a controllable inductance step can be provided. The common-mode signal is affected the same inductance regardless of the controlled condition.

Abstract: System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and a strip of the second polarity. A first dielectric layer is deposited over each strip of the first layer of strips. A first extension layer of a sequence of substantially interdigitated extension strips is deposited over the first dielectric layer, each extension strip deposited over a strip of the first layer of the opposite polarity. A first sequence of vias is coupled to the first extension layer, each via deposited over an extension strip of the same polarity. A second layer of a sequence of substantially parallel interdigitated strips can be coupled to the first sequence of vias.

Abstract: In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.

Abstract: A crystal comprising gallium nitride is disclosed. The crystal has at least one grain having at least one dimension greater than 2.75 mm, a dislocation density less than about 104 cm?2, and is substantially free of tilt boundaries.

Abstract: A semiconductor device comprises an Si substrate (10) and a compound layer (11) of Si1-xGex disposed on the substrate (10). X is varied from 0 to 0.2 away from the substrate (10) towards the upper surface of the compound layer (11), with the rate of change of X increasing through the layer. The increasing rate of change of X significantly improves the defectivity levels and the surf ace roughness at the surf ace of layer (11).

Abstract: A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

Abstract: A seal ring structure between an integrated circuit region and a scribe line is provided. In one embodiment, the seal ring structure comprises a substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; a first passivation layer formed over the plurality of layers of metal lines, the first passivation layer having an opening therein exposing a portion of a top metal line; residual metal pad layers formed proximal the opening of the first passivation layer; and a second passivation layer formed over the first passivation layer, the second passivation layer enveloping the exposed residual metal pad or metal redistribution layers and further having a trench above the top metal line.

Abstract: The present invention relates to a composition of matter based on lamellar materials, and method of deriving one or more predetermined number of layers of material from a bulk lamellar material. In one aspect of the present invention, a material comprising a predetermined number of one or more layers is provided. The one or more layers are layers of a lamellar material that are weakly bonded to each other. In further aspects of the present invention, methods are provided for forming a predetermined number of layers of a lamellar material.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.

Abstract: An integrated circuit package system is provided attaching a film to a die paddle, applying an adhesive to the film, and attaching an integrated circuit die over the adhesive and the film to the die paddle.

Abstract: An exemplary carrier structure (20) for carrying workpieces includes a body (23) and an adhesive tape (27). The body defines a receiving hole (21) therethrough for receiving one or more of the workpieces therein. The adhesive tape is attached to one side of the body and covers the receiving hole thereby allowing one or more of the workpieces to be received in the receiving hole and on the adhesive tape.

Abstract: An assembly structure of thin lead-frame is provided. A lead-frame includes the plurality of leads and a layer located on the extension of the inner lead to bear a die. Then the molding compound is covered the die, the layer, and the plurality of leads but exposed the outer lead to electrically connect with different electric circuit substrates. The inner leads used as a die pad directly may reduce the size of the package. Furthermore, the assembly cost may drop dramatically and facilitate the assembly process due to the invention is totally different than prior package assembly method.

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allowed the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

Abstract: A semiconductor package that includes a semiconductor device that is integrated with a silicon substrate.

Abstract: A circuit board suitable for being electrically connected to a chip package is provided. The chip package has a chip pad and a plurality of inner leads. The circuit board includes at least one patterned conductive layer and at least one insulating layer. The patterned conductive layer has at least one first pad and at least one second pad. The first pad has an extension part and is suitable for being electrically connected to the chip pad. The second pad is suitable for being electrically connected to one end of at least one of the inner leads, while the other end of the inner lead suitable for being electrically connected to the second pad has a projection at least partially overlapping the extension part on the patterned conductive layer. Moreover, the patterned conductive layer is disposed outside the insulating layer.

Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of saw paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, C2, D1, D2) are assigned to each exposure field, each of which control module fields contains at least one optical control module (OCM-A1, OCM-A2, OCM-B1, OCM-B2, OCM-C1, OCM-C2, OCM-D1, OCM-D2) and lies within the exposure field in question and comprises a plurality of control module field sections (A11, A12 . . . AIN and A21, A22 . . . A2N and B11, B12 . . . B1N and B21, B22 . . . B2N and C1N and C2N and D1N and D2N) and is distributed among several lattice grids (3), wherein each control module field section (A11 to D2N) is located in a lattice field and contains at least one control module component (10,11,12,13,14,15,16,17,18).

Abstract: An electronic component is disclosed including a plurality of semiconductor packages soldered together in a side-by-side configuration. The packages are batch processed on a substrate panel. The panel includes a plurality of through-holes drilled through the panel and subsequently filled with metal such as copper or gold. These filled through-holes lie along the cut line between adjacent packages so that, upon singulation, the filled through holes are cut and a portion of the filled through-holes are exposed at the side edges of the singulated packages. These exposed portions of the filled through-holes form vertical surface mount technology (SMT) pads. After the semiconductor packages are singulated and the SMT pads are defined in the side edges, SMT is used to solder the SMT pads of a first semiconductor package to the respective SMT pads of a second semiconductor package to structurally and electrically couple the two packages together side-by-side.

Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

Abstract: Packaging and encapsulation methods include use of a tape substrate with a mold gate that includes an aperture and a support element that extends over at least a portion of the aperture. The tape substrate may be part of a strip. A semiconductor device is secured and electrically connected to the tape substrate. The resulting assembly is placed into a cavity of a mold, and encapsulant is introduced into the cavity through the mold gate of the tape substrate. Once the encapsulant has sufficiently hardened, the package assembly may be removed from the mold, and a sprue of residual encapsulant removed therefrom. If the package assembly is carried by a strip that carries other package assemblies, it may be removed from the strip.

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allow the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.