Abstract: The present invention is a silicon single crystal grown by CZ method, wherein Cu precipitates do not exist inside the silicon single crystal, a silicon wafer produced from the silicon single crystal, wherein Cu precipitates do not exist on a surface of and inside the wafer, and an apparatus for producing a silicon single crystal according to CZ method, wherein Cu concentration in a component made of quartz to be used in a part in which a temperature in a furnace for single crystal growth is 1000° C. or more is 1 ppb or less, and Cu concentration in a component made of quartz to be used in a part in which a temperature in a furnace for single crystal growth is less than 1000° C. is 10 ppb or less, and a method for producing a silicon single crystal by using the producing apparatus. Thereby, there are provided a silicon single crystal and a silicon wafer which have extremely few crystal defects and have high quality and high yield, a producing apparatus therefor, and a producing method therefor.

Abstract: A method and apparatus for forming a semiconductor sheet suitable for use as a solar cell by depositing an array of solidified drops of a feed material on a sheet support. The desired properties of the sheet fabricated with the teaching of this invention are: flatness, low residual stress, minority carrier diffusion length greater than 40 microns, and minimum grain dimension at least two times the minority carrier diffusion length. In one embodiment, the deposition chamber is adapted to form and process sheets that have a surface area of about 1,000-2,400 cm2.

Abstract: A laser repair structure and method for TFT panel. A first metal conductor is located in the source-drain layer and having a contact hole to the pixel electrode, and the region of the first metal conductor is within the region of the storage capacitance line. To repair a white defect of a pixel, make extending portions of the first metal conductor to overlap with the gate line of the previous pixel so as to electrically connect them by the laser irradiation. Another choice is setting two second metal conductors located in the gate-electrode layer and partially overlapped with the data line and the first conductor separately, then using laser irradiation to electrically connect one second metal conductor to repair the white defect of a pixel or electrically connect two second metal conductors lo repair an open-circuited data line.

Abstract: An LCD includes a thin film display device having a plastic insulating substrate in which lifting of the edge of the thin film is avoided which includes a display region and a non-display region; a gate line assembly formed on the plastic insulating substrate with the use of a shadow mask disposed over the plastic insulating substrate; a gate insulating layer formed on the gate line assembly in the display region; a data line formed on the gate insulating layer and a data pad formed in the non-display region and spaced away from the gate insulating layer; and a passivation layer formed on the data line.

Abstract: An object of the invention is to provide a method for manufacturing a light emitting device capable of reducing deterioration of elements due to electrostatic charge caused in manufacturing the light emitting device. Another object of the invention is to provide a light emitting device in which defects due to the deterioration of elements caused by the electrostatic charge are reduced. The method for manufacturing the light emitting device includes a step of forming a top-gate type transistor for driving a light emitting element. In the step of forming the top-gate type transistor, when processing a semiconductor layer, a first grid-like semiconductor layer extending in rows and columns is formed over a substrate. The plurality of second island-like semiconductor layers are formed between the first semiconductor layer. The plurality of second island-like second semiconductor layers serve as an active layer of the transistor.

Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer. Methods of fabricating silicon carbide MOSFET devices are also provided.

Abstract: A semiconductor structure with active zones, such as light diodes or photodiodes, including a substrate (SUB) with at least two active zones (AZ1-AZn), each of which emits or absorbs a radiation of differing wavelength. According to the invention, a multi-wavelength diode may be achieved, in which a first (lower) active zone (AZ1) is grown on a surface of the substrate (SUB), with one or several further active zones (AZ1-Azn) epitaxially grown one on the other and the active zones (AZ1-AZn) are serially connected from the lower active zone (AZ1) to an upper active zone (AZn), by means of tunnel diodes (TD1-TDn), serving as low-impedance resistors.

Abstract: New combinations of semiconductor devices in conjunction with optically active materials are set forth herein. In particular, light emitting semiconductors fashioned as diodes from indium gallium nitride construction are combined with high-performance optically active Langasite La3Ga5SiO14 crystalline materials. When Langasite is properly doped, it will respond to the light output emissions of the diode by absorbing high energy photons therefrom and reemitting light of longer wavelengths. High-energy short wavelength light mixes with the longer wavelengths light to produce a broad spectrum which may be perceived by human observers as white light. Langasite, a relatively new material, enjoying great utility in frequency control and stabilization schemes has heretofore never been used in combination with optical emission systems.

Abstract: ZnO nanostructure-based LEDs are provided to improve the emission efficiency. The devices include several configurations. Single crystal ZnO or MgxZn1?xO nanotips are grown on the top of a GaN p-n junction. Also, n-type ZnO nanotips are grown on p-GaN film to form an n-type ZnO nanotip/p-GaN heterojunction LED. A ZnO LED can be formed when depositing n-type ZnO nanotips on a p-type ZnO film layer. The ZnO nanotips, with a p-n junction in the tips, can be grown on glass for a low cost nano-LED, and can be grown on Si substrates to form an integrated ZnO nanoLED array on Si chips.

Abstract: A two-dimensional photonic crystal LED composed of a p-type semiconductor cladding layer 12, an active layer 11 of light-emitting material, and an n-type semiconductor cladding layer 13 placed between a pair of electrodes, where air holes 16 penetrating through the layers 12, 11 and 13 and arranged periodically in the layers 12, 11 and 13 are provided. At least a part of the inner wall of the air holes 16 is oxidized 17 in either one or both of the p-type semiconductor cladding layer 12 and the n-type semiconductor cladding layer 13. The holes and electrons injected from the electrodes avoid the oxidized region 17 and enter the active layer 11 apart from the air holes 16, which minimizes the recombination (surface recombination) of the holes and electrons producing heat instead of light.

Abstract: An optoisolator device is shown having a die attachment device with a planar surface. A first circuit die has first and second planar surfaces and a first side surface. A receiver circuit and a first photodiode are formed on the first planar surface of the first circuit die, where the first photodiode is electrically coupled to the receiver circuit. The second planar surface of the first circuit die is attached to the planar surface of the die attachment device. A second circuit die has a transmitter circuit that includes a first light emitting diode and is attached to the die attachment device in a position adjacent to the first side surface of the first circuit die. A clear plastic layer is formed on the planar surface of the die attachment device over the first and second circuit dies. An opaque layer may be formed over the clear plastic layer.

Abstract: A MESA-type photonic detection device, including at least one first junction, which itself includes a first receiving layer and sides formed or etched in the receiving layer. These sides at least partially include a layer with a doping opposite the doping of the first receiving layer.

Abstract: A method for fabricating a light emitting diode (LED) is provided. First, a first type doped semiconductor layer, an emitting layer and a second type doped semiconductor layer are sequentially formed on an epitaxy substrate. Then, a gold layer is formed on the second type doped semiconductor layer. Next, a silicon substrate is provided, and a wafer bonding process is performed between the silicon substrate and the gold layer. Finally, the epitaxy substrate is removed. As mentioned above, a LED with better reliability and efficiency of light-emitting is fabricated according to the method provided by the present invention. Moreover, the present invention further provides a LED.

Abstract: A backlight unit includes a light guide plate having a light-incidence plane and a light-exit plane and at least a light emitting diode (LED) mixing package located in proximity to the light-incidence plane for providing lights to the backlight unit. The LED mixing package includes at least a first color LED chip, at least a first color compensation film corresponding to the first color LED chip, at least a second color LED chip, and at least a second color compensation film corresponding to the second color LED chip, in which the first color compensation film and the second color compensation film are located on the light-incidence plane of the backlight unit. The backlight unit further includes at least a spectrum sensor disposed on the light-exit plane of the backlight unit.

Abstract: A light-emitting diode structure with transparent window covering layer of multiple films discloses at least a first transparent covering layer and a second covering layer, which are covered with the outside of the light-emitting diode chip. The light-emitting diode chip can emit more than two kinds of light waves to increase the transmission of the different wavelengths and the taking out efficiency of the light-emitting diode. Furthermore, the first transparent covering layer and the second covering layer are deposited each other on the outside of the light-emitting diode chip. The surface of the light-emitting diode with the covering layers is smooth. The contacting parts of the first transparent covering and the second covering layer have strong adhesive force and the contacting parts of the covering layer and light-emitting diode chip also have strong adhesive force.

Abstract: One close loop system and method for electrophoretic deposition (EPD) of phosphor material on light emitting diodes (LEDs). The system comprises a deposition chamber sealed from ambient air. A mixture of phosphor material and solution is provided to the chamber with the mixture also being sealed from ambient air. A carrier holds a batch of LEDs in the chamber with the mixture contacting the areas of the LEDs for phosphor deposition. A voltage supply applies a voltage to the LEDs and the mixture to cause the phosphor material to deposit on the LEDs at the mixture contacting areas.

Abstract: A chip coated LED package and a manufacturing method thereof. The chip coated LED package includes a light emitting chip composed of a chip die-attached on a submount and a resin layer uniformly covering an outer surface of the chip die. The chip coated LED package also includes an electrode part electrically connected by metal wires with at least one bump ball exposed through an upper surface of the resin layer. The chip coated LED package further includes a package body having the electrode part and the light emitting chip mounted thereon. The invention improves light efficiency by preventing difference in color temperature according to irradiation angles, increases a yield, miniaturizes the package, and accommodates mass production.

Abstract: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the semiconductor light-emitting element, the bonding wire, and the upper end of the leads, provided with a non-circular lateral cross-sectional surface structure with a long axis and a short axis. In the device, when observed along a direction in which the plurality of light-emitting devices are mounted on a same lead frame, a curvature of the lateral direction of said envelope is smaller than a curvature of the vertical direction of said envelope.

Abstract: An LED that can effectively prevent heat accumulation while preventing short-circuiting, discharge, fire and the like, even in the case where LEDs are relatively densely placed, is provided. In a can type LED 3 where an anode A, a cathode K and an LED pedestal 31p are provided within a housing 31, and pins a1 and k1 of anode A and cathode K lead out at least to the outside of housing 31 so that a voltage can be applied between anode A and cathode K via these pins a1 and k1, a condition of isolation is maintained between pin a1 of anode A and housing 31, as well as between pin k1 of cathode K and housing 31, and pin r1 which is thermally connected to LED pedestal 31p is provided outside of housing 31.

Abstract: A flat light source including a first substrate, ribs, a phosphor layer, a second substrate, electrode patterns and an insulating layer is provided. The ribs are disposed on the first substrate. The phosphor layer is disposed on the surface of the ribs. The second substrate is located above the first substrate. The electrode patterns are disposed on the second substrate, and each electrode pattern is aligned to one of the rib correspondingly. The insulating layer covers the surface of the electrode patterns. In particular, an inert gas is filled between the first and second substrates, and a discharge path is formed between the adjacent electrode patterns above the phosphor layer.

Abstract: A wafer-level chip packaging process includes the following steps. First, a wafer having a plurality of chip units, an active surface, and a corresponding back surface is provided. Each chip unit has a plurality of pads on the active surface. Next, a plurality of through holes is formed under the pads. The through holes are filled with a conductive material such that the conductive material within each through hole is electrically connected to corresponding one of the pads and a portion of the conductive material is exposed and protrudes from the back surface of the wafer. Thereafter, a transparent adhesive layer is formed on the active surface. Next, a transparent cover panel is disposed on the transparent adhesive layer such that the transparent cover panel is connected to the wafer through the transparent adhesive layer. Afterwards, a singulation step is performed to form a plurality of independent chip package structures.

Abstract: A light emitting device is disclosed. The light emitting device includes a light emitting element (15), and a light emitting element container (11) having a concave section (20) for containing the light emitting element (15). The concave section (20) includes a side surface (20A) and a bottom surface (20B) almost orthogonal to the side surface (20A). The light emitting device further includes a conductive paste layer (17) formed of a conductive paste in which metal particles are dispersed in a solution, and the conductive paste layer (17) includes a slanting surface (17A) on the side surface (20A) and the bottom surface (20B).

Abstract: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the semiconductor light-emitting element, the bonding wire, and the upper end of the leads, provided with a non-circular lateral cross-sectional surface structure with a long axis and a short axis. In the device, when observed along a direction in which the plurality of light-emitting devices are mounted on a same lead frame, a curvature of the lateral direction of said envelope is smaller than a curvature of the vertical direction of said envelope.

Abstract: A method of driving a solid-state imaging device using a 4 phase driving method, a 3 phase driving method or a 6 phase driving method. A single-layer transfer electrode configuration of forming first transfer electrodes and second transfer electrodes by one polysilicon layer is used. Two shunt wirings extending in a horizontal direction are formed on the first transfer electrodes connected in a horizontal direction and, for example, four-phase transfer pulses are supplied to first transfer electrodes and second transfer electrodes on transfer channels through low-resistance shunt wirings extending in the horizontal direction.

Abstract: Embodiments relate to a bipolar junction transistor and a method for manufacturing the same. An oxide pattern may be formed on a P type semiconductor substrate. A low-density N type collector area may be formed in the semiconductor substrate. First spacers may be formed at sidewalls of the oxide pattern, and a low-density P type base area may be formed in the semiconductor substrate. Second spacers may be formed on sidewalls of the first spacers. A high-density N type emitter area may be formed in the low-density P type base area between the second spacers, and a high-density N type collector area may be formed in the semiconductor substrate at an outside of the first spacers. The bipolar junction transistor may be realized through a self-aligned scheme using dual nitride spacers. A base width between the emitter area and the low-density collector area may be narrowed by the width of the second spacer.

Abstract: A high voltage/power semiconductor device has a relatively lowly doped substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer. A low voltage terminal and a high voltage terminal are each electrically connected to the semiconductor layer. The device has a control terminal. The semiconductor layer includes a drift region of a first conductivity type, the substrate being of the second conductivity type. The semiconductor layer includes a relatively highly doped injector region of the second conductivity type between the drift region and the high voltage terminal, said relatively highly doped injector region being in electrical contact with the high voltage terminal and not being connected via any semiconductor layer to the substrate. The device has a relatively highly doped region of the first conductivity type in electrical contact with the said highly doped injector region and the high voltage terminal and forming a semiconductor junction with the substrate.

Abstract: A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

Abstract: A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.

Abstract: In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device.

Abstract: A semiconductor device is provided which comprises a connecting lead 4 mounted between a MOS-FET 1 and a regulatory IC 2 on a support plate 3. Connecting lead 4 has a thermally radiative and electrically conductive substrate 6 and electrically insulative and thermal transfer-resistive covering 7. Substrate 6 has one end 6a providing one main surface 4a of connecting lead 4 which is mounted and electrically connected on the other main surface 1b of MOS-FET 1. Covering 7 provides the other main surface 4b of connecting lead 4 for supporting regulatory IC 2 at one end 6a of substrate 6.

Abstract: Methods of forming a semiconductor device include forming a protective layer on a semiconductor layer, implanting ions having a first conductivity type through the protective layer into the semiconductor layer to form an implanted region of the semiconductor layer, and annealing the semiconductor layer and the protective layer to activate the implanted ions. An opening is formed in the protective layer to expose the implanted region of the semiconductor layer, and an electrode is formed in the opening. A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer.

Abstract: An InGaP buffer layer (3) is formed on a semi-insulating GaAs substrate (1) to a thickness of not less than 5 nm and not greater than 500 nm and an InAlAs layer (4) and an InGaAs channel layer (5) are grown thereon to form a heterostructure. An In segregation effect occurs at the time of forming the InGaP buffer layer (3), so that the region of the InGaP buffer layer (3) near the layer above becomes excessive in In. As a result, the composition of the surface of the InGaP buffer layer (3) becomes very close to the composition of InP, thereby suppressing occurrence of misfit dislocations that can result in degradation of the surface condition. Further, the surface condition of the InAlAs layer (4) and InGaAs channel layer (5) formed thereon can be made good.

Abstract: A transistor epitaxial wafer having: a substrate; an n-type collector layer, a p-type base layer and an n-type emitter layer formed on the substrate in this order; and an n-type InGaAs non-alloy layer having an n-type InGaAs nonuniform composition layer formed on the n-type emitter layer and having an nonuniform indium (In) composition, and an n-type InGaAs uniform composition layer formed on the n-type InGaAs nonuniform composition layer and having a uniform indium (In) composition. The n-type InGaAs nonuniform composition layer has a first layer doped with Si and having a low indium (In) composition, and a second layer formed on the first layer, doped with an n-type dopant except Si, and having an indium (In) composition higher than the first layer.

Abstract: In an insulated gate bipolar transistor, an improved safe operating area capability is achieved according to the invention by a two-fold base region comprising a first base region (81), which is disposed in the channel region (7) so that it encompasses the one or more source regions (6), but does not adjoin the second main surface underneath the gate oxide layer (41), and a second base region (82) is disposed in the semiconductor substrate (2) underneath the base contact area (821) so that it partially overlaps with the channel region (7) and with the first base region (81).

Abstract: A plasma display panel (PDP) may include a first substrate having first discharge electrodes and a first separation border where the first substrate was separated from a first base substrate and a second substrate having second discharge electrodes and a second separation border where the second substrate was separated from a second base substrate.

Abstract: A memory device includes a semiconductor substrate having a surface, a plurality of first and second conductive lines, a plurality of memory cells, and a plurality of landing pads. Each of the first conductive lines has a line width wb and two neighboring ones of the first conductive lines having a distance bs from each other. Each of the second conductive lines has a line width wl and two neighboring ones of the second conductive lines having a distance ws from each other. Each memory cell is accessible by addressing corresponding ones of said first and second conductive lines. Each of the landing pads are made of a conductive material and are connected with a corresponding one of said second conductive lines.

Abstract: A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

Abstract: Programmable resistive RAM cells have a resistance that depends on the size of the programmable resistive elements. Manufacturing methods and integrated circuits for programmable resistive elements with uniform resistance are disclosed that have a cross-section of reduced size compared to the cross-section of the interlayer contacts.

Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Abstract: The present invention provides a semiconductor device capable of suppressing current collapse, and also of preventing dielectric breakdown voltage and gain from lowering so as to perform high-voltage operation and realize an ideal high output. On a substrate (101), there are formed a buffer layer (102) made of a first GaN-based semiconductor, a carrier traveling layer (103) made of a second GaN-based semiconductor and a carrier supplying layer (104) made of a third GaN-based semiconductor. A recess structure (108) is made by eliminating a part of a first insulation film (107) and a part of the carrier supplying layer (104). Next, a gate insulation film (109) is deposited, and then a gate electrode (110) is formed so as to fill up the recess portion (108) and cover on over an area where the first insulation film (107) remains so that its portion on the drain electrode side is longer than that on the source electrode side.

Abstract: A semiconductor device having an improved gate process margin includes two active regions spaced apart from each other on a semiconductor substrate and respectively having bent sides with recesses and protrusions corresponding to each other, and two line-shaped gate patterns respectively formed in the longitudinal directions of the active regions. A gap at which the two gate patterns are spaced apart from each other by the recesses and the protrusions in the active regions is relatively narrower by a width difference between the recesses and the protrusions.

Abstract: A semiconductor device comprising a substrate having a well region, at least one well pickup region formed on the substrate to surround the well pickup region, a first drain region formed on the substrate to be positioned on one side of the source region, and a first gate electrode formed on the substrate to be positioned between the source region and the first drain region.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A semiconductor integrated circuit structure and method for fabricating. The semiconductor integrated circuit structure includes a light sensitive device integral with a semiconductor substrate, a cover dielectric layer disposed over the light sensitive device, and a lens-formation dielectric layer disposed over the cover dielectric layer. Light is transmittable through the cover dielectric layer; and through the lens-formation dielectric layer. The lens-formation dielectric layer forms an embedded convex microlens. The microlens directs light onto the light sensitive device.

Abstract: Provided are a phase change memory device that can operate at low power and improve the scale of integration by reducing a contact area between a phase change material and a bottom electrode, and a method for fabricating the same. The phase change memory comprises a current source electrode, a phase change material layer, a plurality of carbon nanotube electrodes, and an insulation layer. The current source electrode supplies external current to a target. The phase change material layer is disposed to face the current source electrode in side direction. The carbon nanotube electrodes are disposed between the current source electrode and the phase change material layer. The insulation layer is formed outside the carbon nanotube electrodes and functions to reduce the loss of heat generated at the carbon nanotube electrodes.

Abstract: In a phase change memory including an ovonic threshold switch, conduction around the phase change material layer in the ovonic threshold switch is reduced. In one embodiment, the reduction is achieved by undercutting the conductive layers on either side of the phase change material layer. In another embodiment, an angled ion implantation is carried out which damages the edge regions of the conductive layers that sandwich the phase change material layer.

Abstract: A semiconductor device includes a semiconductor substrate, a first and second semiconductor regions formed on the semiconductor substrate insulated and separated from each other, a gate dielectric film formed on the substrate to overlap the first and second semiconductor regions, a floating gate electrode formed on the gate dielectric film and in which a coupling capacitance of the first semiconductor region is larger than that of the second semiconductor region, first source and drain layers formed on the first semiconductor region to interpose the floating gate electrode therebetween, a first and second wiring lines connected to the first source and drain layers, respectively, second source and drain layers formed on the second semiconductor region to interpose the floating gate electrode therebetween, and a third wiring line connected to the second source and drain layers in common.

Abstract: A field effect transistor comprising: a semiconductor layer projecting from the plane of a base; a gate electrode provided on opposite side surfaces of the semiconductor layer; a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer; and source/drain regions where a first conductivity type impurity is introduced, wherein the semiconductor layer has a channel forming region in a portion sandwiched between the source/drain regions, and has in the upper part of the semiconductor layer in the channel forming region a channel impurity concentration adjusting region of which the concentration of a second conductivity type impurity is higher than that in the lower part of the semiconductor layer, and in the channel impurity concentration adjusting region, a channel is formed in a side surface portion facing the gate insulating film of the semiconductor layer in the channel impurity concentration adjusting region in a state of operation in which a signal voltage is

Abstract: This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric linen layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate.

Abstract: A transistor comprising a semiconductor including a source, a drain, and a channel interposed between the source and the drain; a first dielectric layer having a first thickness, the first dielectric layer being positioned on the channel; a second dielectric layer having a second thickness, the second dielectric layer being positioned on the first dielectric layer; and a gate electrode on the second dielectric layer, wherein the transistor gate is made of a mid-gap metal. A process comprising depositing a first dielectric layer on at least one surface of a semiconductor layer; depositing a second dielectric layer on the first dielectric layer; depositing a layer of mid-gap metal on the second dielectric layer; and patterning and etching the first dielectric layer, the second dielectric layer and the layer of mid-gap metal to create a gate electrode separated from the substrate by a first dielectric and a second dielectric. Other embodiments are disclosed and claimed.