Abstract: A semiconductor device is provided with test-subject circuit 1, test-irrelevant circuit 2, first pads used for the test-subject circuit, and second pads used for the test-irrelevant circuit. The first pads include a plurality of divided pad portions while each of the second pads is provided with a single pad portion.

Abstract: A semiconductor device includes a circuit board having an element mounting area, connecting pads positioned in the same surface side as the element mounting area and external connectors to be connected with the connecting pads, respectively; and a semiconductor element mounted on the element mounting area of the circuit board and having electrode pads to be electrically connected with the connecting pads, respectively. The external connectors are detachably configured through a combination of convex portions and concave portions which are mechanically and electrically connected with one another.

Abstract: A new circuit for producing simulated electrostatic discharges (ESD) based on the Human Body Model (HBM) is disclosed for testing integrated circuits. HBM ESD test systems provide stress pulses defined by industry standards. The pulses produced by prior art have small imperfections or anomalies. These anomalies can cause incorrect testing to certain devices. The improved ESD HBM test system herein disclosed provides pulses meeting the requirements of industry standards while reducing several anomalies to negligible levels.

Abstract: A method for testing integrated circuits comprises: generation of a change in an input signal of the integrated circuit, detection of a change in the output signal of the integrated circuit, the change triggered by the change in the input signal when a predetermined condition is satisfied, and a comparison of the detected output signal with at least one predetermined comparison criterion. Whereby, the predetermined condition is derived individually for each integrated circuit from a time response of the output signal.

Abstract: A device and a method are provided for the analysis of a sample plate on which at least two material samples are situated. In the method, one impedance spectrum is measured for each of the material samples. As a function of the respectively measured impedance spectrum, a configuration of a circuit equivalent is determined which includes at least one electronic component. Then, for an error minimization computation, starting values for the components of the respective circuit equivalents are determined. In the error minimization computation, a theoretical impedance spectrum is calculated for at least one of the material samples, based on the impedance spectrum measured for the material sample, as well as the starting values for the components of the respective circuit equivalent, and fit values are determined for the components of the respective circuit equivalent.

Abstract: The present invention discloses an apparatus for detecting a current flowing from a first node to a second node. One or more MOS devices are serially coupled between the first and second nodes. Each of the MOS devices has its body connected to its source and its gate connected to its drain for providing each MOS device with a voltage difference between its gate and its source that is lower than a threshold voltage of the same, such that a voltage difference measured between the first and second nodes responds to a change of the current exponentially.

Abstract: A method for measuring capacitance characteristics of a gate oxide in MOS transistor device. Capacitance characteristics of a gate oxide may be accurately, rapidly, and effectively obtain (e.g. in the form of a capacitance characteristics curve). A method may measure capacitance characteristics of a gate oxide using a characteristics measuring system using an impedance Z—phase angle ? method.

Abstract: According to one embodiment, a logical circuit performs an AND operation based on a mode signal input via a mode terminal and a signal formed by delaying a system reset signal as much as one clock during system reset. The logical circuit outputs a signal indicating a usual operation mode for a predetermined period in response to the system reset signal, and outputs a value of the input mode signal after the predetermined period. This mode signal is held by a selector and a flip-flop, and output to an LSI main body unit.

Abstract: It is configured by plurality of NAND circuits connected in series through a plurality of inverters, and a plurality of NOR circuits connected in series through the plurality of inverters. Each of a plurality of source signal lines provided in a pixel portion is connected to one input terminal of a NAND circuit and a NOR circuit, and an output of an inspection is obtained from final lines of the NAND circuit and the NOR circuit connected in series. In this manner, an inspecting circuit which is capable of determining a defect simply and accurately by using a small-scale circuit, and a method thereof are provided.

Abstract: In a two stage inverter providing power to a load, a first stage component is operable to receive a first voltage input and a first control input to generate a first voltage output, which is higher than the first voltage input. The first control input is indicative of the power provided to the load. The first voltage output varies in response to a change in the first voltage input by a predefined function. A second stage component of the inverter is operable to receive the first voltage output and a second control input to generate the power as an output. The second control input is indicative of the power provided to the load. A controller component of the inverter is operable to receive a feedback input indicative of the power required by the load and generates the first and second control inputs.

Abstract: A method and circuit for static phase error measurement includes a reference clock delay chain having a selectable number of delay elements. A number of the delay elements are enabled in accordance with a select length signal to delay a reference clock signal. A feedback signal delay chain also has a selectable number of delay elements. A number of the delay elements are enabled in accordance with a select length signal to delay a feedback signal. A latch tests phase alignment between the delayed reference clock signal and the delayed feedback signal and outputs a measurement of static phase error.

Abstract: A discharge lamp controlling apparatus includes a detector for detecting a discharge condition of a discharge lamp; a frequency changing unit for gradually changing a frequency of a voltage to be applied to the discharge lamp until the discharge condition reaches a predetermined lighting condition; and a voltage controller for controlling the voltage to be applied to the discharge lamp on the basis of the frequency changed by the frequency changing unit.

Abstract: According to embodiments of the subject matter disclosed in this application, a wide input common mode sense amplifier may include a level shifter stage and an amplifier stage. The level shifter comprises a CMOS differential amplifier that has a rail-to-rail input common mode range. The level shifter accepts two input signals with a common mode voltage in a rail-to-rail range and produces two output signals with a stable common mode voltage. The differential amplifier amplifies the two output signals from the level shifter stage with high gain. The disclosed sense amplifier may be used to measure delay between two discrete time events.

Abstract: Provided are a FET-based sensor for detecting an ionic material, an ionic material detecting device including the FET-based sensor, and a method of detecting an ionic material using the FET-based sensor. The FET-based sensor includes: a sensing chamber including a reference electrode and a plurality of sensing FETs; and a reference chamber including a reference electrode and a plurality of reference FETs. The method includes: flowing a first solution into and out of the sensing chamber and the reference chamber of the FET-based sensor; flowing a second solution expected to contain an ionic material into and out of the sensing chamber while continuously flowing the first solution into and out of the reference chamber; measuring a current in a channel region between the source and drain of each of the sensing and reference FETs; and correcting the current of the sensing FETs.

Abstract: A power down reset circuit for asserting a signal when a first VDD voltage falls below a voltage threshold. The circuit has at least one diode coupled to the first VDD voltage. The at least one diode is configured to produce a second voltage. At least one capacitor is coupled to the at least one diode to maintain the second voltage. A voltage detector asserts a signal when the first VDD voltage drops below a threshold level. The voltage detector is powered by the second voltage and is coupled to the at least one diode.

Abstract: A digital output driver includes a pre-driver and a driver that may be implemented with thin-oxide FETs. The pre-driver generates first and second digital signals based on a digital input signal. The first digital signal has a first voltage range determined by a first (e.g., pad) supply voltage and an intermediate voltage. The second digital signal has a second voltage range determined by a second (e.g., core) supply voltage and circuit ground. The driver receives the first and second digital signals and provides a digital output signal having a third voltage range determined by the first supply voltage and circuit ground. The pre-driver may include a latch and a latch driver. The latch stores the current logic value for the digital input signal. The latch driver writes the logic value to the latch. The latch driver is enabled for a short time duration to write the logic value and is turned off afterward.

Abstract: An output stage interface circuit (50) implemented on a P-substrate comprises a first substrate diffusion isolated main NMOS transistor (MN1) coupling a data output terminal (5) to a first rail (2) which is held at ground, and a second main PMOS transistor MP2 coupling the data output terminal (5) to a second rail (3) to which the power supply voltage VDD is applied. First and second data control signals on first and second data control lines (8) and (9) through first and second primary and secondary buffer circuits (11, 14, 12, 15) selectively operate the first main transistor MN1 and the second main transistor MP2 for determining the logic high and low states of the data output terminal (5).

Abstract: The invention discloses a device for multiplying the pulse frequency of a signal, a pulse train, comprising input means for the signal and means for accessing the signal at points with a predetermined phase difference between them. The device additionally comprises means at a first level for combining accessed signal pairs, with one and the same phase distance within all the combined pairs, the output from each first level combining means being a pulse train. The device additionally comprises combining means at a second level for combining the pulse trains from the first level, and the combining means at the first level are such that the pulses in their output pulse trains have rise flanks which always coincide with the rise flank of the first signal in the combined accessed signal pairs, and fall flanks which always coincide with the fall flanks of the second signal in said pair.

Abstract: A system (101) for clock signal synchronization includes a data analyzer (104) and a synchronized clock signal generator (105) coupled to an RC oscillator (103). The data analyzer (104) generates a digital control signal representing the number of cycles of a reference signal of the RC oscillator (103) during an eight-bit period of an incoming token packet. The synchronized signal clock generator (105) uses the digital control signal to lock a clock signal to packets that have the same bit rate as the token packet.

Abstract: A power supply voltage detection circuit is provided including: a first switch to connect between a power supply voltage terminal and a first terminal according to a power supply voltage detection signal and an external signal; a second switch to connect between a reference potential terminal and a second terminal according to the power supply voltage detection signal and the external signal; a first resistance connected between the second terminal and the power supply voltage terminal; and a third switch connecting between the first terminal and the reference potential terminal according to a voltage of the second terminal; and an output circuit outputting the power supply voltage detection signal based on a signal from the first terminal.

Abstract: A technique includes locking a locked loop circuit onto a reference clock signal. The locking includes locking the lock loop circuit onto the reference clock signal in response to a first feedback signal provided by a first feedback path and locking the locked loop circuit onto the reference clock signal in response to a second feedback signal that is provided by a second feedback path.

Abstract: A completely differential approach to correcting duty-cycle distortions of a differential clock signal propagating through a differential amplifier. A duty-cycle distortion correction (DCDC) differential amplifier circuit/device is provided with a differential amplifier whose output wires are coupled to a correction circuit. The correction circuit comprises a differential low pass filter and a differential correction amplifier. The differential correction amplifier's output is dotted back into the output of the amplifier. The differential output of the amplifier is passed through the low pass filter, which provides differential DC output signals that triggers respective correction amplifier transistors to generate an inverted correction current that is added back to respective differential output pulse. The DCDC differential amplifier provides a completely differential approach to correction of duty-cycle distortions within the differential output.

Abstract: A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A high-high detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.

Abstract: A clock generator includes a first circuit, a second circuit, and a third circuit. The first circuit generates a first clock signal. The second circuit divides the frequency of the first clock signal to generate a second clock signal. The third circuit generates a third clock signal from the first and second clock signals. The third clock signal has the same period as that of the second clock signal, and timing at which the third clock signal changes from a first logic level to a second logic level coincides with timing at which the first clock signal changes from a first logic level to a second logic level.

Abstract: A method and apparatus are disclosed for detecting disturbances in an alternating current (AC) supply. A method includes a step of indicating a relationship between supplied AC voltage and a threshold voltage for at least a portion of each cycle of the supplied AC voltage. A circuit for detecting disturbances in supplied alternating current (AC) is provided. The circuit includes a threshold detector coupled to a source of supplied AC. The threshold detector provides a signal indicating a relationship of the supplied AC levels to a threshold level for at least a portion of each cycle of the supplied AC.

Abstract: Described are controllable termination impedances that may be adjusted collectively by a combination of digital and analog signals. Each adjustable impedance, responsive to the digital signals, establishes a gross termination resistance for one of a plurality of communication channels by enabling one or more of a plurality of parallel-coupled impedance legs. Each leg includes at least one transistor for controlling the impedance of the leg over a continuous range. An analog compensation voltage is level shifted and the resulting level-shifted signal is applied to the control terminals of the transistors of the selected impedance legs. The compensation voltage, and consequently the level-shifted signal, varies with supply-voltage and temperature fluctuations in a manner that causes the collective impedance of the selected legs for each channel to remain stable despite the fluctuations.

Abstract: An electronic circuit has a signal conductor (11), a power supply reference conductor (10) connected by a switching circuit. The switching circuit contains a PMOS transistor (17) and an NMOS transistor realized on a common substrate (100). The NMOS transistor (17) has a source coupled to the power supply reference conductor (10). The NMOS transistor (18) has a source coupled to the drain of the PMOS transistor (17), and a drain coupled to the signal conductor (11). A control circuit (13, 14, 15, 16) switches between an “on” state and an “off” state, in which the control circuit (13, 14, 15, 16) controls the gate source voltages of the first and second MOS transistor (17, 18) to make channels of these MOS transistors (17, 18) conductive and not to make the channels of these first and second transistors (17, 18) conductive respectively. Preferably a complementary switching circuit is also provided.

Abstract: According to one embodiment of the invention a method for switching an alternating current signal between at least two paths includes providing, in at least one of the paths, first and second field effect transistors in series. The method also includes providing a control voltage node operable to receive a control voltage and maintaining each of the first and second field effect transistors in pinch-off mode by offsetting a voltage on each gate of the field effect transistors with a DC voltage component other than the control voltage when it is desired for the alternating current not to flow through the at least one path.

Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.

Abstract: An internal voltage generation apparatus for a semiconductor device is disclosed. The internal voltage generation apparatus includes a power-up detector for receiving an external supply voltage and generating a power-up signal, an internal voltage generator for generating a plurality of internal voltages, and an initial level holder including a plurality of transistors for supplying the external supply voltage to the internal voltage generator in response to the power-up signal, and a plurality of passive elements connected in parallel with the transistors, respectively.

Abstract: In a basic circuit of a booster circuit, two charging units perform a charging operation and two boosting units perform a boosting operation (discharging operation). One of the charging units is connected to a voltage input and the other is connected to a voltage output. The charging unit that is connected to the voltage input includes three parallel connected MOS transistors Q11, Q21, and Q13, the other charging unit includes a MOS transistor Q4. One of the boosting units is connected to the voltage input and the other is connected to the voltage output. The boosting unit that is connected to the voltage input includes three parallel connected MOS transistors Q31, Q32, and Q33, the other boosting unit includes a MOS transistor Q2. Q11 and Q31 are turned ON immediately after start up, then Q12 and Q22 are turned ON operation, and finally Q13 and Q23 are turned ON.

Abstract: An integrated circuit (10), preferably a field programmable gate array—FPGA or an application specific integrated circuit—ASIC—, comprises a level comparator (30) for comparing a level of a comparator input signal and correspondingly providing a comparator output signal (COS). A sampling unit (40) is coupled to the level comparator (30) for sampling (SAM) the comparator output signal (COS). A bit error test unit (60) receives the sampled comparator output signal (SAM) and determine therefrom an indication of a bit error in a sequence of the sampled comparator output signal (SAM).

Abstract: A wireless sensor device of low energy consumption operates over a prolonged period of time for providing a reliable sensor result. The wireless sensor device includes a sensor configured to sense a target object and provide a sensor signal of varying levels indicative of condition of the target object, a signal processing circuit configured to amplify the sensor signal and give an amplified electric analog signal, and a detection circuit configured to receive the amplified analog signal and provide a detection output when the electric analog signal goes beyond a predetermined detection threshold. Also included in the device is a radio transmitter which transmits a radio detection signal in response to the detection output. Further, the device includes a power supply configured to provide an electric power to the signal processing circuit and the radio transmitter; and a power generating element which converts an external energy into the electric power to be accumulated in the power supply.

Abstract: An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transistors have a common conduction terminal connected to an output terminal of the output buffer. An input terminal of the buffer is connected to control terminals of the transistors of the first stage through a first open loop driving circuit. A second feedback driving circuit is connected between the input terminal and the control terminals of the transistors of the second stage. The second feedback driving circuit includes a current detector operating to detect a maximum in the value of the current drawn by and supplied to the output buffer. A comparison block, having a threshold value, detects current in excess of the threshold value and processes information coming from the current detector to regulate an output impedance value of the output buffer.

Abstract: A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature.

Abstract: A voltage reference generating method, source, memory device and substrate containing the same include a voltage reference generator comprised of a bandgap voltage reference circuit including a first complementary-to-absolute-temperature (CTAT) signal and a second complementary-to-absolute-temperature (CTAT) signal. The voltage reference generator further includes a differential sensing device for generating a reference signal substantially insensitive to temperature variations over an operating temperature range by differentially sensing the first and second CTAT signals. The method includes generating first and second complementary-to-absolute-temperature (CTAT) signals and generating a reference signal that is substantially insensitive to temperature variations over an operating temperature range.

Abstract: A power gating structure controls a connection between a power supply terminal and a virtual power supply node so as to operate a logic circuit in a plurality of operation modes. The power gating structure includes a first path and a second path. In an active mode, the first path electrically couples the power supply terminal with the virtual power supply node in response to a first control signal. In a data retention mode, the second path electrically couples the power supply terminal with the virtual power supply node in response to the first control signal and a second control signal with a predetermined voltage level difference. In a power-down mode, both the first path and the second path electrically isolate the power supply terminal from the virtual power supply node in response to the first control signal and the second control signal.

Abstract: A biquad gain stage, as well as a Variable Gain Amplifier is disclosed. The biquad gain stage comprises a plurality of transistors as well as conductances, and capacitances, as well as current sources. The resulting variable gain amplifier comprising a plurality of biquad gain stage cascaded in series allows to filter large unwanted blockers and to amplify a small wide-band signal. Both the gain and the filtering are distributed along a signal chain comprising a series of low-noise, high-Q biquad gain stages, each with limited current consumption and low component ratios.

Abstract: A PPM signal demodulator for demodulating a PPM signal transmitted in a UWB radio communication system includes a rectifier for rectifying a received PPM signal to obtain an absolute value signal, integrator and comparators for integrating the absolute value signal for every first, second and third integral times and comparing the integrated values for the integral times, absolute value circuits for converting respective outputs of the integrator and comparators to corresponding absolute values, moving average circuits for moving-averaging respective outputs of the absolute value circuits, a determining circuit for generating demodulation data on the basis of the integrated and compared result by the integrator and comparator, and a main control for generating, on the basis of the outputs of the moving average circuits, integral interval control signals that control the first, second and third integral times to supply them to the respective integrator and comparators.

Abstract: A timing adjusting method detects a phase error between a main signal path from which a transmitting signal is obtained and a control signal path from which a voltage control signal is obtained, based on a to-be-amplified signal that is to be amplified and represents an amplitude or a power of the transmitting signal prior to amplification and a feedback signal that represents an amplitude or a power of the transmitting signal after the amplification, adjusts an amount of delay of at least one of the main signal path and the control signal path so as to mutually cancel the phase error, and amplifies the transmitting signal from the main signal path depending on the voltage control signal from the control signal path. The detecting the phase error may include detecting polarity transition points of a slope of a waveform of the to-be-amplified signal or the feedback signal, and measuring the phase error using the detected polarity transition points.

Abstract: In a circuit and a method for amplification of an electrical input signal, a signal splitter divides the input signal into a first partial signal in a first signal path and a second partial signal in a second signal path. The first signal path has a first amplification stage for amplification of the first partial signal and the second signal path has a second amplification stage for amplification of the second partial signal. Each of the two amplification stages is supplied with current by a current supply device. Both amplified partial signals are recombined into an output signal by a signal combination element downstream from the amplification stages.

Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Abstract: An apparatus for calibrating the non-linearity of an RF power amplifier is provided. In an amplification apparatus for the RF power amplifier, a main amplification portion up converts an input baseband digital signal to a time variant input analog signal, and amplifies the input analog signal to a power level. A distortion generation portion generates a digital distortion signal using the input baseband digital signal and a reference value, up converts the digital distortion signal to a time variant analog distortion signal, and amplifies the analog distortion signal to the power level. The power combiner generates a distortion-free main amplification signal as a final output signal of the RF power amplifier by adding the main amplification signal received from the main amplifier to the amplified distortion signal.

Abstract: A power amplifier includes: an active device having at least one heterojunction bipolar transistor based on a compound semiconductor; a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; a resistor connected in series between the diode and the base of the bipolar transistor; and a bias circuit connected between the diode and the resistor. A power amplifier may alternatively includes: an active device having at least one heterojunction bipolar transistor based on a compound semiconductor; a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; two resistors connected in series between the diode and the base of the bipolar transistor; and a bias circuit connected between the two resistors.

Abstract: A CMOS amplifier of a filter for an ultra wideband application and a method of the same are provided. In the CMOS amplifier, an active load circuit adds a Zero location and increases a gain by MOSFETs, feeding back operation, and has a property of a high gain and a wide bandwidth. When the CMOS amplifier is applied to a biquad LPF, a high voltage linearity over about 200 mV peak-to-peak and an suitable ultra wideband property over about 320 MHz of an cutoff frequency may be achieved.

Abstract: A differential amplifying circuit capable of reducing amplitude-difference deviation over a full range of grayscale voltages inclusive of voltages in the vicinity of power-supply voltage includes first and second differential pairs of mutually different polarities, in which the outputs of the differential pairs are coupled by a coupling stage. One of the first and second differential pairs receives an input signal from an input terminal and a feedback signal from an output terminal at a pair of inputs thereof, and the other differential pair receives reference signals (which may be of the same voltage), which have voltage levels that set the other differential pair transistors to an on-state, at a pair of inputs of the other differential pair.

Abstract: Disclosed is a differential amplifier which comprises a differential pair comprising depletion-type first and second N-channel MOS transistors, a first current source that supplies a current for the differential pair, a current mirror circuit formed by transistor pairs connected in cascode fashion in two stages, for connecting an output pair of the differential pair in folded connection, second and third current sources connected to an input terminal of the current mirror circuit and an output terminal of the current circuit, respectively, and a buffer amplifier with that has an input terminal connected to the output terminal of the current mirror circuit and has an output terminal connected to an output terminal of the differential amplifier.

Abstract: A differential amplifying circuit that includes a differential pair and a cascode current mirror circuit that forms the load circuit of this differential pair. The cascode current mirror circuit includes a control-terminal-coupled first transistor pair, and second and third transistor pairs that receive first and second bias signals at coupled control terminals, respectively. The second transistor pair is straight-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit, and the third transistor pair is cross-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit. The second and third transistor pairs are controlled so as to each be placed in active and inactive states by changing over voltage values of the first and second bias signals, with control being exercised in such a manner that when one of these transistor pairs is in an active state, the other is in an inactive state.

Abstract: Variable gain amplifier includes signal amplifying transistor, and gain control transistors at output and non-output sides. Emitters or sources of gain control transistors at output and non-output sides are connected to collector or drain of signal amplifying transistor. Output load is connected between collector or drain of gain control transistor at output side and power source side. Load is connected between collector or drain of gain control transistor at non-output side and power source side. Output load and load have the same impedance. Negative feedback path is connected between output end of gain control transistor at output side and input end of signal amplifying transistor. Negative feedback path is also connected between output end of gain control transistor at non-output side and input end of signal amplifying transistor. Two negative feedback paths have the same circuit constant. A differential amplifier is formed of a pair of such variable gain amplifiers.

Abstract: A transconductance input apparatus energized by supply voltage has an input for receiving an input signal, and an output for delivering an output signal. The apparatus also has a plurality of transconductance stages for converting the input signal into the output signal, which is substantially free of dead zones when the total supply voltage is 2.7 volts or less.