Abstract: In a Group III nitride compound semiconductor light-emitting device which outputs lights from a semiconductor plane, about 1.5 ?m in height of a Group III nitride compound semiconductor projection part 150, which is made of Mg-doped p-type GaN having Mg doping concentration of 8×1019/cm3 and is formed through selective growth, is formed on a p-type contact layer (second p-layer) 108. And a light-transparency electrode 110 is formed thereon through metal deposition. The Group III nitride compound semiconductor projection part 150 makes a rugged surface for outputting lights and actual critical angle is widened, which enables to improve luminous outputting efficiency. And because etching is not employed to form the ruggedness, driving voltage does not increase.

Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

Abstract: An apparatus and method for detecting electromagnetic radiation employs a deflectable micromechanical apparatus incorporating multiple quantum wells structures. When photons strike the quantum-well structure, physical stresses are created within the sensor, similar to a “bimetallic effect.” The stresses cause the sensor to bend. The extent of deflection of the sensor can be measured through any of a variety of conventional means to provide a measurement of the photons striking the sensor. A large number of such sensors can be arranged in a two-dimensional array to provide imaging capability.

Abstract: The present invention relates to solutions of organic semiconductors and their use in the production of electronic components.

Abstract: Modular fluidic microchips, systems integrating such microchips, and associated preparative and analytical methods are presented.

Abstract: Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film. LDD region is formed by using the first gate electrode as a mask, and a source region and a drain region are formed by using the second gate electrode as a mask. By removing a portion of the second gate electrode, a structure in which a region where LDD region and the second gate electrode overlap with a gate insulating film interposed therebetween, and a region where LDD region and the second gate electrode do not overlap, is obtained.

Abstract: A double gate silicon over insulator transistor may be formed wherein the bottom gate electrode is formed of a doped diamond film. The doped diamond film may be formed in the process of semiconductor manufacture resulting in an embedded electrode. The diamond film may be advantageous as a heat spreader.

Abstract: An n-type layer of the opposite conduction type composed of n-GaN is formed between a light emitting layer and a p-type cladding layer composed of p-AlGaN. The bandgap of the n-type layer of the opposite conduction type is larger than the bandgap of the light emitting layer and is smaller than the bandgap of the p-type cladding layer.

Abstract: A light emitting die package is disclosed. The die package includes a substrate, a reflector plate, and a lens. The substrate may be made from thermally conductive but electrically insulating material or from a material that is both thermally and electrically conductive. In embodiments wherein the substrate is made from an electrically conductive material, the substrate further includes an electrically insulating, thermally conductive material formed on the electrically conductive material. The substrate has traces for connecting to a light emitting diode (LED) at a mounting pad. The reflector plate is coupled to the substrate and substantially surrounds the mounting pad. The lens substantially covers the mounting pad. Heat generated by the LED during operation is drawn away from the LED by both the substrate (acting as a bottom heat sink) and the reflector plate (acting as a top heat sink). The reflector plate includes a reflective surface to direct light from the LED in a desired direction.

Abstract: In a liquid crystal display device, a recessed portion is formed in a portion of a periphery of a lower frame, a columnar member is provided to the recessed portion, the columnar member is allowed to pass through a hole formed in a projecting portion which is provided on an optical sheet, and a side surface of a liquid crystal panel is brought into contact with the columnar member. The columnar member provided on the lower frame not only determines the position of the liquid crystal panel with respect to the lower frame, but also determines the position of the optical sheet with respect to the lower frame and firmly holds the optical sheet onto the lower frame, thus preventing the disengagement of the optical sheet from the lower frame.

Abstract: A method of fabricating an integrated circuit sensor package. The method comprises the steps of: 1) mounting a substrate on a first mold block, the substrate comprising a substantially planar material having a first substrate surface and a second substrate surface that contacts a mounting surface of the first mold block; 2) placing an adhesive on the first substrate surface; 3) placing an integrated circuit sensor on the adhesive; and 4) pressing a second mold block against the first substrate surface. The second mold block comprising a cavity portion for receiving the integrated circuit sensor, a contact surface surrounding the cavity portion, and a compliant layer mounted with the cavity portion. Pressing the second mold block against the first substrate surface causes the contact surface to form with the first substrate surface a seal surrounding the integrated circuit sensor.

Abstract: The present invention is to provide a group III nitride tunneling junction structure with a low tunneling potential barrier, in which Si layer or a group III-V compound semiconductor In(a)Ga(b)Al(c)As(d)[N]P(e) (0?a?1, 0?b?1, 0?c?1, 0?d?1, 0?e?1) which has a smaller band gap than that of Al(x)Ga(y)In(z)N (0?x?1, 0?y?1, 0?z?1) and can be doped with a high concentration of p is inserted into a tunneling junction based on a P++-Al(x)Ga(y)In(z)N (0?x?1, 0?y?1, 0?z?1) layer and a N++-Al(x)Ga(y)In(z)N (0?x?1, 0?y?1, 0?z?1) layer. This tunneling junction structure will be useful for the fabrication of a highly reliable ultrahigh-speed optoelectronic device.

Abstract: A power semiconductor device comprises a semiconductor substrate, a gate electrode region (control electrode region), a cathode electrode region (first main electrode region), an anode electrode region (second main electrode region) and a guard ring. The semiconductor substrate has a side surface portion having a vertical portion formed substantially vertical to a main surface and a mesa portion connected to the vertical portion in a cross section. The gate electrode region is formed in a first main surface of the semiconductor substrate. The cathode electrode region is formed in part of a surface of the gate electrode region. The anode electrode region is formed in a second main surface of the semiconductor substrate. The guard ring is formed in the second main surface of the semiconductor substrate and annularly surrounds the anode electrode region.

Abstract: A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.

Abstract: A solid state image pickup device comprising: a semiconductor substrate having a surface layer; charge storage regions disposed in the surface layer; vertical channels disposed in the surface layer adjacent to respective columns of the charge storage regions; vertical transfer electrodes formed above the semiconductor substrate, crossing the vertical channels; a horizontal channel disposed in the surface layer coupled to the vertical channels, having a first portion with transfer stages, each including a barrier region and a well region, and a second portion constituting a gate region with gradually decreasing width, and including an upstream region and a downstream region of different effective impurity concentration, establishing a built-in potential; horizontal transfer electrodes disposed above respective transfer stages of the horizontal channel; an output gate electrode disposed above the gate region; a floating diffusion region disposed in the surface layer coupled to the gate region of the horizontal

Abstract: In a field effect transistor, an Si layer 11, an SiC (Si1?yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.

Abstract: A method for making a filed-effect semiconductor device includes the steps of forming a gate electrode on a semiconductor layer composed of a gallium nitride-based compound semiconductor represented by the formula AlxInyGa1?x?yN, wherein x+y=1, 0?x?1, and 0?y?1; and forming a source electrode and a drain electrode by self-alignment using the gate electrode as a mask. A field-effect semiconductor device fabricated by the method is also disclosed.

Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semi-conductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.

Abstract: A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.

Abstract: A low programming power, high speed EEPROM device is disclosed which is adapted for large scale integration. The device comprises a body, a source, a drain, and it has means for injecting a programming current into the body. The hot carriers from the body enter the floating gate with much higher efficiency than channel current carriers are capable of doing. The drain current of this device is controlled by the body bias. The device is built on an insulator, with a bottom common plate, and a top side body. These features make the device ideal for SOI and thin film technologies.

Abstract: A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).

Abstract: A solid state imaging device and a method for manufacturing the same that prevents the reproduction characteristic of an optical image from being affected by diagonal light on a semiconductor substrate surface. A CCD image sensor includes a semiconductor substrate, light receiving pixels formed on the semiconductor substrate, and a color filter arranged above the light receiving pixels and including filters transmitting light having different wavelengths. Dummy wires, which shield light that passes through the color filter and which are electrically isolated from clock wires, are arranged at locations corresponding to boundaries of regions, each defining one of the light receiving pixels.

Abstract: A semiconductor memory device includes a substrate having a semiconductor element formed thereon, an interlayer dielectric layer formed above the substrate, a plug formed in the interlayer dielectric layer, an adhesion layer formed in a region including a region above the plug, and a ferroelectric capacitor formed above the adhesion layer and having a lower electrode, a ferroelectric layer and an upper electrode, wherein an oxidized layer is formed in a part of the adhesion layer at a side wall thereof.

Abstract: A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and a dielectric film is formed along the sidewalls of the deep trench. A masking layer is patterned such that a portion of the dielectric film is covered by the masking layer and a remaining portion of the dielectric film is exposed. An upper region of the exposed portion of the dielectric film is removed such that a trench collar is formed along a middle portion of a side of the deep trench. The deep trench is partly filled with doped polysilicon. The dopants in the polysilicon diffuse through the side of the deep trench into adjoining regions of the semiconductor substrate during subsequent thermal processing steps to form a buried strap region along a side of the deep trench.

Abstract: A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a vertical embodiment, the diffusion regions are formed at the bottom of the trenches and the tops of the mesas formed by the trenches. An enriched region is formed in the substrate adjacent to and substantially surrounding each diffusion region in the substrate. Each enriched region has a matching conductivity type with the substrate. A gate insulator stack is formed over the substrate and each of the plurality of select gates. A word line is formed over the gate insulator stack.

Abstract: A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film formed on the dielectric film. The dielectric film of the capacitive element is crystallized. The first and second conductive films are made of a polycrystal of an oxide, a nitride or an oxynitride of a noble metal.

Abstract: Apparatus for an on-chip decoupling capacitor. The capacitor includes a bottom electrode that consist of nanostructures deposited over a planarized metal, a dielectric material deposited over the nanostructures, and a top electrode deposited over the dielectric material. The shape of the bottom electrode is tunable by modulating the diameter and/or the length of the nanostructures to produce an increase in capacitance without increasing the footprint of the on-chip decoupling capacitor.

Abstract: This nonvolatile semiconductor memory includes: a first and a second memory cell column having memory cell transistors connected in series with a floating gate and a first and a second control gate located at both sides of that floating gate; a first select-gate transistor connected between the first memory cell column and a bit line; a second select-gate transistor connected between the second memory cell column and the bit line; and a third select gate transistor connected between the first memory cell column and a source line and also between the second memory cell column and the source line, respectively.

Abstract: A non-volatile memory array including memory units which are arranged in a row/column array is provided. Source lines are arranged in parallel in the column direction and connect to the source regions of the memory units in the same column. Bit lines are arranged in parallel in the row direction and connect to the drain regions of the memory units in the same row. Word lines are arranged in parallel in the column direction and connect to the select gates of the memory units in the same column. Control lines are arranged in parallel in the column direction and connect to the control gates of the memory units in the same column. The control lines are grouped into several groups with n control lines (n is a positive integer not less than 2) in one group, and the control lines in each group are electrically connected to each other.

Abstract: A 2-bit cell is made up of first and second diffusion regions provided on a substrate surface, first and second storage nodes adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second storage nodes, a third storage node provided on the substrate and a third gate electrode provided on the third storage node. The first and second gate electrodes are connected common to form word line electrodes. A control gate electrode at right angles to the word line electrodes and a third diffusion region in the substrate surface disposed at a longitudinal end of the control gate electrode are provided. A storage node, Node 1, of interest, with the control gate channel as a drain, is read without the intermediary of the second node, which is not of interest, such that reading of Node 1 unaffected by the second node.

Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.

Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film, and a second nitride film, which are formed on a sidewall of an upper portion of the gate electrode, and a gate sidewall insulating film having a two-layered structure formed of the oxide film and the second nitride film, which are formed on a sidewall of a lower portion of the gate electrode. The semiconductor apparatus further comprises a raised source/drain region formed of an impurity region formed in a surface layer of the semiconductor substrate and an impurity region grown on the impurity region.

Abstract: A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200, 300, 400) that includes a semiconductor substrate (110, 210, 310, 410) having a first conductivity type and buried semiconductor region (115, 215, 315, 415) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120, 220, 320, 420) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130, 230, 330, 430) having the first conductivity type located above the first semiconductor region, a third semiconductor region (140, 240, 340, 440) having the second conductivity type located above the first semiconductor region, an emitter (150, 250, 350, 450) having the first conductivity type disposed in the third semiconductor region, and a collector (170, 270, 370, 470) having the first conductivity type disposed in the third semiconductor region.

Abstract: On an SOI substrate, a hydrogen ion implantation section in which distribution of hydrogen ions peaks in a BOX layer (buried oxide film layer), and a single-crystal silicon thin-film transistor are formed. Then this SOI substrate is bonded with an insulating substrate. Subsequently, the SOI substrate is cleaved at the hydrogen ion implantation section by carrying out heat treatment, so that an unnecessary part of the SOI substrate is removed, Furthermore, the BOX layer remaining on the single-crystal silicon thin-film transistor is removed by etching. With this, it is possible to from a single-crystal silicon thin-film device on an insulating substrate, without using an adhesive. Moreover, it is possible to provide a semiconductor device which has no surface damage and includes a single-crystal silicon thin film which is thin and uniform in thickness.

Abstract: A semiconductor integrated apparatus, including: an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film; an NMOSFET, a PMOSFET and an FBC (Floating Body Cell) formed on the SOI substrate separately from each other; a p type of first well diffusion region formed along the embedded insulation film in the support substrate below the NMOSFET; an n type of second well diffusion region formed along the embedded insulation film in the support substrate below the PMOSFET; and a conduction type of third well diffusion region formed along the embedded insulation film in the support substrate below the FBC.

Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Abstract: A driving circuit and a data-line driver is provided which are capable of improving the tolerance to noise between adjacent terminals by using a conventional CMOS process while keeping the chip size small, because a high-density N-diffusion layer (116) is provided in an isolation region (115) to minimize a collector current of a parasitic NPN transistor (102).

Abstract: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Abstract: A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). Each row has a first part (1102) and a second part (1108). A first conductor (750) is coupled to a respective column of memory cells in each first part. A second conductor (752) is coupled to a respective column in each second part. A third conductor is coupled to a control terminal of each memory cell in the first part (1102) of a first row and the second part (1108) of a second row.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of a source and a drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometaric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequity: (X/Y)>(X0/Y0).

Abstract: An electronic system includes a three terminal device having a light emitting portion and a magnetically sensitive portion. The magnetically sensitive portion is for modulating light emission from the light emitting portion. The device is a spin valve transistor having a light-emitting quantum well in its collector. The device can convert a magnetic digital signal to both an electrical digital signal and an optical digital signal, wherein either or both of these signals can be provided as a device output. The magnetically sensitive portion of the device is formed of a pair of magnetically permeable layers. When the layers are aligned electron current can pass through with sufficient energy to reach a quantum well where they recombine, generating light. The device may be used to read a magnetic storage medium, such as a disk drive. Or it can be used to provide a display or a memory array composed of single device magnetic write, optical read memory cells.

Abstract: The present invention is a semiconductor module (20) in which, for example, twenty-five semiconductor devices (10) with a pnotoelectric conversion function are arranged in the form of a five row by five column matrix via an electrically conductive mechanism including of six connecting leads (21 to 26). The semiconductor devices (10) in each column are connected in series, and the semiconductor devices (10) in each row are connected in parallel. Positive and negative terminals, which are embedded in a light transmitting member (28) made of a transparent synthetic resin and which protrude to the outside, are also provided. The semiconductor device (10) comprises a diffusion layer, a pn junction, and one flat surface on the surface of a spherical p-type semiconductor crystal, for example.

Abstract: A capacitor includes a first electrode and a second electrode arranged so that a main surface of the first electrode opposes a main surface of the second electrode, a first pseudo electrode layer disposed on the main surface of the first electrode, and a dielectric layer disposed between the first pseudo electrode layer and the main surface of the second electrode. The first pseudo electrode layer includes conductive particles electrically coupled to the first electrode.

Abstract: A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region; a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region; wherein each of the pillars is substantially free of stringers.

Abstract: Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.

Abstract: A semiconductor substrate which effectively prevents a chipping phenomenon, wherein the outer peripheral extremity of the insulation layer is located between the outer peripheral extremity of the semiconductor layer and the outer peripheral extremity of the support member, and wherein the semiconductor layer and the insulation layer produce a stepped profile.

Abstract: An electrical component includes a substrate, a first integrated circuit attached to the substrate, a metal portion coupled to the first integrated circuit, and a second integrated circuit attached to the first integrated circuit. The metal portion is sandwiched between the first integrated circuit and the second integrated circuit.

Abstract: A semiconductor device mountable on a wiring board with the bottom surface being opposed to the wiring board including a semiconductor chip; a mold resin encapsulating the semiconductor chip; a first heat spreader joined to the semiconductor chip on the bottom surface side with both ends protruding from the mold resin, the first heat spreader being capable of being joined to the wiring board at both ends; and a second heat spreader joined to the semiconductor chip on a top surface side with both ends thereof protruding from the mold resin, the second heat spreader being capable of being joined to the wiring board at both ends. One of the heat spreaders is a lead frame electrically connected to the semiconductor chip. The first and second heat spreaders are substantially entirely covered with the mold resin on the bottom surface side and the top surface side, respectively.

Abstract: The invention relates to a lead-frame configuration with a frame base and multiplicity of lead-frames connected with the frame base, of which each lead-frame is intended to hold a chip, where each lead-frame has two connection plates of which each is intended to connect with a connection of a chip, where the two connection plates of each lead-frame delimit a bridging zone which can be bridged using a chip.

Abstract: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said leadframe suitable for bonding wire attachment and solder attachment.