Abstract: A system and method of balancing state of charge among plural series connected electrical energy storage unit is provided. Individual storage units are selectively coupled by semiconductor switches for monitoring and balancing state of charge. When the state of charge of a selected unit is greater than a target state of charge, energy is transferred from the selected unit to the string of storage units, such that the state of charge of the selected unit converges toward the target state of charge. Conversely, when the state of charge of a selected unit is less than a target state of charge, energy is transferred from the string of storage units to the selected unit, such that the state of charge of the selected unit converges toward the target state of charge.

Abstract: The present invention provides a power converter for recreational vehicle (RV) batteries that uses time and ambient temperature to control output voltage. By employing a remote temperature sensor attached to the battery post, temperature information is sent to an output voltage control circuit in the power converter. When the power converter is powered up an internal timing circuit increases the output voltage by a preset amount for a timed period for rapid charging but is also adjusted to predetermined temperature curve controlled by the remote temperature sensor to prevent overcharge. The output voltage is held at the increased value until the internal timing circuit times out and the output voltage is reduced (setback) to the float voltage determined by the remote temperature sensor.

Abstract: Polarized electric charge storage devices economically provide high available capacitance. The present invention directly employs polarized electrical charge storage (PECS) devices such as polarized capacitors or electrochemical batteries in general AC applications with a novel circuit topology. In one embodiment, an anti-series configuration of first and second PECS devices are used within an AC network for enhancing operation of the AC network. At least one DC source is provided for maintaining the PECS devices forwardly biased while they are subjected to an AC signal. The AC signal, which drives an AC load, is applied to the anti-series devices. The devices are sufficiently biased by the at least one DC voltage source so that they remain forwardly biased while coupling the AC signal.

Abstract: An improved regulator system is disclosed for controlling a field winding of an alternator to regulate the charging of a battery. The improved regulator system comprises an internal regulator mounted onto the alternator. The internal regulator has an internal regulator control circuit for monitoring the battery and for controlling the field winding. An electrical connector actuates the internal regulator to regulate the output of the alternator in accordance with the internal regulator. The electrical connector enables an external regulator to be connected to the alternator thereby bypassing the internal regulator to regulate the output of the alternator in accordance with the external regulator. The improved regulator system facilitates the connection of an upgrade external regulator with the internal regulator functioning as a reserve regulator in the remote event of a malfunction of the external regulator.

Abstract: There is provided an energy discharge apparatus for dissipating a quantity of stored magnetic energy in a generator field coil of a brushless generator. The apparatus includes an exciter regulator responsive to an output signal of the generator and which provides an exciter field signal, and an exciter field coil responsive to the exciter field signal and which provides an exciter magnetic field, and an exciter armature coil responsive to the exciter magnetic field and which provides an exciter armature signal. The apparatus further includes a control circuit responsive to the exciter armature signal, and a variable impedance in series with the generator field coil and responsive to the control circuit. The variable impedance serves to dissipate the quantity of stored magnetic energy. In another embodiment the apparatus includes a positive feedback circuit responsive to the exciter armature signal and operable to dissipate the quantity of stored magnetic energy.

Abstract: A voltage regulator includes a voltage source for providing an input voltage and circuitry for regulating the input voltage to provide an output voltage. The circuitry for regulating the input voltage includes at least a high side switch and a low side switch. A skip mode controller controls the high side switch and the low side switch in order to minimize conduction losses and switching losses within the voltage regulator.

Abstract: The present invention discloses a DC-to-DC step-up converter to which a logic control unit is added in order to reduce the ripples of a DC output voltage and improve the power quality. The converter of the present invention comprises a step-up circuit, a ring oscillator, a divider circuit, a PFM (pulse frequency modulation) comparator and a logic control unit. The step-up circuit is used to step up a source voltage to generate a DC output voltage. The ring oscillator is used to generate an oscillator output signal. The divider circuit receives the DC output voltage to generate a feedback voltage. The PFM comparator compares the feedback voltage with a reference voltage to generate a comparator output signal to control outputting of the oscillator output signal.

Abstract: A low dropout voltage regulator apparatus is disclosed, which includes a low dropout voltage regulator circuit connected to a supply voltage, wherein at least one input voltage is input to the low dropout voltage regulator circuit to generate at least one output voltage from the low dropout voltage regulator circuit. A feedback compensation component is also provided, which is integrated with the low dropout voltage regulator circuit. The feedback compensation component is located generally within the low dropout voltage regulator circuit to take advantage of a Miller effect associated with the low dropout voltage regulator circuit in order to withstand high voltages associated with the supply voltage and generate the output voltage from the low dropout voltage regulator circuit.

Abstract: In a driver circuit constructing a switching power supply device that switches power transistors passing a current through a coil by a PWM mode, a current detection transistor, which is smaller in size than the low-potential side power transistor and a current detection resistor are provided in parallel to the low-potential side power transistor. The same control voltage as the power transistor is applied to the control terminal of the current detection transistor. An operational amplifier is formed, that has the potential of the connection node between the current detection transistor and the current detection resistor applied to its inverse input terminal and a feedback loop, so as to make a pair of input terminals of the operational amplifier be at the same potential. A signal produced by the current detection resistor is thus outputted as a current detection signal.

Abstract: The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency or set of frequencies and a predetermined amplitude. The energizing signal is coupled to the sensor via magnetic coupling and induces a current in the sensor which oscillates at the resonant frequency of the sensor. The system receives the ring down response of the sensor via magnetic coupling and determines the resonant frequency of the sensor, which is used to calculate the measured physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal.

Abstract: A system is useful for positioning a load, such as a test head. The system includes an arm which supports the load and which moves along a first vertical axis. The system also includes a rotation unit for rotating the first vertical axis about a second vertical axis spaced apart from the first vertical axis.

Abstract: A fixture for functional testing of an assembled wireless device, the wireless device having a data port and a removable casing concealing a battery cavity having battery contacts, the fixture comprising: a base having an opening formed therein for receiving a retainer, the retainer being rotatably mounted in the opening for rotating from a first position to a second position, the retainer for receiving the wireless device with the removable casing removed while in the first position; a connector mounted in the retainer for engaging the data port of the wireless device when the wireless device is received by the retainer in the first position; and, a battery emulator insert rotatably mounted on the base, the battery emulator insert having power contacts for engaging the battery contacts in the battery cavity of the wireless device when the retainer is rotated to the second position.

Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

Abstract: The invention relates to a device for determining the path of an in particular metallic target, with at least two detection devices so positioned along a path to be monitored that the sensitivity curves of immediately adjacent detection devices at least partly overlap, the detection devices in each case having at least one inductance coil and at least one oscillator and as a function of a damping of the oscillator by the target supply a distance signal, with at least one converting device operatively connected to the detection devices for converting the dampings detected by the detection devices into analog signals, particularly current and/or voltage signals, and with at least one evaluating device operatively connected to the converting device or devices for determining and reading out a local position of the target from the analog signals going back to the detection devices.

Abstract: A vane actuated drive mode sensor is generally composed of two primary components, including a drive mode sensor array and an actuator. The sensor array can be provided as a housing composed of a plurality of Hall Effect (HE) sensors, magnets and the electronics associated with the sensors. The actuator, also referred to as a vane, can be provided as a plate constructed from a magnetic material, such as, for example, ferrous steel, and can be provided with holes punched thereon at different places depending on the requirement of a user. The actuator can be connected to a user's driver and can slide on and/or within the housing.

Abstract: A sensor-equipped hub unit comprises a hub unit 1 having a wheel-side raceway member 4, a body-side raceway member 5, and two rows of rolling bodies 6, and a sensor device 2 provided on the hub unit 1. The sensor device 2 has a magnetostrictive sensor 31 for detecting a reverse magnetostrictive effect of the raceway member 4 produced by a force exerted thereon by the rolling bodies 6. The sensor device 2 detects rotation from the number of repetitions of a variation in strain and also detects the force acting on the wheel-side raceway member 4 from the amplitude of strain.

Abstract: A 3D MRI image is acquired as a series of spherical shells of increasing radius. Each shell is sampled by one or more interleaved spiral sampling trajectories and to shorten the scan time one or more spiral sampling trajectories are skipped in the larger shells that sample the periphery of k-space. Motion correction of the acquired k-space data is accomplished by reconstructing tracking images from each of the shells and locating markers therein which indicate object movement from a reference position. The k-space data is corrected using this movement information.

Abstract: In a method and MRI apparatus for the minimization of streak artifacts in modular k-space scanning in magnetic resonance imaging, an odd integer k-space scanning module number N?=2n+1 is defined that defines the number of incrementally rotated repeated modules of the k-space scanning process, a slice selection gradient selects any slice in the range of the object to be examined, and data for all N? angle-oriented k-space scanning modules in the selected slice acquired such that each k-space scanning module has an azmuthal distance of ? ? ? ? 2 = 360 ? ° 2 ? ? N ? from both adjacent projections, with the direction of the scanning of the adjacent k-space scanning modules alternating.

Abstract: There is disclosed an NMR measurement method and NMR apparatus in which the temperature of the NMR detection coil or the RF irradiation coil hardly varies if pulsed RF power is applied to the coil during NMR measurements. The apparatus includes the detection coil or the RF irradiation coil, a first RF power application means for applying RF power of a frequency necessary for measurement of NMR signals, a second RF power application means for applying RF power of a frequency not affecting the measurement of NMR signals, and a control means for controlling the two power application means such that the sum of the RF power applied to the coil from the first application means and the RF power applied to the coil from the second application means is kept almost constant.

Abstract: A phased array coil for a Magnetic Resonance Imaging (MRI) system is provided that includes a first coil and a second coil adjacent the first coil. The first and second coils are configured in a shifted arrangement from a center of examination of the MRI system.

Abstract: A magnetic resonance imaging apparatus and the magnet apparatus thereof comprise plural pairs of magnetic field generation sources, arranged face to face with each other, for forming a magnetic field space 3; and magnetic field homogeneity adjusting apparatuses 17 and 18 for providing homogeneity adjustment of the magnetic field formed in the magnetic field space 3. The magnetic field homogeneity adjusting apparatuses 17 and 18 contain a plurality of tapped holes 24 for installing a magnetic field homogeneity adjusting member 26 of smaller volume in a plate-formed tray made of a non-magnetic substance; and a plurality of mounts 25 for installing the magnetic field homogeneity adjusting member 27 of greater volume, these mounts being formed over the area containing a plurality of through-holes for permitting installation of a magnetic field homogeneity adjusting member 26 of smaller volume, whereby major magnetic field adjusting work can be performed independently of minor magnetic field adjusting work.

Abstract: A novel mechanism for performing high accuracy cable diagnostics. The mechanism utilizes time domain reflectometry (TDR) to detect and identify cable faults, perform estimations of cable length, identify cable topology, identify load and irregular impedance on metallic paired cable, such as twisted pair and coaxial cables. The TDR mechanism transmits pulses whose shapes are programmable and analyzes the signal reflections. The shapes of the pulses transmitted can be optimized in accordance with the channel characteristics. Further, the TDR mechanism is adapted to operative in the presence of high pass filters in the channel.

Abstract: An apparatus for diagnosing motor damping network integrity, the motor damping network configured for selective short-circuiting of the windings of a motor in a motor control system. The apparatus includes a motor controller with a motor drive portion thereof electrically isolated from the windings of the motor. A resonant network is based on the windings of the motor, the damping network, and a remaining non-isolated portion of the controller. An amplifier circuit applies an excitation signal to the resonant network. A detector circuit detects a response of the resonant network based on the excitation signal. A state of the damping network is determined based on the response.

Abstract: A capacitance detection apparatus includes a detection electrode for detecting approach of an object on the basis of a change of capacitance, a calculating circuit for calculating a value associated with the capacitance change, a judging circuit for judging whether the calculated value is a normal or initial value calculated after or before a predetermined period of time lapse from a start time of the capacitance detection apparatus, an initial reference value-determining circuit for determining an initial reference value, a difference calculating circuit for calculating a difference between the normal value and a value calculated earlier than a time when the normal value is calculated by the predetermined period of time or longer or between the initial value and the initial reference value, and a determining circuit for determining whether the object is approaching by comparing the difference with a predetermined threshold value.

Abstract: Corrosion measurement devices are described with electrical isolation and intrinsic safety barriers advanced corrosion measurement in a field transmitter for online corrosion monitoring or off-line corrosion data logging.

Abstract: An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure Analysis. An iterative method is described for identifying and localizing fault sites on the circuit.

Abstract: A probe card of a wafer test system includes one or more programmable ICs, such as FPGAs, to provide routing from individual test signal channels to one of multiple probes. The programmable ICs can be placed on a base PCB of the probe card, or on a daughtercard attached to the probe card. With programmability, the PCB can be used to switch limited test system channels away from unused probes. Programmability further enables a single probe card to more effectively test devices having the same pad array, but having different pin-outs for different device options. Reprogrammability also allows test engineers to re-program as they are debugging a test program.

Abstract: The present invention relates to A microfabricated tip and post structure comprising a post having a rough top surface that diffuses incident light and a cross-section, and a tip, lithographically plated on the rough top surface of the post, having a smooth reflective surface appropriate for automatic vision recognition, and having a cross-section that is less than the cross-section of the post.

Abstract: An electronic device workpiece processing apparatus and method of communicating signals within an electronic device workpiece processing apparatus are provided.

Abstract: A test head assembly can include a probe card, which can include first contact areas. The test head assembly can also include a contactor, which can include second contact areas. An interposer can include first spring contact structures and second spring contact structures. The first spring contact structures can contact one of the first contact areas, and the second spring contact structures can contact one of the second contact areas. Ones of the first spring contact structures can be electrically connected through the interposer to ones of the second spring contact structures. One of the first spring contact structures can include a pair of contacts, both of which can extend from a first surface of the interposer to contact one of the first contact areas. Alternatively or additionally, one of the second spring contact structures can include a pair of contacts, both of which can extend form a second surface of the interposer to contact one of the second contact areas.

Abstract: A POGO pin that can measure low frequency products as well as RF products and also have a long life span, and a test socket including the POGO pin are provided. The POGO pin includes a metal plunger formed of a conductive metal so as to electrically contact the semiconductor package, and a rubber contact pin connected with the metal plunger and formed of a conductive rubber so as to electrically contact the test board.

Abstract: A probe card provides signal paths between integrated circuit (IC) tester channels and probes accessing input and output pads of ICs to be tested. When a single tester channel is to access multiple (N) IC pads, the probe card provides a branching path linking the channel to each of the N IC input pads. Each branch of the test signal distribution path includes a resistor for isolating the IC input pad accessed via that branch from all other branches of the path so that a fault on that IC pad does not substantially affect the voltage of signals appearing on any other IC pad. When a single tester channel is to monitor output signals produced at N IC pads, the resistance in each branch of the signal path linking the pads of the tester channel is uniquely sized to that the voltage of the input signal supplied to the tester channel is a function of the combination of logic states of the signals produced at the N IC pads.

Abstract: A semiconductor device includes an ODT (on die termination) pin coupled to a tester that applies a tester termination control signal thereon. The semiconductor device also includes a measure path that transmits the tester termination control signal from the ODT pin to an ODT circuit during measurement of a parameter of the semiconductor device. The ODT pin and the measure path advantageously allow for control of the ODT circuit by the tester for more accurate parameter characterization.

Abstract: A system is provided for communicating with a device within a packaged semiconductor device through a shared external terminal thereof. As one example, the system provides for testing a memory within the package. In addition to the device and the shared external terminal, the system includes a command register that receives a plurality of command signals, and digital logic devices coupled between the external terminal and the command register. Each of the digital logic devices receives a different clock signal and outputs one of the command signals to the command register. The command signals are provided to the external terminal in a sequence that is coordinated with the clock signals so that each digital logic device buffers one of the command signals.

Abstract: A liquid crystal substrate inspection apparatus includes an inspection device for inspecting a liquid crystal substrate and a prober replacing device disposed adjacent to the inspection device. The prober replacing device has a conveying device for conveying a prober for inspecting a liquid crystal substrate. The inspection device and the prober replacing device are arranged next to each other, so that it is possible to shorten an inspection time of the liquid crystal substrate. The prober replacing device has the conveying device for automatically conveying the prober to the inspection device.

Abstract: An electro-optical device includes a first substrate that holds an electro-optical material, a first IC that is mounted on the first substrate and that has a plurality of first terminals, a plurality of second terminals formed on the first substrate to be connected to the first terminals, respectively, a plurality of wiring lines formed on the first substrate, first substrate crack diagnostic terminal pairs that are included in the plurality of the first terminals and that are used for diagnosing whether a crack occurs in the first substrate, second substrate crack diagnostic terminal pairs that are included in the plurality of second terminals and that are connected to the first substrate crack diagnostic terminal pairs, respectively, a substrate crack diagnostic conductive pattern that connects the second substrate crack diagnostic terminal pairs and that extends around an outer periphery of the first substrate, a substrate crack diagnostic unit provided in the first IC to diagnose whether the first substra

Abstract: Systems and methods are provided using common-mode-voltage bias circuitry to make common-mode-voltage adjustments to differential driver circuitry in integrated circuit differential communications links. Adjustable bias circuitry may be controlled using static and dynamic control signals. Dynamic control signals can be produced by core logic on a programmable logic device or other integrated circuit. Static control signals can be produced by programmable elements. Bias circuit adjustments made at one end of a differential link can be used to improve performance at either end of the link or can be used to improve power consumption or to balance power and performance considerations. The same integrated circuit design can be used in both AC-coupled and DC-coupled environments. The bias circuitry can be formed from an adjustable current source and adjustable resistor. The current source and adjustable resistors can be controlled by the same control signals.

Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Abstract: A semiconductor device includes a transmitter, a termination resistance adjusting section, a transmitter control section and a control signal generating section. The transmitter has two output terminals and operates based on a control current. The termination resistance adjusting section is connected with the output terminals of the transmitter and applies a termination resistance adjusted in response to a control signal to each of the output terminals of the transmitter. The transmitter control section supplies the control current to the transmitter in response the control signal. The control signal generating section compares a first voltage corresponding to an external resistance and a second voltage corresponding to an internal resistance whose precision is lower than that of the external resistance, and outputs the control signal to the termination resistance adjusting section and the transmitter control section based on the comparing result.

Abstract: The present invention provides circuitry for implementing a multiple data rate interface architectures for programmable logic devices. The programmable logic device of the invention includes a core and surrounding periphery. The core includes a plurality of logic elements arranged in an array. Some of the logic elements within the core include registers that are used as data registers for the multiple data rate interface.

Abstract: A circuit in an integrated circuit having an input terminal to be coupled to a resistor network for selecting one of multiple digital states in the integrated circuit includes a voltage decode circuit, a control circuit and a power-up control circuit. The first input terminal receives an input voltage having a voltage value associated with the multiple digital states. The voltage decode circuit receives the input voltage and generates a voltage decode signal indicative of the voltage value of the input voltage. The control circuit receives the voltage decode signal and generates an output control signal accordingly where the output control signal selects one of the multiple digital states. The power-up control circuit provides power to the resistor network, the voltage decode circuit and the control circuit for determining the selected digital state and disconnects power to those circuits after the selected digital state is determined.

Abstract: A DPLA (dynamic programmable logic array) uses an enable unit for each output line that provides OR-functionality, to eliminate a clock signal in the OR-plane. A clock signal is used only in the AND-plane for pre-charging the product term lines. Such a DPLA operates properly without a delay constraint between clock signals in both the AND-plane and the OR-plane for proper operation at higher frequencies.

Abstract: In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.

Abstract: Logic circuitry is powered by a partially rectified alternating current (ac) waveform. The waveform is partially rectified in the sense that it does not provide a clean, primarily dc power signal. Instead, it is possible to power logic circuitry with a waveform that includes a substantial ac component. The partially rectified ac waveform may be applied to logic circuitry incorporating thin film transistors based on amorphous or polycrystalline organic semiconductors, inorganic semiconductors or combinations of both.

Abstract: In a voltage-level shifter, an input line is configured to convey an input voltage to be shifted. A pair of transistors is coupled to and is configured to receive the input voltage from the input line. There is a first side and a second side, with each side comprising the following: a low-voltage transistor that is coupled to the pair of transistors, a medium-voltage transistor that is coupled to the low-voltage transistor, a high-voltage transistor that is coupled to the medium-voltage transistor, and an output line, which is coupled to the first and second sides, for providing an output voltage that is higher than the input voltage.

Abstract: A level shift circuit for shifting levels of a pair of binary input signals having a first voltage range to produce a pair of binary output signals having a second voltage range includes a first circuit to shift a level of a first one of the binary input signals thereby to produce a first signal having the second voltage range, a second circuit to shift a level of a second one of the binary input signals thereby to produce a second signal having the second voltage range, and a timing adjustment circuit to produce the binary output signals by adjusting a pulse width thereof in response to the first and second signals such that the pulse width is equal to a time interval from when one of the first and second circuits stops level shift operation to when another one of the first and second circuits stops level shift operation.

Abstract: In one embodiment, a circuit is provided that includes: a differential input receiver having a first input terminal and a second input terminal; a first programmable switch coupled to the first input terminal and coupled through a first resistor to a first voltage such that if the first programmable switch is closed, the first input terminal is pulled towards the first voltage; and a second programmable switch coupled to the second input terminal and coupled through a second resistor to a second voltage such that if the second programmable switch is closed, the second input terminal is pulled towards the second voltage, wherein the first and second programmable switches are programmed to be closed during a differential input mode of operation in which the differential input receiver processes differential input signals provided to the first and second input terminals.

Abstract: A data output circuit is composed of first and second differential MOS transistors, first and second cascade MOS transistors, first and second outputs, and first and second resistor elements. The first and second differential MOS transistors receive first and second input voltages on the gates, respectively, sources of the differential MOS transistors being commonly connected. The first cascade MOS transistor is connected between the first differential MOS transistor and the first output, and the second cascade MOS transistor is connected between the second differential MOS transistor and the second output, gates of the first and second cascade MOS transistors being commonly connected. The first transistor element is connected between a ground line and the commonly connected gates, and the second transistor element is connected between a power supply line and the commonly connected gates.

Abstract: A pre-driver circuit includes a first stage to generate a first pre-driver signal and a second stage to generate a second pre-driver signal. The first and second stages are to generate the first and second pre-driver signals to cross at a point which reduces rise-and-fall mismatch in differential signal outputs from a current-mode driver.

Abstract: A primarily domino logic block uses static buffers instead of clocked domino buffers to correct a phase skipping problem, while realizing the same logic function with less integrated circuit area, power consumption, and cost. The use of static buffers simplifies the clock network and clock tree synthesis. A domino logic circuit including at least one logic gate including a fast input and a slow input, and a static buffer inserted in series with the fast input of the logic gate. The falling time of the static buffer is set to be greater than a defined minimum falling time and less than a defined maximum falling time.