Abstract: A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line. The first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively. The first and second p-type MOS transistors share an active junction with each other in a first area. The first and second n-type MOS transistors are spaced from the first area in a direction of the section line and have independent active junctions.

Abstract: A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.

Abstract: A short pulse rejection circuit is disclosed. The circuit comprises a signal transition detecting circuit, a control signal generating circuit, a capacitor resetting and charging circuit, and a charge pulse detecting circuit. The signal transition detecting circuit is to output detecting pulses in response to any input pulse. The control signal generating circuit generates two control signals for capacitor charging and discharging in response to the detecting pulses. The capacitor resetting and charging circuit generates discharging and charging signals in response to two control signals. The charge pulse detecting circuit generates output enable pulse and outputting a short pulse rejected pulses in response to the charging signals and original input pulse.

Abstract: An apparatus and method for verifying glitch-free operation of a multiplexer are provided. The apparatus includes a circuit having a plurality of flip-flop elements that receive as inputs the plurality of clock signals that are inputs to the multiplexer, and a corresponding synchronized output signal of a decoder generated based on control inputs to the decoder. The synchronized output signals from the decoder are used as trigger signals to the plurality of flip-flops. The flip-flops sample the clock signals based upon the trigger signals and provide outputs to a logic gate. The logic gate operates on the outputs from the flip-flops to generate an output signal indicative of whether glitch-free operation is verified or is not verified.

Abstract: An output stage circuit may include a sourcing driver device, a nonlinear local feedback loop having a feedback transistor and a first current mirror, a sinking driver device, and an output signal. The output stage circuit may actively and dynamically adjust the transconductance of the sourcing driver device by sensing its region of operation, and by sending a nonlinear feedback signal through the local feedback loop and the first current mirror. The nonlinear local feedback loop may be used for control and headroom compensation of the sourcing driver transistor to provide low distortion operation using a smaller size driver transistor.

Abstract: A semiconductor device controller includes a current supply control unit for controlling a conduction state of a semiconductor device connected to a load in response to a control signal to supply current to the load, a current level judging unit for comparing one or more switching judgment values set in an area smaller than an overcurrent judgment value with current detected by a current detecting unit to carry out a current level judgment and a time constant changing unit for changing the circuit time constant of the input signal processing circuit in accordance with a judgment result by the current level judging unit.

Abstract: When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signal is inputted to input terminals and an output is matched with a frequency as high as that of the original frequency in a Gillbert cell double-balanced mixer, so that a doubled output is obtained with no DC offset. According to the circuit configuration of the present invention, it is possible to provide a circuit readily performing integration and to efficiently output only a double frequency merely by inputting a simple differential signal without the need for the original signal which has been phase controlled. Further, a DC short circuit in the resonance circuit makes it possible to eliminate a DC offset voltage in an output.

Abstract: An amplifier/driver (40) for a bus has an output transistor (M1) that is controlled by a controlled current source (I1). In a quiescent state, the output transistor is configured as part of a current mirror (M1, M11) that maintains a gate-source voltage on the output transistor above the threshold voltage of the output transistor, thereby providing a fast turnon turn-on time. In an active state, the controlled current source provides a substantially constant current to the output transistor to achieve a controlled slew-rate, then reduces the current to the output transistor when a desired output voltage level is achieved. To improve power efficiency, a second controlled current source (I2) provides current to the output load when the desired output voltage level is achieved. To minimize transients, a class-AB control circuit (710) provides a minimum bias current to the output transistor, to prevent it from turning off when the desired output voltage level is achieved.

Abstract: A starter circuit includes a start detection circuit for detecting a change of an input signal and outputting a start digital signal, a digital OR circuit for outputting a determination digital signal based on the start digital signal, a power supply circuit being activated based on the determination digital signal, and a digital control circuit being operated based on a power from the power supply circuit. The digital control circuit inputs a retention signal to the digital OR circuit for maintaining an operation of the power supply circuit and a reset signal to the start detection circuit for resetting the start detection circuit.

Abstract: Clock regulation apparatus for preventing a logic switching mechanism from operating incorrectly. The apparatus has a supply voltage input that receives a supply voltage, which is also applied to the logic switching mechanism, a comparison unit that outputs an error signal if the supply voltage value drops below a reference value, a clock signal input that receives a clock signal from a clock generator, and a clock suppression unit, which is coupled to the clock signal input and to the comparison unit, that has a clock output for outputting the clock signal and that suppresses or delays the clock signal for a duration of at least one clock period if the error signal exists.

Abstract: A clock selection circuit and method may operate to generate a clock signal for a digital processing system. In the clock selection circuit, first and second clock control signals may be generated based on a received control signal and/or the inverse of a received clock signal. A first clock signal may be selected when the first clock control signal is activated, and may be output as the selected clock signal. A second clock signal may be selected when the second clock control signal is activated, and may be output as the selected clock signal. The selection operation of the clock selection circuit may reduce the likelihood that a glitch occurs and/or may reduce the amount of power consumed when compared to a conventional clock selection circuit.

Abstract: An offset correcting circuit includes: an amplifying unit including an offset adjusting unit that adjusts an offset of the amplifying unit; and an offset determining unit that outputs a signal to detect and corrects the offset of the amplifying unit. The offset determining unit includes a comparing unit that compares an output of the amplifying unit with a reference value, and a counter that increases or decreases a count value in response to an output of the comparing unit. The offset adjusting unit adjusts the offset based on the count value.

Abstract: Provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section A and a reference potential section GND. Further provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line B arranged in parallel to the signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section B and a reference potential section GND.

Abstract: A voltage clamping circuit comprises a first high current gain circuit adapted to receive current from the first line; and a first switching circuit that turns on the first high current gain circuit to flow current away from the first line when the first switching circuit senses a first voltage from the first line above a clamping voltage, and turns off the first high current gain circuit when the first switching circuit senses the first voltage below the clamping voltage.

Abstract: A level shifter apparatus and method for minimizing duty cycle distortion are provided. The level shifter includes a bank of comparators each having an associated threshold built into it. The comparators compare a difference in source voltages for two power domains to these built-in thresholds and output a signal indicative of whether the threshold is exceeded. The output signals from the comparators are provided to a thermometric decoder which generates control signals based on these output signals. The control signals are used to control stages in a level shifter for modifying the voltage output of the level shifter. Individual stages may be enabled to thereby monotonically modify the voltage output of the level shifter and thereby decrease a time required to achieve a voltage having a level that causes a state change in a driven circuit. As a result, duty cycle distortion is minimized and maximum operational frequency is increased.

Abstract: A method of power consumption reduction in integrated circuits comprising extensive use of differential signaling within said circuits. Differential signaling comprises a pair of coupled, symmetrically opposite and operatively dependent electronic signals each driven by voltages of the same magnitude, but of opposite polarity with respect to a common ground. The drive voltages of each signal are of relatively low potential as compared to the core operating voltage of present day devices. The low-voltage pair of signals tends to create offsetting fields of electromagnetic interference from the flow of current within their respective conductors which tends to minimize inductive effects (and therefore corruption of signals) in adjacent signal lines. Differential signaling replaces all or as many single-end signals as possible throughout the device resulting in relatively lower power usage as compared to present devices.

Abstract: A switching circuit (20) comprising first and second switch terminals (2,3) and a switch (21). The switch (21) comprises a first bipolar transistor (22), having a collector connected to the first switch terminal (2) and an emitter connected to the second switch terminal (3), and a second bipolar transistor (23), having an emitter connected to the first switch terminal (2) and a collector connected to the second switch terminal (3). The switch (21) can be turned on by supply of a control current to the base of either the first or the second bipolar transistor.

Abstract: A semiconductor switch includes first and second normally off type FETs Q1, Q2 and a normally on type FET Q3 connected between the first normally off type FET Q1 and the second normally off type FET Q2. Further, in the semiconductor switch, the normally on type FET Q3 is connected between the first and second normally off type FETs Q1, Q2 in series.

Abstract: An apparatus for receiving a first supply voltage in order to generate an internal voltage includes a control signal generating block for receiving a control enable signal and a clock signal and generating a pumping control signal having a period determined by one of the control enable signal and the clock signal in response to a test mode signal; and a charge pumping block for converting the first supply voltage into the internal voltage in response to the pumping control signal.

Abstract: This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

Abstract: An analog filter circuit in which filter characteristic deviation can be adjusted with simple circuitry and its adjustment method can be provided. The analog filter circuit includes a low pass filter and a high pass filter and output signals of both filters are input to a comparison and adjustment section from which an adjustment signal is fed back to the low pass and high pass filters and also input to a predetermined-band pass filter having predetermined correlation to the low pass and high pass filters. The low pass and high pass filters are tuned so that the frequency-gain characteristic line in an attenuation band of the low pass filter linearly falls, while that line of the high pass filter linearly rises, both the lines crossing at a reference frequency.

Abstract: A gain-controlled transimpedance amplifier circuit that comprises a first gain unit including an input for receiving a first current and an output, a current source for providing a second current, a second gain unit including an input and an output, a first impedance unit of a first impedance coupled in parallel with the second gain unit, and a comparator including an output, a first input coupled to the output of the first gain unit, and a second input coupled to the output of the second gain unit.

Abstract: A bypass circuit is disclosed for use with lower power supply voltage PC cards. The bypass circuit controls the power supply voltage fed to a power amplifier when switching between a lower power 8-PSK modulation mode and a higher power GMSK modulation mode. A step-up DC/DC converter provides a higher voltage to the power amplifier than can be supplied by an original power supply. Switch control logic controls a step-up switch and a battery switch. The step-up switch is turned on when operating in an 8-PSK modulation mode to provide a higher voltage to the power amplifier than the original power supply voltage. The battery switch is turned on when operating in the GMSK modulation mode to provide the original power supply voltage to the power amplifier.

Abstract: A linear amplifier circuit comprising a first differential amplifier (DA1) having a differential input terminals (I+, I?) for receiving a binary input signal, and a differential output terminals (O+,O?), a second differential amplifier (DA2) having input terminals coupled to the differential input terminals (I+, I?). The amplifier further comprises, a third differential amplifier (DA3) coupled in cascade to the second differential amplifier (DA2) and having its output cross-coupled to the differential output terminals in a feedforward connection, and a capacitor (C) coupled to the third differential amplifier (DA3) for determining an increase of a bandwidth of the linear amplifier, a current flowing through the capacitor (C) being proportional with a derivative of the differential input signal (I+, I?).

Abstract: A high frequency amplifier circuit has a bias supplying transistor for supplying a bias current to an amplifying transistor, and first and second temperature compensating transistors for compensating the temperature properties of the base voltage of the bias supplying transistor. The base of the bias supplying transistor and the base of the first temperature compensating transistor are connected by a resistor in order to keep the base voltage of the bias supplying transistor approximately constant without following a change in the base voltage of the first temperature compensating transistor, even in the case where such a change occurs. The temperature compensating transistors, the bias supplying transistor and the resistor are formed in one multi-emitter type transistor.

Abstract: A method of processing an electromagnetic wave comprises regulating at least two independently controllable current sources with a signal determined from at least one characteristic of the electromagnetic wave to generate a processed electromagnetic wave from at least one of the independently controllable current sources.

Abstract: A high frequency power amplifier electronic component (RF power module) is so constituted as to apply bias to an amplifier FET in current mirror configuration. In this RF power module, deviation of a bias point due to the short channel effect of the FET is corrected, and variation in high frequency power amplifier characteristics reduced. The high frequency power amplifier circuit (RF power module) is so constituted that the bias voltage for the amplifier transistor in a high frequency power amplifier circuit is supplied from a bias transistor connected with the amplifier transistor in current mirror configuration. In addition to a pad (external terminal) connected with the control terminal of the amplifier transistor, a second pad is provided which is connected with the control terminal of the bias transistor connected with the amplifier transistor in current mirror configuration.

Abstract: In response to a change in a circuit parameter of a converter delivering power to a load, the converter is operated in a mode in which additional power is supplied to the load by a capacitive element that is in parallel with the converter, the circuit parameter including a parameter other than input current.

Abstract: The present invention discloses a bandpass amplifier having gain and bandpass performance. The bandpass amplifier includes an input match unit for matching the gain of the amplifier and having a first filter response; a first bias unit electrically connected to the input match unit for driving the first terminal of the amplifier and having a first high pass filter response; a gain stage electrically connected to the first bias unit for providing the flat gain of the amplifier; a second bias unit electrically connected to the gain stage for driving the second terminal of the amplifier and having a second high pass filter response; and an output match unit electrically connected to the second bias unit for matching the gain of the amplifier and having a second filter response.

Abstract: The present invention relates generally to amplifiers, and more specifically to multi-band and/or multi-standard low noise amplifiers. There are currently no inexpensive, highperformance, fully-integrable, multi-standard low noise amplifiers (LNAs) available. The invention provides a suitable LNA for a multi-band and/or multi-standard receiver in wireless and other applications.

Abstract: A light receiving amplification circuit according to the present invention includes: a light receiving element; an amplification circuit which amplifies a photoelectric current generated by the light receiving element and outputs from an amplification stage for external output and a plurality of amplification stages for feedback; an operating current source set in each of the amplification stages which supplies an operating current to the corresponding amplification stages; a gain selection switch set in the respective plurality of amplification stages for feedback, which interrupts the operating current between the corresponding amplification stage and the operating current source; and a gain resistor set in the respective plurality of amplification stages for feedback and connected between the operating current side of the corresponding gain selection switch and an input of the amplification circuit.

Abstract: Variable gain amplifiers offering high frequency response with improved linearity and reduced power dissipation are provided. An amplifier is disclosed that is constructed from a one-stage topology with multiple signal paths and compensation networks for improved linearity and stable operation. In this amplifier, improved performance is obtained by replacing single transistor components with enhanced active devices which incorporate local negative feedback. One embodiment of the invention is a transconductance enhancement circuit that improves transconductance and input impedance relative to the prior art. A further development is an enhanced active cascode circuit that provides improved linearity. A high frequency bipolar transistor switch is also disclosed that incorporates lateral PNP transistors as high frequency switches with improved OFF-state to ON-state impedance ratio to realize a variable gain function.

Abstract: A silicon bipolar VCO implementing a double-coupled transformer is disclosed. The VCO circuit, which is suitable in the field of integrated RF circuits, has been integrated into a universal LNB having a down-converter block and PLL merged into a single die and implemented in silicon bipolar technology. The integrated transformer is formed by three turns of stacked metal layers, where the topmost metal layer is employed for the resonator inductance. The VCO is missing conventional biasing resistors and decoupling capacitors, thus improving phase noise and tuning range performance.

Abstract: A PLL circuit provides a self-selecting divide ratio, which is varied as necessary to lock the circuit to a reference clock which may have several possible frequencies, thereby enabling the VCO to employ a type of oscillator having a superior jitter characteristic. The PLL circuit includes a variable divider which divides the VCO output by a divide ratio value provided by a frequency band select circuit, which provides the divide ratio needed to drive the phase difference between the reference and divided clocks toward zero while the VCO clock output operates within a predetermined frequency range. The self-selecting variable divide ratio allows the VCO's oscillator to have a narrow output frequency range, thereby allowing the use of an oscillator type with a jitter characteristic which may be low enough to meet the requirements of JEDEC, for example.

Abstract: Couplers are disclosed that include first and second mutually coupled conductors. The coupled conductors may be regular or irregular in configuration, and for example, may be linear, including rectilinear or with one or more curves, bends or turns, such as forming a ring, coil, spiral or other loop. One or more sections of a coupler may be on different levels and separated by a dielectric medium, such as air or a dielectric substrate. Coupled conductors may be facing each other on the same or spaced-apart dielectric surfaces, such as opposing surfaces of a common substrate, and each conductor may include one or more portions on each side or surface of a substrate. In some examples, a coupler may include plural coupled sections, with conductors in one section being only broadside coupled, and conductors in another section being edge-coupled.

Abstract: A surface acoustic wave element 1 includes a substrate 2, an intermediate layer and a piezoelectric layer 4 laminated on the substrate 2, an IDT 5 disposed on the piezoelectric layer 4, a pair of reflectors 6 and 7 arranged on both sides of the IDT 5, and a protective layer 8 provided so as to cover the IDT 5 and the reflectors 6 and 7. The IDT 5, that is each of the electrode 5a and 5b, has a plurality of electrode fingers 51 juxtaposed with a prescribed spacing and the reflectors 6 and 7 have respectively a plurality of reflecting bodies 61 and 71. Further, the pitch Pr of the reflecting body of each reflector 6 and 7 is set to be smaller than the pitch Pt of the electrode finger of the IDT 5 and the ratio Pr/Pt is preferably set to be in the range of 0.7 to 0.9995. According to the surface acoustic wave element 1, the impedance characteristic and the insertion loss can be improved. Furthermore, electronic equipment having such surface acoustic wave element is provided.

Abstract: One pair of resonant electrodes is formed in a loop shape or a spiral shape in a substrate stacking direction symmetrically to each other. This allows a longitudinal space in substrate to be reduced. A first capacitor having an electrode connected to the grounding conductor layer, an electrode connected to an open-end side of the resonant electrode, and a dielectric layer is provided. A second capacitor having an electrode connected to the grounding conductor layer, an electrode connected to an open-end side of the resonant electrode, and a dielectric layer is also provided. This results in having a desired characteristic even if a length of the resonant electrode is short.

Abstract: A plurality of one-quarter wavelength coplanar resonators 5a to 5d are formed in series on a dielectric substrate 1, and coplanar input/output terminal sections 4a and 4b are formed on the dielectric substrate at opposite ends of the series connection for coupling with resonators 5a and 5d, respectively. A center conductor line width w1 of each of the resonators 5a to 5d is equal to a center conductor line width wio of each of the input/output terminal section 4a and 4b, but a ground conductor spacing d1 of each of the resonators 5a to 5d is greater than a ground conductor spacing dio of each of input/output terminal section 4a and 4b. Maintaining the accuracy of design is facilitated and a reduction in the maximum current density in the resonator is enabled.

Abstract: This invention relates to high frequency electromagnetic circuits, in particular to those made on planar or quasi-planar substrates, where the circuit is patterned on a metallic or superconducting film on top of a dielectric in any of the configurations known to those skilled in the art (for instance micro-strip, strip-line, co-planar, parallel plate or slot-line configurations). A part of the circuit such as the characteristic strip or slot of said configurations is shaped in a novel space-filling geometry which allows a significant size reduction of the circuital component. Miniature transmission lines, capacitors, inductors, resistors, filters and oscillators can be manufactured this way.

Abstract: The invention relates to a liquid-cooled choke comprising a choke core (1), a choke coil (2) and a path (3) for a cooling liquid to cool the choke. The choke core (1) is divided into at least two parts (1a, 1b) arranged in a cooling profile (4) to which the path (3) for the cooling liquid is arranged and which at the same time provides the choke with a frame and an assembly jig.

Abstract: A motor start relay (100) comprises a positive temperature PTC thermistor, a PTC case 400 of heat resistant resin for receiving the PTC thermistor horizontally, first and second contact/terminals (500, 560) each having contacts electrically engaged with a respective electrode surface of the PTC thermistor in the PTC case (400), a housing (200) receiving the PTC case (400) and a cover (300) attached on the housing (200). FIG. 9 shows the failsafe mechanism of the present invention. In case of a crack occurring in the PTC thermistor, thermistor portion PTC1 is rotated by spring contact (510) with a force F1, and thermistor portion PTC2 is pushed by spring contact (570) at the reverse direction and is dropped through an opening of the PTC case (400).

Abstract: The saw table guide bar has magnets thereon so that when it is inserted into the slot in an iron saw table it is urged to slide along the side of the slot. The magnetic saw table guide bar is used to support various measuring devices and overcomes measuring difficulties resulting from table slots of varying width.

Abstract: When a request to unlock a door of one side portion of a vehicle is input, an ID request signal is transmitted from a first transmitting antenna provided in the one side portion, and an alarm signal is transmitted from a second transmitting antenna provided in the other side portion of the vehicle. A portable unit sends back a portable-unit signal in dependence on the ID request signal and alarm signal. When the portable unit receives the first signal and does not receive the second signal, a door-unlocking control part unlocks the door of the one side portion in dependence on the portable-unit signal received by a receiving antenna.

Abstract: The invention describes a method and a device for communicating a signal over a power line. One embodiment may comprise a length of MV power cable that comprises a center conductor substantially surrounded by an insulator. A first concentric conductor is disposed external to the insulator over a first portion of the cable. A second concentric conductor that may have a length related to the wavelength of one or more carry frequencies of the data signals is disposed external to the insulator over a second portion of the cable and external to the insulator. A first gap is formed where the cable is exposed between the first concentric conductor and a first end of the second concentric conductor. A transceiver for communicating data signals over the MV power cable may be coupled to the first end of the second concentric conductor.

Abstract: Systems and methods for haptic devices are described. One described method comprises receiving a first input signal from a first control node and generating an output signal configured to administer a haptic effect on a second control node that is based at least in part on the first input signal.

Abstract: An indicator is provided that utilizes a side-emitting light-emitting diode to indicate the state of a vehicle. An example vehicle indicator is an automobile turn indicator. Other embodiments and features further provide for a conventional light-emitting diode additionally mounted to the vehicle indicator. Certain embodiments provide a cover that protects the vehicle indicator from damage and influences the pattern and/or frequency of light emanating from the vehicle indicator. Yet other embodiments provide a circuit board for converting power from the vehicle's power source to the particular power requirements, a timing mechanism for controlling illumination, and a heat dissipating apparatus for controlling the temperature of the side-emitting light-emitting diode. Still other embodiments provide an indicator that directs light toward the vehicle operator.

Abstract: A system and method is described for alerting authorities during a vehicle carjacking or carnapping. The method includes a first step of providing a vehicular radiotelephone communication system with speech recognition and a controller operable to monitor at least one vehicular system. A next step includes defining at least one predetermined sequence of operation of the at least one vehicular system for triggering a silent alert. The sequence can include spoken words or vehicle control operation. A next step includes monitoring the at least one vehicular system for the defined at least one predetermined sequence, such as a hidden switch activation for example. A next step includes activating a silent alert upon detection of the at least one predetermined sequence.

Abstract: The invention concerns a vehicle with a window pane, especially a front window, a rear window, a side window or a roof window, for covering of the internal space of the vehicle. The transparency of the window pane is adjustable, and the vehicle includes a control for automatic adjustment of the transparency of the window pane as a function of an operating state of the vehicle.

Abstract: A method for allocating wheels of a motor vehicle to a respective vehicle axle, each of the wheels includes an inflation tire whose tire pressure is monitored by a tire pressure monitoring device including at least one transmitting module in each wheel, and at least one receiving module arranged at or in the vehicle and one evaluation module, with each transmitting module transmitting tire pressure information and a wheel-specific identification number to the receiving module, which are sent to an evaluation process in the evaluation module, and tire pressure changes of the wheels are considered for the allocation, with the wheels having almost identical tire pressure changes being allocated to one vehicle axle by taking into account a vehicle-specific axle load.

Abstract: A safety system for use with a vehicle. The camera is capable of wirelessly transmitting signals to the display device. The camera can be specially mounted onto the rear of the vehicle. The display device may be mounted in the interior of the vehicle. The camera and display device may be automatically activated when the vehicle is place in reverse.