Abstract: Techniques are disclosed to regulate an output of a power converter. One example power converter includes an energy transfer element coupled between an input and an output of the power converter. A switch included in the power converter is coupled to the input of the energy transfer element. The power converter also includes a controller circuit coupled to the switch. The controller circuit is also coupled to receive a feedback signal representative of the output of the power converter and coupled to receive a signal representative of the power converter input voltage. The controller circuit is coupled to control switching of the switch to provide a regulated output parameter at the output of the power converter in response to the feedback signal. The controller circuit is coupled to latch the power converter into an off state in response to a detection of a loss of regulation of a power converter output parameter if the power converter input voltage is above a threshold level.

Abstract: A power supply system and corresponding methodology is provided for providing a self-protected power supply for use with electronic electricity meters. The self-protecting features are provided, in part, through the use of surface mounted resistive components corresponding to a resistor dropper portion of the power supply. The use of surface mount components also provides a general reduction in circuit board surface area requirements thereby providing a compact overall construction and provides economies with respect to reduction in manufacturing process steps. When the surface mount resistor divider is configured along with a half-wave rectifier, a low voltage DC supply is obtained from a direct connection to a much higher voltage AC mains source without requiring the use of coupling capacitors or transformers. Plural output voltages may be provided and capacitive filtering may be associated with the outputs.

Abstract: A digital PID controller for controlling the operation of a switching power converter is disclosed. A data converter is provided for converting the analog sense voltage to a digital sense voltage. A difference circuit then determines the difference between the digital sense voltage and a reference voltage as a digital error voltage, which reference voltage represents a desired output DC voltage for the power converter. A digital compensator processes the digital error voltage. The digital compensator includes a PID compensation network for compensating the digital error signal with a discrete time PID control law and a postprocessing filter for processing the output of the PID compensation network, comprised of a sinc filter with variable parameters to define the operating characteristics thereof, such that a first notch associated therewith can be placed at a desired frequency.

Abstract: In a semiconductor integrated circuit device in which a rectifier device constituting a rectifier comprises a MOS transistor whose gate is connected to one antenna terminal and whose source is connected to the other antenna terminal, the parasitic capacitance applied between the antenna terminals increased. The present invention provides a technology for connecting a first MOS transistor whose gate is connected to a second input terminal between a first input terminal and a first output terminal, allowing an output terminal of a first bulk terminal control circuit, which is connected between the first and second input terminals, to control a bulk terminal of the first MOS transistor, and allowing an output terminal of a second bulk terminal control circuit, which is connected between the first and second input terminals, to control a bulk terminal of a second MOS transistor, which is connected between the second input terminal and the first output terminal.

Abstract: A synchronous rectification circuit of a switching power supply device where circuit elements such as rectification switch elements are protected when an abnormality occurs in an output of a transformer, wherein a (fault) detecting circuit detects an abnormality of a trigger signal transmitted from a transformer, a shutoff circuit quickly cuts off a discharge route of an inductor (coil) forming a gate drive signal source of a first transistor (NMOS transistor) when the (fault) detecting circuit detects an abnormality, and a (linear) driver holds (clamps) a drain-source voltage of the NMOS transistor at a constant voltage and turns on the NMOS transistor by that constant voltage so as to prevent it from turning off immediately when the detecting circuit detects an abnormality.

Abstract: The proposed power converter system includes: a main body component having a case, an input terminal, a power converter circuit electrically connected to the input terminal, a plurality of resistors electrically connected to the power converter circuit, and a first connecting port electrically connected to each of the resistors, and a plurality of adaptor units each having an adaptor. Each of the adaptors is employed to let the power converter circuit generate a specific output voltage value and includes: an input connecting port coupled to the first connecting port to let each of the resistors become one of the grounded state, the open-circuited state, and the coupled to the output voltage state, and an output port coupled to the input connecting port for outputting the output voltage.

Abstract: A required value of decoupling capacitance is calculated in advance for every functional cell, a virtual cell which has a functional cell, and a decoupling capacitance placing area required for placing the decoupling capacitance with the calculated value is created, the virtual cell is placed on a chip, and the decoupling capacitance cell is subsequently placed in the decoupling capacitance placing area of the virtual cell. A layout method of an integrated circuit and a computer program, in which a decoupling capacitance with an amount required for preventing malfunction caused by a noise can be surely placed, and there is no possibility that the functional cell will need to be replaced due to a shortage of the decoupling capacitance after placing the functional cell can be realized.

Abstract: Four memory cells each obtained by connecting a ferroelectric capacitor in parallel to a transistor are connected in series with each other to constitute a cell block. A sense amplifier circuit is arranged on a one-end side in a column direction every four cell blocks sequentially adjacent to each other in a row direction. One ends of the four cell blocks are connected to four different plate lines, respectively, and the other ends of the four cell blocks are connected to four different bit lines through four block selection transistors, respectively. Of the four bit lines, two bit lines constitute a first bit line pair, and the two remaining bit lines constitute a second bit line pair. Any one of the first and second bit line pairs is connected to the sense amplifier circuit and the other bit line pair is connected at a constant voltage.

Abstract: A ferroelectric memory includes a memory cell array having a plurality of memory cells with ferroelectric capacitors arranged therein, a plurality of word lines, a plurality of plate lines, and a plurality of plate line selection circuits. An L-th plate line selection circuit among the plurality of plate line selection circuits includes a first transistor that is provided between an L-th plate line and a supply node for supplying an I-th plate line selection signal and turns on when a K-th word line is set to a selection voltage to thereby supply the I-th plate line selection signal to the L-th plate line, and a second transistor that is provided between the L-th plate line and a first power supply and turns on when the K-th word line is set to a non-selection voltage to thereby set the L-th plate line to a voltage level of the first power supply.

Abstract: A programmable capacitor array does not require separate switching transistors because the capacitors themselves have a switchable capacitance, which capacitors are made in the manner of regular N channel transistors with their source/drains connected to each other. When a logic low is applied to the gate, the capacitance is relatively low and the capacitance is what is commonly called parasitic capacitance. The capacitance increases significantly when a logic high is applied to the gate because the logic high has the effect of inverting the channel. Thus, the capacitor array is made of transistors that themselves have switchable capacitance operated so that no separate switching transistors are required. This allows for construction of an array of unit capacitors to achieve monotonic operation and good linearity using conventional manufacturing of N channel transistors while achieving significant area savings and reduced power consumption.

Abstract: A random access memory cell includes first and second nanotube switching elements and an electronic memory with cross-coupled first and second inverters. Each nanotube switching element includes a nanotube channel element having at least one electrically conductive nanotube, and a set electrode and a release electrode disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between a channel electrode and an output node. Input nodes of the first and second inverters are coupled to the set electrodes and the output nodes of the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or in a shadow memory or store mode to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode to transfer the state of the nanotube switching elements to the electronic memory.

Abstract: The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed.

Abstract: The magnetic memory device comprises: a memory cell including two magnetoresistive effect elements serially connected to each other, and a select transistor connected to a connection node between the two magnetic resistant devices, a bit line connected to the connection node of the magnetoresistive effect elements via the select transistor, and a read circuit for reading information memorized in the magnetoresistive effect elements, based on a voltage of the connection node outputted to the bit line.

Abstract: Roughly described, a magnetic structure includes an electrically conductive path for carrying current flow, a soft magnetic material with high permeability value in magnetic communication with the current flow so that it can be magnetized in either of two directions, and a magnetic device such as a magnetic random access memory cell, having an active layer that is quantum mechanically or magnetostatically coupled to the soft magnetic material. The soft magnetic material acts as an intermediary between the magnetic induction of the current flow and the magnetization of the active layer of the magnetic device to reduce the writing current.

Abstract: A magnetic memory device includes a first write wiring which runs in a first direction, a second write wiring which runs in a second direction different from the first direction, and a magnetoresistive element which is arranged at an intersection between the first and second write wirings, has a fixed layer, a recording layer, and a magnetoresistive layer sandwiched between the fixed layer and the recording layer, and has an axis of easy magnetization obliquely with respect to the first and second directions, the recording layer including a first ferromagnetic layer, a second ferromagnetic layer, and a first nonmagnetic layer sandwiched between the first and second ferromagnetic layers, in which first magnetization of the first ferromagnetic layer and second magnetization of the second ferromagnetic layer are ferromagnetically coupled, and a ferro-coupling constant C of a ferromagnetic coupling is 0.0001 erg/cm2?C?0.2 erg/cm2.

Abstract: In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, the second end is pulled down to zero or even a negative value. If the cell is storing a “1,” the voltage at the thyristor cathode can be approximately 0.6 volt at the time of the pull down. The large forward-bias across the diode pulls down the thryistor cathode. This causes the thyristor to be restored. If the cell is storing a “0,” the voltage at the thyristor cathode can be approximately zero volt. The small or zero forward-bias across the diode is unable to disturb the “0” state. As a result, the memory cell is restored to its original state.

Abstract: A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced by non-selected memory cells is detected by a leakage detecting circuit and compensated by a leakage current supply circuit.

Abstract: A non-volatile memory system (230) includes a magnetoresistive random access memory (MRAM) (232) including a plurality of magnetoresistive memory cells, a floating-gate nonvolatile memory (234) including a plurality of floating-gate memory cells, and a controller (236) coupled to the MRAM (232) and to the floating-gate nonvolatile memory (234). The controller (236) is adapted to be coupled to a system bus (220) and controls a selected one of the MRAM (232) and the floating-gate nonvolatile memory (234) in response to an access initiated from the system bus (220).

Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.

Abstract: An integrated circuit programmable resistor or programmable capacitor has a floating gate memory cell connected either in series or in parallel to a fixed resistor or a fixed capacitor. The resistance or the capacitance of the floating gate memory cell can be changed by the amount of charge stored on the floating gate which affects the resistance or the capacitance of the channel from which the floating gate is spaced apart. A particular application of the programmable resistor/capacitor is used in a system whereby the resistance or the capacitance can be change or fine tuned as a result of either drift caused by time or by operating conditions such as temperature. Thus, the temperature of the substrate in which the floating gate memory cell is fabricated can be monitored and the resistance or the capacitance of the floating gate memory cell changed dynamically.

Abstract: A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

Abstract: Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween.

Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

Abstract: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potential on the word lines and bit lines according to the input data. The control circuit further controls the operations of writing data into, reading data from, and erasing data from the memory cells. A data storage circuit is connected to the bit lines and stores data under the control of the control circuit. The data storage circuit and the memory cell array are formed in the same well region.

Abstract: A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer.

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a reference NVM transistor. During programming, the reference NVM transistor has a floating gate coupled to ground through a first set of capacitors, and coupled to a reference voltage through a second set of capacitors. The program threshold voltage of the first NVM transistor is dependent on the first and second sets of capacitors. The first and reference NVM transistors are then coupled in parallel, and a differential amplifier is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Capacitors can be transferred between the first set and the second set, thereby providing precise adjustment of the single ended reference voltage.

Abstract: A nonvolatile memory device and method of programming the device are disclosed. The nonvolatile memory device is adapted to interrupt or resume a programming operation for a memory cell of the device in response to variation in a programming voltage being supplied to the memory cell. The programming operation is typically interrupted or resumed in response to signals generated by a program controller and/or a detector monitoring the programming voltage.

Abstract: An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an auxiliary intermediate voltage that is coupled to a negative level shifting circuit to reduce the drain-source stress experienced by transistors in that circuit that are in an off state. The auxiliary voltage generation circuit also generates a logic control signal that indicates to a high voltage discharge path to perform either a slow discharge operation or a fast discharge operation.

Abstract: A semiconductor device includes a volatile memory and a controller which stores address conversion information in the volatile memory and execute an address converting process using the address conversion information, the address conversion information indicating some of all correspondences between addresses in a first semiconductor memory having a first erase block size and addresses in a second semiconductor memory having a second erase block size different from the first erase block size.

Abstract: A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during an operational mode of the memory device such as an active mode, a read mode, or a refresh mode.

Abstract: A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting a read or write command, the module register generates an active termination control signal to the memory. The memory turns on active termination based on information programmed into one or more mode registers of the memory. The memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

Abstract: A memory device having an open bit line cell structure uses a wafer burn-in testing scheme and a method for testing the same. The memory device includes a sense amplifier having first and second input terminals; a bit line connected to the first input terminal of the sense amplifier and extended in a first direction; an inverted bit line connected to the second input terminal of the sense amplifier and extended in a second direction; and a voltage supply means for applying the same voltage to the bit line and the inverted bit line in a precharge operation mode and applying a different level voltage to the bit line and the inverted bit line in a burn-in test operation mode. It is possible to efficiently screen defects of memory cells and between bit lines by performing a wafer burn-in test using a wafer burn-in scheme on a memory device having an open bit line cell structure.

Abstract: A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.

Abstract: An integrated semiconductor memory device includes a memory cell array with sense amplifiers that are combined in groups within the memory cell array. Each sense amplifier is associated with one data connection, the association varying on the basis of area within the memory cell array. When a memory cell is read, further adjacent memory cells besides the memory cell which is to be read are read, so that data are produced at all the data connections. To this end, the sense amplifiers in a group are activated together. To establish which sense amplifier within a group of sense amplifiers has a signaling connection to which data connection, individual sense amplifiers in a group can be deactivated specifically, which means that a data item which differs from an expected value appears at the data connection which is connected to the deactivated sense amplifier.

Abstract: A memory capable of performing a refresh operation without increasing current consumption is provided. This memory comprises a plurality of memory cells storing data, a delay circuit outputting a first address signal corresponding to the memory cells received from outside for a normal access operation with a delay of a prescribed period, a refresh control circuit outputting a second address signal corresponding to any of the memory cells subjected to a refresh operation of the data and a switching circuit switching and outputting the first address signal output from the delay circuit and the second address signal output from the refresh control circuit.

Abstract: An integrated circuit chip includes a number of memory bitcells. Each bitcell includes: a latch having a sense node; a programming transistor having an efficient saturation region of operation; and a fuse connected to the programming transistor at a first terminal of the fuse. A programming voltage can be supplied to the fuse at a second terminal of the fuse; and a logic gate circuit is connected to the gate of the programming transistor. The logic gate circuit is operated at the programming voltage so that the logic gate circuit drives the programming transistor in the efficient saturation region when programming the fuse. The bitcell also includes a fuse-sensing circuit having no more than one transistor. Operation in the efficient saturation region allows the programming transistor to be small. Combined with using no more than one sensing transistor, significant reduction in area of the bitcells on the chip is achieved.

Abstract: A nonvolatile memory cell operates without a time delay in an external power mode using an external power source. A power detector includes high voltage generators for generating voltages to a target level in response to a high voltage enable signal. A high voltage level detector detects attainment of the generated voltages to their respective target levels in response to an internal power mode signal generated in an internal power mode, and outputs a first detection signal. An external power mode detector outputs a second detection signal for an operation of the nonvolatile memory cell in response to an external power mode signal generated in an external power mode, and outputs the second detection signal in response to the first detection signal in the internal power mode.

Abstract: Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

Abstract: A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k?1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines.

Abstract: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

Abstract: A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.

Abstract: A memory device includes: a memory array for storing data; data pads for supplying as an output of the memory device data retrieved from the memory array in a read operation; parallel read data paths each coupled between the memory array and the data pads, where the parallel read data paths include synchronous data paths operable in different modes of operation and an asynchronous data path; and a mode selector for selecting one of the parallel read data paths to supply data retrieved from the memory array to the data pads.

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

Abstract: An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such a way that when a noisy clock signal is applied to the integrated semiconductor memory device, the less sensitive input amplifier is used for generating an internal clock signal. If, by contrast, a lower-noise clock signal is applied to the integrated semiconductor memory device, the control circuit drives the controllable switch in such a way that the more sensitive input amplifier is used for generating the internal clock signal. The changeover of the controllable switch is effected after evaluation of a bit sequence applied to a further input terminal of the integrated semiconductor memory device.

Abstract: An automatic ATD control circuit operates with a first delay circuit accepting a system clock pulse as an input and producing a delayed version of the system clock pulse as an output. The delay to the system clock is performed to allow a frequency comparison in a later part of the circuit. An edge detection circuit operates when the delayed system clock is received and senses an edge of the delayed system clock pulse. A pulse output from the edge detection circuit feeds into a second delay circuit; the second delay circuit produces an output pulse where a period of the pulse is determined by delay characteristics of the sense amplifier and is thus independent of system clock frequency. The pulse is compared to the system clock frequency. If the system clock frequency is above a determined frequency, the automatic ATD control circuit is disabled.

Abstract: A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on the embodiment, each write segment is made up of a single memory cell or a small number of cells (e.g., a byte). A count is encoded so that it is distributed across a number of fields, each associated with one of the write segments, such that as the count is incremented only a single field (or, in the single bit embodiments, occasionally more than one field) is changed and that these changes are evenly distributed across the fields. The changed field is then written to the corresponding segment, while the other write segments are unchanged. Consequently, the number of rewrites to a given write segment is decreased, and the lifetime correspondingly increased, by a factor corresponding to the number of write segments used.

Abstract: A sonar emits an ultrasonic wave into the water from a transducer on the basis of a transmission signal outputted from a transmission circuit, receives an echo reflected in the water with the transducer and converts the echo into an electric signal, and displays underwater information on a display unit on the basis of an echo signal extracted by processing the electric signal. A tailing signal removing unit for removing a tailing signal and extracting only the echo signal is provided in the sonar such that a video of a surface layer fish shoal is clearly displayed on a screen of the display unit without being hidden by a video of the tailing signal.

Abstract: Described is a system and method for detection using an ultrasonic wave. The system may include a first arrangement and a second arrangement. The first arrangement may include a transmitter and a receiver. The transmitter transmits an ultrasonic wave along a surface on which items are to be stored and the receiver receives the wave after it has passed over the surface. The second arrangement receives from the first arrangement data corresponding to properties of the received wave. The second arrangement compares the properties of the received wave to properties of the transmitted wave to generate current condition value. The second arrangement determines based on the current condition value and calibration data a current condition state corresponding to a degree of the surface currently occupied by the items. The calibration data includes at least one calibration value and a corresponding calibration condition state.

Abstract: Methods and apparatus determine if an underwater intruder passes under a protective boundary. A sonar sensor system comprises a plurality of sonar sensor modules that are spaced on a protective boundary. A sonar sensor module comprises a sonar transducer (sonar array) that is characterized by an omni-directional radiation pattern that may overlap an omni-directional radiation pattern of an adjacent sonar sensor module transducer. The sonar sensor module collects sonar data such as range information of the target in relation to time. A central processor obtains the sonar data from each sonar module through a telemetry link. The central processor processes the sonar data from the plurality of sonar sensor modules in order to determine an estimated path of the target and may determine if the target should be considered as a threatening underwater intruder from a calculated threat level estimate based on this data.