Abstract: An electronic lock utilizes two microprocessors remote from each other for enhanced security. The first microprocessor is disposed close to an input device such as a keypad, and the second microprocessor is disposed close to the lock mechanism and well protected from external access. The first microprocessor transmits a communication code to the second microprocessor when it receives via the input device an access code that matches a preset access code. The second microprocessor opens the lock if the transmitted communication code matches a preset communication code. The dual-microprocessor arrangement is advantageously used in a voice controlled access control system and in a motorcycle ignition control system. The present invention further provides an electronic access control system which has a master electronic key having a preset number of access, and an electronic alarm system for a bicycle that has a remote control mounted in the helmet of the rider.

Abstract: A three-dimensional multi-gate device has a silicon fin, a gate structure, and a stress-adjusting layer. The gate structure contacts with three surface of the silicon fin to form a three-dimensional gate structure. The stress-adjusting layer is disposed on the gate structure to provide stress along the direction parallel to the channel length of the gate structure. The stress helps promote the mobility of the charges in the channel region under the gate structure and improve the electrical performance such as drive current and DIBL of the three-dimensional multi-gate device.

Abstract: A field effect transistor includes a semiconductor layer structure including GaN channel layer 12 and AlGa electron supply layer 13, source electrode 1 and drain electrode 3 which are formed on electron supply layer 13 so as to be separated from each other, gate electrode 2 formed between source electrode 1 and drain electrode 3, and SiON film 23 formed on electron supply layer 13. Gate electrode 2 has a field plate portion 5 that projects toward drain electrode 3 in the form of an eave on SiON film 23. The thickness of a portion (field plate layer 23a) of SiON film 23 lying between field plate portion 5 and electron supply layer 13 gradually increases from gate electrode 2 to drain electrode 3.

Abstract: The protection element of the present invention is constructed of a MOS capacitor composed of a semiconductor substrate, an insulating film formed on the semiconductor substrate and a word line formed on the insulating film. A well region having a conductivity type opposite to that of the semiconductor substrate is formed in a portion of the semiconductor substrate constituting the MOS capacitor. If charge exceeding the breakdown voltage of the insulating film constituting the MOS capacitor is induced in the word line, the induced charge is released into either the semiconductor substrate or the well region depending on whether the induced charge is positive or negative.

Abstract: The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that exposes an outside area of the active area, which is outside of the central area where a gate electrode will be formed. A shallow grade layer is formed by implanting impurities into an opening with an energy that does not permit penetration of impurity ions through the gate insulation film.

Abstract: In order to realize high resolution and high picture quality of a solid-state imaging apparatus, a light-collecting device which is resistant to incident light incoming at a high-angle and a manufacturing method of the light-collecting device are provided. The light-collecting device includes light-transmitting films 101 which form concentric circles wherein, in each area divided by a constant width 103 of the divided area in an in-plane direction, a sum of line widths of a width 103 in the divided area is different each other. In each divided area, outer radius/inner radius of a light-transmitting film 101 may match outer radius/inner radius of the divided area. In each divided area, the sum of line widths is smaller than a sum of line widths in an adjacent inner divided area.

Abstract: A display substrate includes a base substrate, a first metal pattern, a gate insulating layer, a second metal pattern, a channel layer and a pixel electrode. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode of a switching element. The gate insulating layer is formed on the base substrate including the first metal pattern. The second metal pattern is formed on the gate insulating layer, and includes a source electrode, a drain electrode and a source line. The channel layer is formed under the second metal pattern, and is patterned to have substantially the same side surface as a side surface of the second metal pattern. The pixel electrode is electrically connected to the drain electrode. Therefore, an afterimage on a display panel, thus improving display quality.

Abstract: A thin film transistor (TFT) substrate is fabricated in three mask processes. In a first mask process, a gate line and a gate electrode are formed. In a second mask process, a data line, a source electrode, a drain electrode, a semiconductor layer, and a first upper storage electrode overlapping the gate line are formed from a gate insulating film, undoped and doped amorphous silicon layers, and a data metal layer. In a third mask process, a pixel hole is formed through protective and gate insulating films within and outside a pixel area, the first upper storage electrode is partially removed, a pixel electrode contacts a side of the drain electrode within the pixel hole at the pixel area, and a second upper storage electrode contacts a side of the first upper storage electrode in the pixel hole outside the pixel area.

Abstract: A shared-pixel-type image sensor includes a semiconductor substrate, four photoelectric conversion elements disposed adjacent to one another in one direction on the semiconductor substrate, two first transmission elements transmitting charges accumulated in two adjacent ones of the photoelectric conversion elements to a first floating diffusion region, respectively, two second transmission elements transmitting charges accumulated in the other two adjacent photoelectric conversion elements to a second floating diffusion region electrically coupled with the first floating diffusion region, respectively, MOS capacitors that are electrically coupled with the first or second floating diffusion region, a reset element resetting the charges of the first and second floating diffusion regions to a reference value, and a drive element and an select element outputting the charges of the first or second floating diffusion region.

Abstract: An integrated photosensitive device with a metal-insulator-semiconductor (MIS) photodiode constructed with one or more substantially continuous layers of semiconductor material and with a substantially continuous layer of dielectric material.

Abstract: A solid-state imaging device capable of reducing an eclipse (blocking) of an incident light at a circumferential portion of a light receiving portion and realizing a larger angle of view and high-speed driving. A single-layer transfer electrode configuration of forming first transfer electrodes and second transfer electrodes by one polysilicon layer is adopted. Two shunt wirings extending in a horizontal direction are formed on the first transfer electrodes connected in a horizontal direction and, for example, four-phase transfer pulses are supplied to first transfer electrodes and second transfer electrodes on transfer channels through low-resistance shunt wirings extending in the horizontal direction.

Abstract: The present invention, in the various exemplary embodiments, provides a RGB color filter array. The red, green and blue pixel cells are arranged in a honeycomb pattern. The honeycomb layout provides the space to vary the size of pixel cells of an individual color so that, for example, the photosensor of blue pixels can be made larger than that of the red or green pixels. In another aspect of the invention, depicted in the exemplary embodiments, the honeycomb structure can also be implemented with each pixel rowing having a same color of pixel cells which can simplify can conversion in the readout circuits. In another aspect of the invention, the RGB honeycomb pixel array may be implemented using a shared pixel cell architecture.

Abstract: A spin FET according to an example of the present invention includes a magnetic pinned layer whose magnetization direction is fixed, a magnetic free layer whose magnetization direction is changed, a channel between the magnetic pinned layer and the magnetic free layer, a gate electrode provided on the channel via a gate insulation layer, and a multiferroric layer which is provided on the magnetic free layer, and whose magnetization direction is changed by an electric field.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: Provided is a method of manufacturing a nano-sized MTJ cell in which a contact in the MTJ cell is formed without forming a contact hole. The method of forming the MTJ cell includes forming an MTJ layer on a substrate, forming an MTJ cell region by patterning the MTJ layer, sequentially depositing an insulating layer and a mask layer on the MTJ layer, exposing an upper surface of the MTJ cell region by etching the mask layer and the insulating layer at the same etching rate, and depositing a metal layer on the insulating layer and the MTJ layer.

Abstract: A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.

Abstract: A semiconductor memory device excellent in data holding characteristics even when a cell area is reduced is disclosed. According to one aspect of the present invention, a semiconductor memory device comprises a transistor including a source, a drain and a channel region disposed in a semiconductor substrate, and including a gate electrode disposed through a gate insulator on a surface of the semiconductor substrate of the channel region, a capacitor connected to the channel region, a first wiring line electrically connected to the gate electrode, and a second wiring line electrically connected to the drain.

Abstract: A nonvolatile semiconductor memory device includes floating gates, source areas, drain areas, word lines, diffusion layers, source lines and shield wires. The source area is shared by the floating gates adjacent to each other in a column direction. The drain area faces the source area in the column direction with the floating gate. The drain area is wider than the source area in the column direction. The diffusion layer is formed on an inner wall of a trench made between the source areas adjacent to each other in the same row direction and electrically connects the adjacent source areas together. The source line is formed of the source area and diffusion layer on the same row. The shield wire is disposed on and along the source line. A top surface of the shield wire is lower than that of the floating gate adjacent to the shield wire.

Abstract: A polysilicon film forming a memory gate interconnection and the like includes a part extending from a part positioned on one side surface of a control gate interconnection to a side opposite to a side where the control gate interconnection is positioned, and that part serves as a pad portion. A contact hole is formed to expose the pad portion. The height of a part of the polysilicon film that is positioned on one side surface of the control gate interconnection is set equal to or lower than the height of the control gate interconnection so that the polysilicon film forming a memory gate interconnection and the like does not two-dimensionally overlap the control gate interconnection. Therefore, a semiconductor memory device with increased process margin can be obtained.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Abstract: A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel

Abstract: An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate electrode. The first insulating film and the second insulating film are formed in separate steps, and the first insulating film is thicker than the second insulating film. With this structure, when an insulating film is provided between the floating gate electrode and a silicon substrate to have a thickness more increased at its end portion than at its middle portion, the thickness can be increased more freely and a degree of the increase can be controlled more readily.

Abstract: A semiconductor device is disclosed that includes a nonvolatile memory cell having a memory transistor and a selection transistor, and a peripheral circuit transistor. The memory transistor includes a memory gate oxide film that is arranged on a semiconductor substrate, and a floating gate made of polysilicon that is arranged on the memory gate oxide film. The selection transistor is serially connected to the memory transistor and includes a selection gate oxide film that is arranged on the semiconductor substrate, and a selection gate made of polysilicon that is arranged on the selection gate oxide film. The peripheral circuit transistor includes a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film. The memory gate oxide film is arranged to be thinner than the peripheral circuit gate oxide film.

Abstract: Non-volatile memory devices according to embodiments of the present invention include an EEPROM transistor in a first portion of a semiconductor substrate, an access transistor in a second portion of the semiconductor substrate and an erase transistor in a third portion of the semiconductor substrate. The second portion of the semiconductor substrate extends adjacent a first side of the first portion of the semiconductor substrate and the third portion of the semiconductor substrate extends adjacent a second side of the first portion of the semiconductor substrate. The first and second sides of the first portion of the semiconductor substrate may be opposite sides of the first portion of the semiconductor substrate. The access transistor has a first source/drain terminal electrically connected to a first source/drain terminal of the EEPROM transistor and the erase transistor has a first source/drain terminal electrically connected to a second source/drain terminal of the access transistor.

Abstract: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

Abstract: A circuit board includes a substrate and an insulating layer. The substrate has a first surface. The insulating layer has a second surface and is connected to the substrate. The first surface is in contact with the second surface. Heat-conductive particles are provided in the insulating layer. A part of the particles projects from the second surface of the insulating layer and is in contact with the first surface of the substrate.

Abstract: A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are formed through the use of a single mask. An in-process semiconductor device which may be formed using one embodiment of the inventive method is also described.

Abstract: A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

Abstract: A transistor structure, such as a Double-gated FET (DG FET), that has been modified to include a charge-trapping region used to store either 2- or 4-bits of information. The charge-trapping region can, for example, be embedded in the gate dielectric stack underneath each gate electrode, or placed on the sidewalls of each gate electrode.

Abstract: A semiconductor device of the present invention includes vertical double diffused MOS transistor. A gate electrode of the vertical double diffused MOS transistor is disposed within a trench formed on a semiconductor substrate and projects from a surface of the semiconductor substrate. On a side surface of the gate electrode, a side wall is formed. On the surface of the semiconductor substrate and a surface of the gate electrode, a metal silicide film is formed.

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Abstract: Disclosed are a semiconductor device of high breakdown voltage and a method manufacturing the same. According to the invention, it is possible to previously prevent an increase size of the device due to a separation of a high concentration impurity layer and a gate electrode pattern by embedding the gate electrode pattern in a bottom of a semiconductor substrate, and sequentially stacking a low concentration impurity layer and a high concentration impurity layer for source/drain diffusion layers on both sides of the gate electrode pattern, thereby allowing the high concentration impurity layer to easily secure a voltage drop areas necessary for itself without being spaced from the gate electrode pattern.

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Abstract: A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

Abstract: An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, and at least one trench electrode extending substantially vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is electrically connected to the trench electrode, and at least a second terminal is electrically connected to the active region. The gated diode is operative in one of at least a first mode and a second mode as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer substantially surrounding the trench electrode.

Abstract: A semiconductor device has a supporting substrate applied with a predetermined potential, an insulating layer formed on the supporting substrate, a semiconductor layer formed on the insulating layer, a FDSOI transistor formed on the semiconductor layer and including a source region, a drain region, and a channel region, the channel region being formed between the source region and the drain region, and a high-concentration impurity region formed in a vicinity of a surface of the supporting substrate at least just below the channel region, in which an average impurity concentration in the vicinity of the surface of the supporting substrate just below the channel region is not lower than an impurity concentration of the channel region.

Abstract: A semiconductor structure embodiment comprises a semiconductor membrane with local strained areas. The membrane with local strained areas is formed by a process including performing a local oxidation of silicon (LOCOS) process in a substrate and removing resulting oxide to form a recess in the substrate, and bonding a semiconductor membrane to the substrate to induce a strain where the membrane conforms to the recess in the substrate.

Abstract: A system and method for electrostatic discharge protection. The system includes a plurality of transistors. The plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The plurality of source regions and the plurality of drain regions are located within an active area in a substrate, and the active area is adjacent to at least an isolation region in the substrate. Additionally, the system includes a polysilicon region. The polysilicon region is separated from the substrate by a dielectric layer, and the polysilicon region intersects each of the plurality of gate regions. At least a part of the polysilicon region is on the active area.

Abstract: In a semiconductor circuit device including a first terminal adapted to receive a first voltage and a second terminal adapted to receive a second voltage lower than the first voltage, a capacitive circuit and a short-circuit preventing circuit are provided in series between the first and second terminals. In this case, when the capacitive element is in an insulating (non-conductive) state, the short-circuit preventing circuit is in a conductive state, while, when the capacitive circuit is in a conductive state, the short-circuit preventing circuit is in an insulating state.

Abstract: A semiconductor device includes a first semiconductor layer, an n-type/p-type second semiconductor layer, p-type/n-type third semiconductor layers and a first gate electrode. The second semiconductor layer is formed on the first semiconductor layer and has an oxidation rate which is lower than that of the first semiconductor layer. The third semiconductor layers are formed in the second semiconductor layer and have a depth reaching an inner part of the first semiconductor layer. In case that the second and third semiconductor layers are n-type and p-type, respectively, a lattice constant of the second semiconductor layer is less than that of the third semiconductor layer. In case that the second and third semiconductor layers are p-type and n-type, respectively, the lattice constant of the second semiconductor layer is greater than that of the third semiconductor layer. A first gate electrode is formed on the second semiconductor layer.

Abstract: A single stress liner is applied over different type semiconductor devices. The single stress liner avoids the problems of a dual/hybrid stress liner scheme by eliminating the meeting area. The single stress liner may be tensile or compressive. In one embodiment, the semiconductor device includes a static random access memory (SRAM) cell having numerous NFETs and PFETs. In this case, a compressive liner is placed over the SRAM cell, which is normally not ideal for the NFETs therein, but is desirable for the SRAM cell because continued miniaturization of the SRAMs typically requires slowing of the NFETs for the SRAM to maintain stabile. Where SRAM cells require increased speed, a single tensile stress liner can be implemented.

Abstract: Excessive thinning of a thin oxide in a dual gate CMOS fabrication process is mitigated. A thick gate oxide utilized to form high voltage transistors is selectively patterned to leave some thick oxide in an active area where low voltage transistors are formed. Due to fabrication conditions, the thin gate oxide that is formed in an active area where the low voltage transistors are formed may become too thin, particularly in perimeter areas of the low voltage area. Accordingly, the thick gate oxide is patterned so that some of it remains in perimeter areas of the low voltage active area. This mitigates leakage and/or other unwanted conditions that may result if low voltage transistors are formed using the gate oxide that is too thin.

Abstract: Gates of at least one of NMOS transistors and PMOS transistors of a CMOS integrated circuit are formed with a solid-solution alloy of at least two metals. The work function of the gate electrode is tunable by controlling the selection of the metals or the relative proportion of the metals that form a layer of the solid-solution alloy. In one embodiment, a layer of each metal is deposited onto the gate area of a MOS transistor. At least one metal is deposited using atomic layer deposition. The solid-solution alloy is formed by annealing subsequent to the deposition of the metals.

Abstract: Embodiments relate to a SRAM, in which a well isolation method may be applied so that an N-well and a P-well are separated from each other and that well walls of opposite conductive types are formed on facing sides. Also, the active regions of NMOS and PMOS may be connected to each other and the contacts of a PMOS drain and an NMOS source may be united to one so that the contacts are moved to the active regions of wide parts. A size of the common contact may be one to two times the size of a contact defined by a design rule. The active region may have a round bent part. The common contacts are arranged to be asymmetrical with each other. Therefore, it may be possible to secure the process margins of the active regions and the contacts, to improve a leakage current characteristic, and to improve yield. Also, it may be possible to prevent the dislocation of the active region and to omit a conventional thermal treatment process so that it may be possible to simplify processes and to reduce manufacturing cost.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a stacked gate structure, doped regions and high stress material layers. The stacked gate structure is located on the substrate. The stacked gate structure includes at least a dielectric layer and a gate sequentially disposed over the substrate. The doped regions are disposed in the substrate on each side of the stacked gate structure. The high stress material layers are disposed on the substrate to cover the doped regions. The high stress material layers can increase the mobility of the carriers in the doped regions and hence accelerate the operating speed of the device.

Abstract: A system may include detection of reliability degradation of a transistor, and change of a body bias applied to the transistor based on the detected reliability degradation.

Abstract: Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing in these upper metal layers becomes increasingly difficult to fabricate. By providing additional metal routing in the lower gate regions that may be coupled to the upper metal layers, the spacing requirements of the upper metal layers may be eased, while maintaining the size of the semiconductor device. In addition, the additional metal routing formed in the gate regions of the memory devices may be disposed parallel to other metal contacts in a strapping configuration, thus reducing a resistance of the metal contacts, such as buried digit lines of a DRAM memory cell.

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.