Patents Issued in July 19, 2007
  • Publication number: 20070164424
    Abstract: Components and materials, including thermal transfer materials, contemplated herein comprise at least one heat spreader component, at least one thermal interface material and in some contemplated embodiments at least one adhesive material. The heat spreader component comprises a top surface, a bottom surface and at least one heat spreader material. The thermal interface material is directly deposited onto at least part of the bottom surface of the heat spreader component. Methods of forming layered thermal interface materials and thermal transfer materials include: a) providing a heat spreader component, wherein the heat spreader component comprises a top surface, a bottom surface and at least one heat spreader material; b) providing at least one thermal interface material, wherein the thermal interface material is directly deposited onto the bottom surface of the heat spreader component; and c) depositing the at least one thermal interface material onto the bottom surface of the heat spreader component.
    Type: Application
    Filed: March 31, 2004
    Publication date: July 19, 2007
    Inventors: Nancy Dean, Richard Townsend, Paula Knoll, Colin Edie, My Nguyen, Dan Curran, Ignatius Rasiah
  • Publication number: 20070164425
    Abstract: This invention includes a heat sink structure for use in a semiconductor package that includes a ring structure with down sets and a heat sink connected to the ring structure. The down sets can be slanted or V-shaped. The invention also includes a method of manufacturing a semiconductor package that includes inserting a substrate with an attached semiconductor chip in a first mold portion, placing a heat sink structure on top of a portion of the substrate, placing a mold release film onto a second mold portion, clamping a second mold portion onto a portion of the heat sink structure, injecting an encapsulant into a mold cavity, wherein the encapsulant surrounds portions of the substrate, semiconductor chip and heat sink structure, curing the encapsulant, whereby the heat sink structure adheres to the encapsulant and singulating the encapsulated assembly to form a semiconductor package.
    Type: Application
    Filed: July 31, 2006
    Publication date: July 19, 2007
    Inventors: Ravi Kanth Kolan, Danny Vallejo Retuta, Hien Boon Tan, Anthony Yi Sheng Sun, Susanto Tanary, Patrick Tse Hoong Low
  • Publication number: 20070164426
    Abstract: An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die.
    Type: Application
    Filed: January 18, 2006
    Publication date: July 19, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patrick McGinnis, Darrell Miles, Richard Oldrey, John Sylvestri, Manuel Villalobos
  • Publication number: 20070164427
    Abstract: The present invention discloses a method of confining a liquid metal alloy within a closed-loop system; distributing a first portion of the liquid metal alloy in a cavity within the closed-loop system; turning on an electromagnet to generate a magnetic field to permeate flexible sidewalls of the cavity; attracting the liquid metal alloy in the cavity towards the electromagnet to expand the flexible sidewalls; inducing a second portion of the liquid metal alloy to enter the cavity from an inlet end of a heat pipe within the closed-loop system; turning off the electromagnet; repelling the liquid metal alloy in the cavity away from the electromagnet to contract the flexible sidewalls; and inducing a third portion of the liquid metal alloy to exit the cavity to an outlet end of the heat pipe.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 19, 2007
    Inventors: Ioan Sauciuc, Ravi Mahajan
  • Publication number: 20070164428
    Abstract: A semiconductor assembly is disclosed. The semiconductor assembly includes a multilayer substrate having at least two layers with conductive patterns insulated by at least two dielectric layers. The substrate includes a first surface and a second surface. A leadless package comprising a control chip is coupled to the multilayer substrate. A semiconductor die comprising a vertical transistor is coupled to the multilayer substrate. There are conductive structures on the second surface for attaching the substrate to a circuit board. The control chip and the semiconductor die are in electrical communication through the multilayer substrate.
    Type: Application
    Filed: January 18, 2006
    Publication date: July 19, 2007
    Inventors: Alan Elbanhawy, Benny Tjia
  • Publication number: 20070164429
    Abstract: A package board is provided. The package board includes a board body having a front surface and a back surface. A first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad are disposed on the front surface of the board body, and a second power pad, a second ground pad and a second signal pad are disposed on the back surface of the board body. The second power pad, the second ground pad and the second signal pad are electrically connected to the first power pad, the first ground pad and the first signal pad, respectively. An internal terminal interconnection is provided in a bulk region of the board body or on a surface of the board body. The internal terminal interconnection electrically connects the first internal terminal pad to the second internal terminal pad. A semiconductor package employing the package board is also provided.
    Type: Application
    Filed: June 16, 2006
    Publication date: July 19, 2007
    Inventor: Jong-Joo LEE
  • Publication number: 20070164430
    Abstract: The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.
    Type: Application
    Filed: November 27, 2006
    Publication date: July 19, 2007
    Applicant: MEGICA Corporation
    Inventors: Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo
  • Publication number: 20070164431
    Abstract: A wafer level chip scale package capable of reducing parasitic capacitances between a rerouting and the metal wiring of a wafer, and a method for manufacturing the same are provided. An embodiment of the wafer level chip scale package includes a wafer arranged with a plurality of bonding pads and an insulating member formed on the wafer so that the bonding pads are exposed. A rerouting is further formed on the insulating member in contact with the exposed bonding pads and an external connecting terminal is electrically connected to a portion of the rerouting. Here, the insulating member overlapping the rerouting is provided with a plurality of spaces in which air is trapped.
    Type: Application
    Filed: October 16, 2006
    Publication date: July 19, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In Young LEE, Hyun-Soo CHUNG, Dong-Ho LEE, Sung-Min SIM, Dong-Soo SEO, Seung-Kwan RYU, Myeong-Soon PARK
  • Publication number: 20070164432
    Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.
    Type: Application
    Filed: January 22, 2007
    Publication date: July 19, 2007
    Applicant: Casio Computer Co., Ltd.
    Inventors: Shinji Wakisaka, Tomohiro Ito, Shigeru Yokoyama, Osamu Kuwabara, Norihiko Kaneko, Syouichi Kotani
  • Publication number: 20070164433
    Abstract: A ball grid array package includes a substrate with a top and bottom surface. A circuit component is located on the bottom surface. The circuit component has a pair of ends. A pair of conductors are located on the bottom surface. The conductors are connected to the ends of the circuit component. A conductive epoxy covers a portion of the conductors and a portion of the bottom surface. The conductive epoxy is in electrical contact with the conductors. A ball is connected to the conductive epoxy. The conductive epoxy provides an electrical connection between the conductor and the ball. The ball is preferably copper and is subsequently coated to prevent corrosion. Other embodiments of the invention are shown in which the balls are omitted and in which the conductive epoxy is used to fill vias in a substrate.
    Type: Application
    Filed: February 12, 2007
    Publication date: July 19, 2007
    Inventor: Terry Bloom
  • Publication number: 20070164434
    Abstract: A wiring trench is formed in an interlayer insulating film partway in the depth direction of the interlayer insulating film. A via hole is formed extending from the bottom of the wiring trench to the bottom of the interlayer insulating film. A capacitor recess is formed reaching the bottom of the interlayer insulating film. A conductive member is embedded in the wiring trench and via hole. A capacitor is embedded in the capacitor recess, including a lower electrode, a capacitor dielectric film and an upper electrode. The lower electrode is made of the same material as that of the conductive member and disposed along the bottom and side surface of the capacitor recess. A concave portion is formed on an upper surface of the lower electrode, and the capacitor dielectric film covers an inner surface of the concave portion. The upper electrode is embedded in the concave portion.
    Type: Application
    Filed: August 22, 2006
    Publication date: July 19, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Kenichi Watanabe
  • Publication number: 20070164435
    Abstract: To reduce noise between a power supply wiring and ground wiring especially in a small, high-density semiconductor device for high-speed operation. A semiconductor device having a second dielectric layer 5 made of dielectric material of which the dielectric loss tan 6 is at least 0.2 and interposed between a power supply wiring layer 6 electrically connected to a semiconductor chip and a ground wiring layer 4, so composed that a dielectric loss generated in the second dielectric layer 5 acts as a low pass filter of the power supply wiring layer 6, and having a first dielectric layer 3 made of dielectric material whose dielectric loss is less than the dielectric loss tan 6 of the second dielectric layer 5 and interposed between a signal wiring layer 2 electrically connected to the semiconductor chip and the ground wiring layer 4.
    Type: Application
    Filed: December 20, 2006
    Publication date: July 19, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Kazutaka Koshiishi, Mitsuaki Katagiri, Satoshi Isa, Fumiyuki Osanai
  • Publication number: 20070164436
    Abstract: Embodiments relate to a dual metal interconnection structure of a semiconductor device and a method for manufacturing the same. In embodiments, the dual metal interconnection structure may include a contact plug selectively formed in an interlayer dielectric, which covers a silicon substrate, and contacted with an active area of the silicon substrate, a first aluminum interconnection formed on one contact plug in every two cells and having a width larger than a width of the contact plug, a dielectric wrapping an upper surface and a side plane of the first aluminum interconnection, and a second aluminum interconnection formed on one contact plug in every two cells alternatively with the first aluminum interconnection, insulated from the first aluminum interconnection by the dielectric, and having a width larger than a width of the contact plug.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 19, 2007
    Inventors: Heong Kim, Sung Kim
  • Publication number: 20070164437
    Abstract: There is included an inorganic insulating film having a porous structure including a cylindrical vacancy oriented in parallel with the surface of a substrate subjected to a hydrophilic treatment or a hydrophobic treatment.
    Type: Application
    Filed: February 6, 2007
    Publication date: July 19, 2007
    Applicant: Rohm Co., Ltd.
    Inventors: Norikazu Nishiyama, Korekazu Ueyama, Yoshiaki Oku
  • Publication number: 20070164438
    Abstract: Embodiments include interconnect of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a trench and via in the dielectric layer, the via extending to the contact surface. An interlock material is in the via with an interlock opening extending through the interlock material and into the interconnect. A layer of electroless material is on the base of the trench and the surfaces of the via, interlock material, and interlock opening. An subsequent interconnect is formed on the electroless material, in the trench, via, and interlock openings. The structure can be repeated to form a stack or column of interconnects that resist delamination.
    Type: Application
    Filed: March 8, 2007
    Publication date: July 19, 2007
    Inventors: Jiun Sir, Eng Goh
  • Publication number: 20070164439
    Abstract: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.
    Type: Application
    Filed: January 19, 2006
    Publication date: July 19, 2007
    Inventors: Chung-Hsien Chen, Chun-Chieh Lin, Minghsing Tsai, Shau-Lin Shue
  • Publication number: 20070164440
    Abstract: A first interlayer insulating film and a second interlayer insulating film are formed on a semiconductor substrate and first Cu interconnections are formed in the first interlayer insulating film and second Cu interconnections are formed in the second interlayer insulating film. Pad electrodes are formed on the second Cu interconnections with a barrier metal interposed therebetween. The pad electrodes are made of AlCu containing Mg.
    Type: Application
    Filed: October 11, 2006
    Publication date: July 19, 2007
    Inventor: Takayuki Matsuda
  • Publication number: 20070164441
    Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
    Type: Application
    Filed: February 25, 2007
    Publication date: July 19, 2007
    Applicant: MEGICA CORPORATION
    Inventors: Jin-Yuan Lee, Ying-Chih Chen, Mou-Shiung Lin
  • Publication number: 20070164442
    Abstract: A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by radiating heat from the substrate as well as from the copper layer.
    Type: Application
    Filed: February 27, 2007
    Publication date: July 19, 2007
    Inventor: Allen McTeer
  • Publication number: 20070164443
    Abstract: Semiconductor array, with an element region (400), with a conductive substrate (100), with a buried insulation layer (200), which isolates the element region (400) from the conductive substrate (100), with at least one trench (700), which is filled with an insulation material (710) and which isolates at least one element (1000) in the element region (400) from other elements in the element region (400), with an electrical conductor (750), which is connected conductively to the conductive substrate (100), wherein the electrical conductor (750) is disposed within the trench (700) isolated by the insulation material (710), and wherein the trench (700) is formed within a recess (600) in a surface. Furthermore, a method for manufacturing a semiconductor array is provided.
    Type: Application
    Filed: September 28, 2006
    Publication date: July 19, 2007
    Applicant: ATMEL Germany GmbH
    Inventors: Tobias Florian, Michael Graf, Stefan Schwantes
  • Publication number: 20070164444
    Abstract: A stacked mounting structure includes at least two substrates namely a first substrate on which a first protruding electrode is formed and a second substrate on which a second protruding electrode is formed, and an intermediate substrate which is disposed between the first substrate and the second substrate, and which connects the first substrate and the second substrate by leaving a predetermined gap between the first substrate and the second substrate. Mounted components are disposed in the gap between the first substrate and the second substrate. The first protruding electrode and the second protruding electrode are connected in an opening which is provided in the intermediate substrate.
    Type: Application
    Filed: December 14, 2006
    Publication date: July 19, 2007
    Applicant: Olympus Corporation
    Inventors: Takanori Sekido, You Kondoh
  • Publication number: 20070164445
    Abstract: Aiming at adjusting the height of bump electrodes connected to lands on a substrate, a semiconductor device 100 has a first interconnect substrate 103 and a second interconnect substrate 101. On one surface of these substrates, first lands 111 and second lands 113 are provided. The plane geometry of the second lands 113 is a polygon characterized by the inscribed circle thereof having an area smaller than the area of the inscribed circle of the first land.
    Type: Application
    Filed: January 8, 2007
    Publication date: July 19, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Daisuke Ejima
  • Publication number: 20070164446
    Abstract: An integrated circuit comprises a first substrate, an integrated circuit die attached to the first substrate, and a second substrate overlying at least a portion of the integrated circuit die. The second substrate comprises at least one conductor that is wire bonded to a conductor of the first substrate and electrically connected to a conductor of the integrated circuit die. In an illustrative embodiment, conductors of the second substrate are used to provide core power and ground connections for the integrated circuit die.
    Type: Application
    Filed: January 13, 2006
    Publication date: July 19, 2007
    Inventors: Donald Hawk, James Parker
  • Publication number: 20070164447
    Abstract: A semiconductor package including a die, a substrate and bumps is provided. The die has die pads arranged on an active surface thereof and a first passivation layer. The first passivation layer is disposed on the active surface and has first openings for exposing the die pads, respectively. The substrate has a substrate surface, substrate pads and a second passivation layer. The substrate pads are arranged on the substrate surface. The second passivation layer is arranged on the substrate surface and has a second opening for exposing the substrate pads and a portion of the substrate surface. The bumps are arranged on the die pads, respectively. Each bump is connected to one of the substrate pads through a compression bonding process, and the die is electrically connected to the substrate through the bumps. A distance between the first passivation layer and the substrate pads is smaller than 50 ?m.
    Type: Application
    Filed: June 2, 2006
    Publication date: July 19, 2007
    Inventors: Kwun-Yao Ho, Moriss Kung
  • Publication number: 20070164448
    Abstract: Provided are a semiconductor chip package with attached electronic devices, and an integrated circuit module having the same. The semiconductor chip packages may include a supporting substrate, input/output bonding pads arranged on a first plane of the supporting substrate, and device bonding pads arranged on the edges of the first plane or portions of the first plane adjacent to the edges. Accordingly, the mount area of a printed circuit board may be reduced, efficient routing may be possible, and the occurrence of package cracks may be reduced and/or prevented.
    Type: Application
    Filed: August 17, 2006
    Publication date: July 19, 2007
    Inventors: Kyoung-Sun Kim, Ki-Hyun Ko, Byoung-Ha Oh
  • Publication number: 20070164449
    Abstract: A build-up package of an optoelectronic chip mainly includes a transparent circuit carrier board, at least one optoelectronic chip, at least one dielectric layer and at least one wiring layer of a build-up package. The optoelectronic chip is flip-chip bonded to the transparent circuit carrier board. The build-up package is formed on the transparent circuit carrier board, wherein the dielectric layer covers the optoelectronic chip and has a plurality of through holes, the wiring layer is formed on the dielectric layer and is electrically connected to a substrate wiring layer of the transparent circuit carrier board via the through holes. Accordingly, the build-up package of the optoelectronic chip is a thin optoelectronic product and improves the thermal dissipation, the encapsulation, and the compact of the electrical connection of the embedded optoelectronic chip.
    Type: Application
    Filed: December 25, 2006
    Publication date: July 19, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chien-Hao Wang
  • Publication number: 20070164450
    Abstract: An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a plurality of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconnected by respective resilient suspension means. The IC is received in the receiving zone and is electrically coupled to some of the plurality of islands adjacent to the receiving zone.
    Type: Application
    Filed: February 15, 2007
    Publication date: July 19, 2007
    Inventor: Kia Silverbrook
  • Publication number: 20070164451
    Abstract: A method for electrically coupling a bond pad of an integrated circuit such as a field programmable device, an application-specific integrated circuit, or a rapid chip with an input/output device is disclosed. The bond pad is provided with a plurality of metal layers configurable for making a connection with the input/output device. The bond pad is then coupled to the input/output device with an interconnect structure. The method for electrically coupling the bond pad to the input/output device allows the customer to configure the power and ground pad counts after the slice is created.
    Type: Application
    Filed: January 19, 2006
    Publication date: July 19, 2007
    Inventors: Anwar Ali, Tauman Lau, Kalyan Doddapaneni
  • Publication number: 20070164452
    Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
    Type: Application
    Filed: February 25, 2007
    Publication date: July 19, 2007
    Applicant: MEGICA CORPORATION
    Inventors: Jin-Yuan Lee, Ying-Chih Chen, Mou-Shiung Lin
  • Publication number: 20070164453
    Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
    Type: Application
    Filed: February 25, 2007
    Publication date: July 19, 2007
    Applicant: MEGICA CORPORATION
    Inventors: Jin-Yuan Lee, Ying-Chih Chen, Mou-Shiung Lin
  • Publication number: 20070164454
    Abstract: An electronic device includes a substrate, an electrical element on the substrate, a nonconductive adhesive material on the substrate, and a conductive adhesive material on the electrical element and extending onto the nonconductive adhesive material. Methods of forming a packaged LED include providing a substrate having an electrical element thereon, and dispensing a nonconductive adhesive material on the substrate. The nonconductive adhesive material is at least partially cured, and a conductive adhesive material is dispensed on the electrical element and on the at least partially cured nonconductive material. The conductive adhesive material is at least partially cured. The conductive adhesive material may provide an electrical connection between the electrical element and a second electrical element on the substrate or on another substrate.
    Type: Application
    Filed: January 19, 2006
    Publication date: July 19, 2007
    Inventor: Peter Andrews
  • Publication number: 20070164455
    Abstract: An object of the invention is to provide a form of bending wiring patterns whose wiring resistances can be as equal as possible based on a simple structure and to provide an electronic device based on the form. An electronic device having a substrate (100) on which a plurality of conductive lines (10) are formed, the conductive lines (10) having such patterns that the lines are straightly extended from their predetermined front ends is and there-after bend by turns in substantially the same direction for each predetermined interval P to further extend to the respective predetermined connection targets (30). The conductive lines (10) have their straightly-extending portions (10L) of varied line widths and a line width at a nearer position to a bending point (Q) of the line is larger than a line width at a farther position from the bending point (Q), so as to equalize at least resistance values of the straightly-extending portions (10L) of the conductive lines (10).
    Type: Application
    Filed: December 17, 2004
    Publication date: July 19, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONIC, N.V.
    Inventor: Noriyoshi Matsuura
  • Publication number: 20070164456
    Abstract: A method is provided for repairing a die for molding a structure. A die to be repaired has holes for supplying a material, grooves arranged in a lattice form for communicating with the respective holes and for forming the material into a desired shape, and worn-out portions caused by repeated use. In the method, a repairing film is formed on a surface having the grooves and serving as an end face of a die body, through which extrusion is performed, so as to extend onto each corner at an intersecting line between the groove-formed surface and an inner side face of each groove, to restore each worn-out portion. Meanwhile, a material is supplied from the groove-formed surface side utilizing either one or both of PVD and CVD processes. This method readily provides a repaired die with good accuracy, which is excellent in durability and abrasion resistance.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 19, 2007
    Applicant: Denso Corporation
    Inventor: Hitoshi Kanmura
  • Publication number: 20070164457
    Abstract: A semiconductor package comprising: a substrate containing a wiring pattern connected to a plurality of external electrodes; one or more semiconductor chips connected to the wiring pattern and mounted on the substrate; a conductive post connected to a predetermined the external electrode and functioning as a relay electrode in a vertical direction; and a resin sealing layer for integrally sealing the semiconductor chips and the conductive post in a state in which an upper end face of the conductive post is exposed.
    Type: Application
    Filed: January 18, 2007
    Publication date: July 19, 2007
    Inventors: Masahiro Yamaguchi, Hirofumi Nakamura
  • Publication number: 20070164458
    Abstract: In a mold in which a pattern is formed of a fine concavo-convex shape, two or more of alignment marks for determining a relative positional relation between a substrate and a mold are formed concentrically. Moreover, a damaged mark is identified from the positional information and shape of the respective marks, and an alignment between the mold and the substrate to which a resin film is applied is carried out excluding the damaged mark.
    Type: Application
    Filed: January 17, 2007
    Publication date: July 19, 2007
    Inventors: Masahiko Ogino, Akihiro Miyauchi, Takashi Ando, Chiseki Haginoya, Susumu Komoriya, Yasunari Sohda, Souichi Katagiri, Hiroya Ohta, Yoshinori Nakayama
  • Publication number: 20070164459
    Abstract: A nozzle for atomising a liquid by means of a gas comprises a mixing chamber (1), one or more liquid inlets (6c) and at least one tangential gas inlet (5) to the mixing chamber. An outlet (4) is positioned at the downstream end of the mixing chamber (1). A centre body (2) having a generally converging configuration, seen in the flow direction is provided in the mixing chamber (1). The liquid inlet (6c) or inlets is/are positioned at or near the upstream end (3a) of the mixing chamber (1) and in the upstream direction with respect to the gas inlet (5) or inlets.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 19, 2007
    Applicant: NIRO A/S
    Inventors: Niels Gottlieb, Per Sorensen, Heinz Wullschleger
  • Publication number: 20070164460
    Abstract: A completion suspension valve system is described which allows a well to be suspended and desuspended remotely without a dual bore riser to the surface. This is achieved by incorporating a remotely actuatable valve into the production bore of a tubing hanger. The valve is hydraulically operable and may be controlled via the tubing hanger running tool or via the xmas tree. The valve can be closed and tested after the tubing hanger has been installed, thereby isolating the well. The dual bore riser and running tool are retrievable and the MODU type vessel is then free to continue drilling and completion operations elsewhere. The xmas tree can therefore be deployed from a workclass supply boat instead of a MODU type vessel.
    Type: Application
    Filed: December 16, 2004
    Publication date: July 19, 2007
    Inventor: Kurt Andersson
  • Publication number: 20070164461
    Abstract: A breathable liquid-volatizing device for maintaining the relative humidity in a space includes a rectangular closed casing. The casing is hollow and provided with an inlet port. A plurality of parallel draining grooves are provided on the bottom plate of the casing. A plurality of breathable plates are provided under the casing corresponding to the positions of the draining grooves. A water-absorbing layer is provided in the interior of the breathable plate. A film having tiny pores is covered on the outer surface of the water-absorbing layer. When the liquid water is poured into the closed casing through the inlet port, it flows into the breathable plate via the draining grooves provided on the bottom plate and is absorbed by the water-absorbing layer. With the pressure difference between the inside and the outside of the film, the liquid water can be pressed out of the tiny pores and transformed into vapor molecules, thereby to maintain the density of the vapor molecules in the air.
    Type: Application
    Filed: January 13, 2006
    Publication date: July 19, 2007
    Inventor: Nein-Jung Wang
  • Publication number: 20070164462
    Abstract: The grid falling film devolatilizer according to this invention consists of a tower housing, a liquid distributor and a tower internal, said tower internal includes pillars and multiple grid trays, the cross section of said tower internal being square or rectangular, and the four pillars stand respectively at the four corners of the tower internal. Each grid tray includes a pair of beams, a plural of grid bars and corresponding guide members, among them said beams being located at opposite pair of sides of the grid tray and fixed to the pillars, said grid bars being perpendicular to the beams, and said guide member being installed between the grid gaps, so that the liquid pass through those grid gaps and generate films and thus producing huge devolatilization interfaces. The special design according to the invention ensures the substantial renewal of film surface in each grid tray.
    Type: Application
    Filed: October 21, 2004
    Publication date: July 19, 2007
    Inventors: Zhaoyan Liu, Jingyun Shi
  • Publication number: 20070164463
    Abstract: An object is to transfer a concavo-convex pattern formed on the surface of a transfer die onto a transfer target accurately. A pattern transfer apparatus according to the present invention is one for putting a transfer die having a concavo-convex pattern against a transfer target on a substrate to transfer the concavo-convex pattern onto a surface of the transfer target. It is characterized by comprising pressing means for pressing the transfer die against the transfer target on the substrate at a plurality of different locations independently.
    Type: Application
    Filed: March 15, 2005
    Publication date: July 19, 2007
    Applicant: PIONEER CORPORATION
    Inventor: Osamu Kasono
  • Publication number: 20070164464
    Abstract: A medical device and its use are described. The device is useful for replacement or treatment of a diseased or damaged intervertebral spinal disc. The device has volume to occupy space between vertebral bodies, has mechanical elasticity to provide motion between vertebral bodies, and sufficient strength to withstand the forces and loads on the vertebra. The device may have modifications to allow for attachment to the bones of the vertebrae. The device may also contain modifications for ease of placement in the anatomic space between vertebral bodies. The device may be constructed to expand to restore the normal height o the intervertebral space.
    Type: Application
    Filed: March 21, 2007
    Publication date: July 19, 2007
    Inventor: David Ku
  • Publication number: 20070164465
    Abstract: A mold for molding a product in a cavity formed by closing the mold includes a first half; a second half; and a plurality of aligning members which come in contact with each side circumferential surface of the first half 100 and the second half at least in three directions, when the mold is closed. After the mold is closed, at least one of the aligning members is moved to contact the aligning member with the each side circumferential surface of the first half and the second half, which enables a center axis alignment between the first half and the second half.
    Type: Application
    Filed: January 9, 2007
    Publication date: July 19, 2007
    Applicant: FUJIFILM Corporation
    Inventors: Noriko Eiha, Seiichi Watanabe, Yasuhito Hiraki
  • Publication number: 20070164466
    Abstract: Process for production of foam webs or foam sheets, these webs or sheets being based on a polymer selected from polysulfones, polyetherimides, polyether ketones, and styrene polymers, via extrusion of a melt which comprises the polymer and a blowing agent, and then foaming of this melt, which comprises a process in which the melt also comprises from 1 to 50% by weight, based on the polymer, of a filler selected from A) a fibrous filler A, B) a particulate, non-graphite filler B, and mixtures of these.
    Type: Application
    Filed: February 16, 2005
    Publication date: July 19, 2007
    Inventors: Dietrich Scherzer, Rudiger Bluhm, Franz-Josef Dietzen, Swen Ruck
  • Publication number: 20070164467
    Abstract: The processes and resins of the present invention allow the extrusion of polymer products, such as polymer films, that have a reduced occurrence of surface aberrations, e.g., surface melt fracture and/or haze bands and/or haze. Preferably, the polymer products produced in accordance with the present invention are substantially free of surface aberrations even when manufactured under conditions of high sheer stress such as those conditions that occur at commercial production rates. In part, the present invention provides processes for polymer extrusion wherein the resins employed are treated using heat in an atmosphere sufficient to substantially eliminate the tendency to create surface aberrations. The resins can have reduced or substantially eliminated concentrations of low molecular weight components. In some embodiments, both the polymer resins and the extruded polymer products have reduced concentrations of processing aid(s), e.g.
    Type: Application
    Filed: June 16, 2004
    Publication date: July 19, 2007
    Inventors: David Smith, Michael Andrews
  • Publication number: 20070164468
    Abstract: The present invention concerns a process for producing fibre composites. In particular, the invention provides a novel way of producing biodegradable composites comprising a hydrophobic polymer material and a reinforcing component of fibres derived from plant materials. Composite material produced by means of the present invention has improved strength properties and enhanced adhesion between the bifunctional fibre and the natural or synthetic polymer.
    Type: Application
    Filed: December 23, 2004
    Publication date: July 19, 2007
    Applicant: VALTION TEKNILLINEN TUTKIMUSKESKUS
    Inventors: Johanna Buchert, Stina Gronqvist, Hannu Mikkonen, Tarja Oksanen, Soili Peltonen, Anna Suurnakki, Liisa Viikari
  • Publication number: 20070164469
    Abstract: A molding coping fixture is disclosed. The coping fixture includes a plurality of shims, where the shims can be adjusted to conform to a profile of a molding to be coped, the shims are secured into the fixture and maintain the profile during a coping cut by a router. The coping fixture according to the present invention also includes an anti-tear-out device prevent tear-out of material from the molding during the coping cut. In various preferred embodiments, some or all of the anti-tear-out device may be replaceable. The coping fixture according to the present invention also includes a fixture for selectively adjusting the angle of the coping cut. In various preferred embodiments, a guide pin passes along the shims and a router bit secured in a fixed relation to the guide pin performs the coping cut while the guide pin passes along the shims.
    Type: Application
    Filed: November 21, 2006
    Publication date: July 19, 2007
    Inventor: Anthony Brcich
  • Publication number: 20070164470
    Abstract: [Problem to be Solved] An object of the present invention is to obtain a component, such as an end plate of a silencer by one cycle of pressing operation for a sheet material. [Solution] A press forming apparatus comprises an upper die 10 provided with an upper drawing die 13, a punch 12, an upper movable blank holder 14, and a trimming member 15 and a lower die 20 provided with a lower drawing die 23, a die 22, an outer periphery drawing die 24, and a lower movable blank holder 25. The upper die is lowered with respect to the lower die, and the outer periphery portion of a blank B is held by the trimming member and the upper blank holder. Then, the central portion of the blank is drawn by the upper and lower drawing dies. Next, the outer periphery portion of the blank is trimmed by the trimming member and the outer periphery drawing die, and then drawing of the outer periphery portion of the blank is started by the upper drawing die and the outer periphery drawing die.
    Type: Application
    Filed: September 6, 2004
    Publication date: July 19, 2007
    Inventors: Jiro Sasaki, Masahiro Morishita
  • Publication number: 20070164471
    Abstract: In accordance with one embodiment of the present invention, a system for controlling the properties of an extrusion from a production line is provided. The production line comprises a raw material feed, a mixer, and an extruder. The control system comprises one or more ammeters electrically coupled to an electrically driven mixing motor and an electrically driven extrusion motor. Output signals indicative of the load amperes IM of the mixing motor and the load amperes IX of the extrusion motor are provided. The controller is in communication with the raw material feed and the ammeter and is programmed to compare the load amperes IX of the extrusion motor to the load amperes IM of the mixing motor and determine whether a result of the load ampere comparison warrants modification of an operating parameter of the production line. If so, the controller modifies one or more operating parameters of the production line to account for the variation from the target value.
    Type: Application
    Filed: December 13, 2006
    Publication date: July 19, 2007
    Applicant: JOURNEY ELECTRONICS CORP.
    Inventor: Michael Gorden
  • Publication number: 20070164472
    Abstract: A method of and an apparatus for producing a hollow body of thermoplastic includes the steps of injection molding a first hollow body part with an outward-protruding first joining edge, injection molding at least a second hollow body part with an outward-protruding second joining edge, putting the hollow body parts together at the first and second joining edges, and connecting the first and the at least one second hollow body part by a molded, at least partially U-shaped sealing portion comprising a thermoplastic.
    Type: Application
    Filed: April 5, 2005
    Publication date: July 19, 2007
    Inventors: Thomas Endig, Volker Brielmann, Bernd Beiermeister, Joerg Hielscher, Alexander Ziegler, Olof Hansen
  • Publication number: 20070164473
    Abstract: A method of forming a sealing or mounting strip on the periphery of a vehicle door 4 is disclosed. The method includes providing a fixed extrusion device 15 for producing an extruded sealing or mounting strip, moving the door 4 with respect to the fixed extrusion device 15, while operating the extrusion device 15 to produce the extruded sealing or mounting strip, such that the sealing or mounting strip 10 is formed along a desired path 10 on the door 4. The door 4 is mounted in a frame 27 which clamps the door 4 around the door's edge. The frame 27 is movable by any suitable means, such as by a robot typically used in automated vehicle fabrication plants. By making use of the frame 27 and movement means already provided in a conventional automated vehicle fabrication plant, little or no additional cost is incurred by providing for movement of the door 4 with respect to the fixed extrusion die 15.
    Type: Application
    Filed: December 12, 2003
    Publication date: July 19, 2007
    Applicant: GDX North America Inc.
    Inventor: Ralf Hoge