Abstract: A flickering display system has: a display, a microprocessor, one or more light emitting diodes and digital memory, the memory storing one or more digital images of a lighted candle. Under control of the microprocessor, the digital images are displayed on the display and the diodes activate in a flame area of the candle such that, when viewed, the digital images and diodes appear like a real candle. Optionally the system includes an aroma generator that produces a scent similar to the scent produced when burning a scented candle.

Abstract: An umbrella structure is disclosed with a plurality of lights attached to each of a plurality of arms. The umbrella structure includes a pole and a movable device attached to the pole so that the movable device can slide up and down the pole. The movable device can be moved to move the plurality of arms having the plurality of lights attached thereon.

Abstract: The taillight assembly is mountable to a swing arm of a rear suspension motorcycle frame and includes a tubular cover housing and an LED lamp disposed within the cover housing. The LED lamp is electrically wired to the motorcycles electrical system by wires that are run internally through the cover housing and swing arm. The LED lamp uses a plurality of individual light emitting diodes (LEDs), which convert electric energy into electromagnetic radiation (light). The LED lamp is configured so that one portion of the LEDs emit a red light and another portion emit a white light.

Abstract: The invention provides a lighting apparatus which can reduce a layout space within a vehicle and can easily arrange a wiring. A translucent portion of a board lighting apparatus and a translucent portion of a console lighting apparatus are structured such as to serve as a decorative luminous portion and a lighting luminous portion. Since the board lighting apparatus is arranged in an upper side of a glove compartment, it is possible to apply decoration to a portion around the glove compartment and light a space at a time when the glove compartment is open. Since the console lighting apparatus is arranged in an upper side of the center console, it is possible to apply decoration to a portion around the center console and light an area around the feed of a passenger.

Abstract: The present invention provides a lamp for a vehicle provided to a forward inclined face of a roof of a vehicle. The forward inclined face inclines downward and forward of the vehicle from a top of the roof. The lamp for a vehicle is provided with a light emitting face at least on a top face thereof.

Abstract: For creating a lighting system (1) for a vehicle comprising a reflector (4) and a light source (5), wherein the lighting system (1) can be adapted with as low an outlay as possible to different specifications in regard to light distribution, it is proposed that a light distribution corresponding to a first specification can be created by the interaction between the reflector (4) and a first light source (5), and that a light distribution in accordance with a second specification can be created by the interaction between the reflector (4) and a second light source (5).

Abstract: A vehicle lighting device includes a reflection type lamp unit including a first LED that emits light downward; and a reflective face that reflects part of the light emitted by the first LED outward to the front of the vehicle lighting device. Part of the light emitted by the first LED is output, as directly emitted light, directly to the front of the vehicle lighting device. The reflective face includes a first reflective portion that reflects light as vertically almost parallel light and as horizontally diffused light, and a second reflective portion that reflects light below the light reflected by the first reflective portion and above the directly emitted light.

Abstract: A first LED unit, a first reflector, a second LED unit, a second reflector, and a light source mount which supports the first LED unit and the second LED unit are provided in a light chamber. The first reflector is formed integrally with a projection lens and forwardly reflects direct light outputted from a first LED to the central axis of the lens. The second reflector is formed integrally with the projection lens and forwardly reflects direct light outputted from a second LED. The light source mount has a fixing portion adapted to perform the positioning of the projection lens, the first reflector and the second reflector, which are formed integrally with a connecting member, in the direction of the central axis of the lens. The light source mount also has a positioning projection and positioning recesses, which are adapted to perform the positioning of the projection lens, the first reflector and the second reflector in a direction perpendicular to the central axis.

Abstract: The trunks and/or branches of a decoration tree are made of “metal mesh/insulation/metal mesh” sandwiched structure. Ornamental articles are configured to be easily and rapidly inserted into the sandwiched structure to decorate the decoration tree. The two metal meshes are each coupled to one of the two electrodes of an electric power supply. The coaxial pin of each ornamental article is made coaxial to couple to the two metal meshes respectively, so that the ornamental article shines when it has been inserted in the trunks or branches of the tree.

Abstract: A prism of backlight module and structure thereof is provided. The prism includes a central area on which geometrical units are formed and arranged adjacent to each other on the prism and a periphery area, being a planar structure, located at two sides outside the central area and terminated at edges of the prism. The prism applied to a backlight module is provided by an integrity process or mold punching process or by providing a shielding surface formed by an ink print method on a lower surface of a base of the periphery area of the prism. As such, the problem of light condensing at edges of the prism in a general notebook computer due to absence of an upper diffuser may be reduced and light leakage may also be reduced.

Abstract: A display device (1) has an extendible screen (2) and at least one extendible side member (3). The extendible screen (2) is extendible in an extension direction from a relatively compact form to an extended form. The screen (2) in the extended form has opposed edges (17) that are substantially parallel to the extension direction. An extendible side member (3) is provided for at least one of said opposed edges (17). The or each extendible side member (3) is extendible to provide support to and structural rigidity to the screen (2) when the screen (2) is in the extended form. The display device (1) provides an extendible rigid screen (2) suitable for example for creating a rigid collapsible tablet computer, or enabling a compact portable display to support a rigid touch-screen, or for incorporation into a mobile phone or remote control unit.

Abstract: The present invention provides a backlight unit. The backlight unit includes a light guide plate (LGP) having a incident surface and a plurality of light emitting diodes (LEDs) disposed adjacent to the incident surface. Each LED has an light-emitting axis, and the light-emitting axes are not parallel. The present invention further provides a liquid crystal display module including the backlight unit described above and a liquid crystal display panel disposed over the backlight unit. Moreover, the present invention provides an electronic device including the liquid crystal display module described above and a control circuitry electrically connected to the liquid crystal display module.

Abstract: A point light source is converted into a plane light source having a satisfactory uniformity. The point light source is converted into a line light source by means of a linear light guiding plate, and further into the plane light source by means of a plane-like light guiding plate. Light from the point light source is reflected at a lamp reflector to be incident on at least two side surfaces of the plane-like light guiding plate.

Abstract: A frequency converter includes an intermediate circuit without any capacitors and an electronics which is supplied with power from a power supply device. The power supply device has a buffer capacitor which is disposed on an input side of the power supply device and connected electrically in parallel with the intermediate circuit. Connected to the buffer capacitor is a supply line in which a decoupling diode is disposed. A semiconductor adapted to be switched off is connected electrically back-to-back in parallel with the decoupling diode and has a control output which is connected to an output of an identification device for recognizing a power-line failure.

Abstract: System and method for processing analog voltage for cold-cathode fluorescent lamp. The system includes a voltage-to-current converter configured to receive an input analog voltage signal and generate a first current signal, and a current processing component configured to receive the first current signal and a predetermined current and generate a second current signal. Additionally, the system includes a current-to-voltage converter configured to receive the second current signal and generate an output analog voltage signal, and a dimming controller configured to receive the output analog voltage signal and generate a control signal for driving at least a cold-cathode fluorescent lamp. The voltage-to-current converter, the current processing component, and the current-to-voltage converter are configured to be biased between a first power supply voltage level and a second power supply voltage level.

Abstract: The control apparatus for controlling a voltage transforming apparatus having a transformer, power switching elements disposed in a primary side, and synchronous-rectifying switching elements disposed in a secondary side includes a judging circuit making a judgment as to whether or not an output current of the voltage transforming apparatus is smaller than a specified current on the basis of a primary-side current of the transformer and an inhibition circuit inhibiting the synchronous-rectifying switching elements from performing their synchronous-rectifying control operation when the judging circuit judges that the output current is smaller than the specified current. The judging circuit makes the judgment on the basis of the primary-side current flowing through the primary coil of the transformer immediately before the power switching elements are turned off.

Abstract: The control apparatus for controlling a voltage transforming apparatus having a transformer, power switching elements disposed in a primary side, and synchronous-rectifying switching elements disposed in a secondary side includes a judging circuit making a judgment as to whether or not an output current of the voltage transforming apparatus is smaller than a specified current on the basis of a primary-side current of the transformer and an inhibition circuit inhibiting the synchronous-rectifying switching elements from performing their synchronous-rectifying control operation when the judging circuit judges that the output current is smaller than the specified current. The judging circuit makes the judgment with compensating for a variation of a relationship between the primary side-current and the output current due to variation of duty ratio of the power switching elements, and variation of at least one of the DC output voltage and the DC input voltage of the voltage transforming apparatus.

Abstract: One embodiment of the present invention includes a communication network comprises a communication cable having a first wire pair and a second wire pair that both extend between a first end and a second end of the communication cable. The network also comprises at least one power source configured to provide a first supply current through the first wire pair and a second supply current through the second wire pair at the first end of the communication cable. The first supply current and the second supply current can be substantially equal. The network also comprises a first diode bridge and a second diode bridge coupled to the second end of the communication cable and configured to combine the first and second supply currents to provide a combined supply current. The network further comprises a powered device configured to receive the combined supply current.

Abstract: A driver circuit provides a driving signal to the power stage of a switched mode power supply in correspondence with a pulse width modulated duty cycle. A voltage doubler circuit including a bucket capacitor and plural switches is arranged to successively couple the bucket capacitor to the input power source and to the driver circuit. The voltage doubler circuit thereby provides the driving signal to the driver circuit having a voltage approximately double the corresponding voltage of the input power source. The voltage doubler circuit discharges the bucket capacitor into the driver circuit to provide the driving signal in correspondence with a first portion of the pulse width modulated duty cycle, and the voltage doubler circuit recharges the bucket capacitor in correspondence with a second portion of the pulse width modulated duty cycle.

Abstract: Virtualization arrangements, including: splitting a relationship between a first and second virtual volume; receiving a differential copying request; if the differential copying request indicates to copy differential data from one of the first and second virtual volume to the other of the first and second virtual volume, (1) controlling to copy the data to the one of the first and second virtual volume based on the differential information, and (2) transferring the data to the other of the first and second logical volume of the storage systems, so that the storage system can write the data of the write request to a storage area of the disk drives.

Abstract: A magnetic field probe apparatus includes a loop-like conductor and feeder lines spaced at a distance from the loop-like conductor. The shape of the loop-like conductor and the arrangement of the feeder lines are adjusted in such a manner that the resonance frequency determined by the combination of the inductance of the loop-like conductor line and the capacitance formed between the looped-conductor and the feeder lines, is matched to the frequency of the magnetic field generated by and in the vicinity of a measurement object (e.g. electronic device) or the frequency of the electric signal which generates the magnetic field. With the magnetic field probe apparatus according to this invention, the magnetic field in the vicinity of the measurement object can be measured with high sensitivity.

Abstract: A data access system for accessing data stored in a first and a second memory devices. The first and second memory devices have a difference of latency ?L that constitutes a time-duration by which the first memory device starts an initial data access earlier than in the second memory device. A data access controller is implemented to simultaneously access data in the first and second memory devices and to stop accessing data in the first memory device once a data access operation has begun in the second memory device. Therefore, the first memory device stored data only accessed initially in a time duration corresponding substantially to the difference of latency ?L before the data access operations is started in the second memory device.

Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

Abstract: Systems and methods according to aspects of the present invention are described. The systems and methods enable charging, soaking, and measuring of capacitors to be conducted quickly. Charging and soaking typically occurs in parallel and certain embodiments facilitate the measuring of capacitor leakage by sequentially disconnecting each capacitor and measuring the time for voltage on the capacitor to reach a predetermined threshold. Further, all capacitors can be disconnected from a charging source simultaneously and voltages can be measured for each capacitor simultaneously. Monitoring can be periodic in nature. Substantial time savings in the calculation device of leakage values and parameters can be attained.

Abstract: Nanoelectromechanical (NEM) memory cells are provided. More particularly, NEM memory cells are provided by anchoring a conductive nanometer-scale beam (e.g., nanotube) to a base and allowing a portion of the beam to move. A charge containment layer is provided in the vicinity of this free-moving portion in which a charge may be stored. To read if a charge of a particular polarity is stored in a charge containment layer, a charge is formed on the nanotube. If a charge is being stored in the charge containment layer then forces between the charged nanotube and charge containment layer will cause the free-moving portion of the nanotube to be displaced toward or away from a sense contact depending on the polarity of the charge formed on the nanotube. Numerous other NEM memory cell embodiments are also provided. For example, the beam may contact a sense contact at an ambient frequency when no charge is stored in the charge containment layer due to the thermal vibrations of the surrounding environment.

Abstract: An asymmetric Static Random Access Memory (SRAM) cell is provided. The SRAM cell comprises first and second storage nodes, drive transistors and access transistors. The first and second storage nodes are configured to store complementary voltages. The drive transistors are configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and maintain a first logic state through a feedback loop. The access transistors are configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines and maintain a second logic state through relative transistor leakage currents. A method for reading from and writing to the SRAM cell are also provided.

Abstract: A toggle MTJ is disclosed that has a SAF free layer with two or more magnetic sub-layers having equal magnetic moments but different anisotropies which is achieved by selecting Ni˜0.8Fe˜0.2 for one sub-layer and CoFeB or the like with a uni-axial anisotropy of 10 to 30 Oe for the higher anisotropy sub-layer. When a field is applied at <10° angle from the easy axis, magnetic vectors for the two sub-layers rotate to form different angles from the easy axis. A method is also described for selectively writing to bits along a word line that is orthogonal to bit line segments and avoids the need to “read first”. A bipolar word line pulse with two opposite pulses separated by a no pulse interval is applied in the absence of a bit line pulse to write a “0”. A bit line pulse opposite the second word line pulse writes a “1”.

Abstract: It is made possible to cause spin inversion at a low current density which does not cause element destruction and to conduct writing with a small current. A magnetoresistance effect element includes: a magnetization pinned layer in which magnetization direction is pinned; a magnetic recording layer in which magnetization direction is changeable, the magnetization direction in the magnetization pinned layer forming an angle which is greater than 0 degree and less than 180 degrees with a magnetization direction in the magnetic recording layer, and the magnetization direction in the magnetic recording layer being inverted by injecting spin-polarized electrons into the magnetic recording layer; and a non-magnetic metal layer provided between the magnetization pinned layer and the magnetic recording layer.

Abstract: A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value at a time following reading of the stored charge. The memory cell includes a first capacitor connected between a first node and ground. A second capacitor is connected between a second node and ground, and a first switch is connected between the first node and the second node. A second switch and a third capacitor are connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the third capacitor comprising a third node. A third switch is connected between the third node and ground. In operation, in a first storage phase the first and third switches are closed and the second switch is open.

Abstract: An embodiment of a flash memory device comprises a cell array including memory cells coupled to bit lines, a decoder configured to decode successive logical column addresses into physical column addresses that are arranged non-sequentially, and a gate circuit to partially select the bit lines in response to the decoded addresses. Physically adjacent bit lines may be activated so that electrical coupling effects are eliminated by non-successively activating the bit lines.

Abstract: Data from an n-time pad is used in security-related tasks. To accommodate use of the pad with security-related tasks of different security ratings, the maximum number of times any particular data from the pad is used is determined by the security rating of the highest-security application using that data.

Abstract: A method and apparatus for correcting embedded memory that has been identified as being defective by a memory controller. The address of the defective memory is provided by the memory controller to Built-In Test (BIST) logic in combination with a Built-In Redundancy Analyzer (BIRA) to replace the defective memory element with a redundant element.

Abstract: The present invention discloses a system and method for delivery of software payload from a peripheral device to a host system, with generally one component of the software payload enabling the host system to communicate with the peripheral device. The method of the present invention uses an electronic component/storage device associated with the peripheral device (or provides one if none exists), and configures the electronic component to comprise a file system (e.g., CDFS—Compact Disk File System) and files that are native to operating system of the host (e.g., AUTORUN.INF), which the host system can recognize, access, and use automatically for initiating communications with the peripheral device, and delivery of the software payload. When communication with the host is established, any program can be loaded from the peripheral device to the host because the peripheral device appears to the host system as a CD ROM with an AUTORUN. INF file.

Abstract: A nonvolatile memory device and method thereof are provided. The example method may include applying a first bias voltage to a gate electrode, applying a second bias voltage to a substrate to obtain a first voltage potential difference between the gate electrode and the substrate and applying a third bias voltage to a first impurity region to obtain a second voltage potential difference between the substrate and the first impurity region, the first and third bias voltages being positive and the second bias voltage being negative.

Abstract: A memory circuit arrangement includes a memory cell array having a plurality of memory cells. A memory read/verify control circuit controls a read operation and/or a verify operation on one or a plurality of memory cells of the memory cell array. The memory read/verify control circuit is adapted to read and/or verify the status of each memory cell of the memory cell array according to read and/or verify instruction information on memory cell level.

Abstract: A nonvolatile semiconductor memory that have a a plurality of bit lines and word lines disposed crossing each other; a memory cell array having a plurality of electrically-programmable memory cells disposed in a region where the bit lines and the word lines are crossing; a trimming circuit which is operated a parameter of initial program voltage every the word line; an initial programming voltage parameter memory section which is stored receiving the parameter of initial program voltage from the trimming circuit; and a controller which is data program for the memory cell array based on the parameter of initial program voltage stored in the initial programming voltage parameter memory section.

Abstract: A data transfer apparatus that performs burst transfer includes a buffer memory that temporarily stores data sent from a sending apparatus, and a control unit that controls data transfer to and from the sending apparatus. When an amount of free space in the buffer memory is equal to or less than a predetermined threshold value, the control unit sends a stop request to stop the data transfer to the sending apparatus.

Abstract: There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.

Abstract: A non-volatile memory latch may be formed with a phase change memory layer. Such a latch may be faster and more easily integrated into main stream semiconductor processes than conventional latches that use non-volatile memory elements such as flash memory.

Abstract: Described embodiments generally relate to methods of encoding data on a data storage medium and methods of decoding and reading such encoded data. Other aspects relate to systems or apparatus for performing these methods. Still other aspects relate to systems and methods for monitoring use of data recorded on data storage media. These aspects are particularly suited to protecting proprietary data against unauthorized or excessive copying, where the proprietary data is embodied on a data storage medium that is publicly available for rent or sale.

Abstract: A nonvolatile semiconductor memory device comprises a memory array of 3-level nonvolatile memory cells. The memory array comprises first even and odd strings of memory cells connected to respective first even and odd bit lines and second even and odd strings of memory cells connected to respective second even and odd bit lines. The first even and odd bit lines are selectively connected to a first common bit line during data programming and read operations, and the second even and odd bit lines are selectively connected to a second common bit line during data programming and read operations. The device programs and reads data in a pair of memory cells using three bits of data corresponding to three threshold voltage distributions of the 3-level nonvolatile memory cells.

Abstract: A system is provided for a wireless local area network. The system includes, but is not limited to, at least one cell controller and simplified RF ports which are configured to provide lower level media access control functions. Higher level media access control functions are provided in a cell controller, which may service one or more RF ports that are capable operating with at least two wireless local area subnetworks. Mobile units can also be configured with the higher level media access control functions being performed in a host processor.

Abstract: A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.

Abstract: A nano-technology modeling method wherein a group of atoms and an interaction thereof to an open environment are defined by Hamiltonian matrices and overlap matrices, matrix elements of the matrices being obtained by a tight-binding (TB) fitting of system parameters to a first principles atomistic model based on density functional theory (DFT) with non-equilibrium density distribution.

Abstract: A shift register has multiple stages each of which includes a pull-up part to generate a current gate line driving signal having a first state in response to a first control signal and a clock signal, a pull-down part to generate the current gate line driving signal having a second state in response to a second control signal, a pull-up driver to generate the first control signal to control the pull-up part in response to a previous gate line driving signal provided from a previous stage, a following gate line driving signal provided from a following stage, and an input voltage signal externally provided, and a pull-down driver to generate the second control signal to control the pull-down part in response to a third control signal provided from the pull-up driver and the input voltage signal, in which the second control signal swings between first and second voltage levels in association with the input voltage signal that swings between predetermined voltage levels.

Abstract: An apparatus, method, system, computer program and product, each capable of managing supply information of an image forming device provided in an image forming apparatus, and displaying the supply information.

Abstract: A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.

Abstract: A method of arranging redundancy fuse block arrays may reduce test time for a memory device. The memory device may include a stack bank structure in which at least two banks share a row decoder or a column decoder. Redundancy fuse block arrays for the two banks may be alternately arranged in an X-axis direction or a Y-axis direction of a wafer. Accordingly, a tester may repair defective rows or columns of the two banks without shifting from one axis.

Abstract: Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output (LIO) line and a global input/output (GIO) line each having first and second signal lines. A source follower circuit, coupled between the LIO line and the GIO line, includes first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO and a gate coupled to the first and the second signal lines of the LIO. A third NMOS transistor has a source coupled to the source of the first and the second NMOS transistors, a gate coupled to a reference voltage supply and a drain coupled to a drain of a fourth NMOS transistor. The fourth NMOS has a gate to which a selection signal is applied and a source coupled to a ground.

Abstract: This disclosure concerns a semiconductor memory including memory cells; a first dummy cell and a second dummy cell generating a reference potential and storing first data and second data of mutually opposite polarities, respectively; word lines; a first and a second dummy word lines connected to gates of the first and the second dummy cells; a pair of bit lines; and a sense amplifier provided for the pair of bit lines, the sense amplifier detecting the first data using the second data as a reference or detecting the second data using the first data as a reference in a refresh operation of the first and the second dummy cells