Abstract: A thin film transistor comprising at least three terminals consisting of a gate electrode, a source electrode and a drain electrode; an insulator layer and an organic semiconductor layer on a substrate, which controls its electric current flowing between the source and the drain by applying a electric voltage across the gate electrode, wherein the organic semiconductor layer comprises a styryl derivative having a styryl structure expressed by C6H5—CH?CH—C6H5, or a distyryl structure expressed by C6H5—CH?CH—C6H5—CH?CH—C6H5 each without molecular weight distribution. The transistor has a fast response speed (driving speed), and further, achieves a large On/Off ratio getting an enhanced performance as a transistor.

Abstract: Provided is an organic light emitting device that includes at least one organic layer between a first electrode and an emissive layer wherein the organic layer includes at least two organic materials and at least one of the organic materials consequently has a concentration gradient in the direction from the first electrode to a second electrode through a single solution process by self organization. Since the organic layer has a work function having a gradient in the direction from the first electrode to the second electrode, holes can be injected from the first electrode to the emissive layer, and thereby an organic light emitting device having high efficiency and a long lifetime can be obtained.

Abstract: Provided are an organic electro-luminescent display (“OELD”) and a method of fabricating the OLED. The OELD includes an organic light emitting diode (“OLED”), a driving transistor driving the OLED, and a switching transistor controlling an operation of the driving transistor. The driving transistor includes an active layer having a crystal structure grown in a direction parallel to a current channel of the driving transistor, and the switching transistor includes an active layer having a crystal structure grown in a direction perpendicular to a current channel of the switching transistor. Accordingly, the requirements for the switching transistor and the driving transistor can be satisfied in designing the OELD. Therefore, it is possible to efficiently fabricate a low-mobility switching transistor and a high-mobility driving transistor.

Abstract: A method of fabricating a dual panel-type active matrix organic electroluminescent device includes patterning a first metal layer to form a gate electrode, a gate line, a power line, a gate pad, and a power pad on a first substrate, forming a first insulating layer on the first substrate to cover the gate electrode, the gate pad, and the power pad, forming a semiconductor layer on the first insulating layer over the gate electrode, the semiconductor layer including an active layer of undoped amorphous silicon and an ohmic contact layer of doped amorphous silicon, forming source and drain electrodes, a data line, a first link electrode, and a data pad, wherein the source and drain electrodes are disposed on the ohmic contact layer, wherein the data line, the data pad, and the first link electrode are disposed on the first insulating layer, and wherein the first link electrode crosses the gate line, forming a channel within the active layer by etching a portion of the ohmic contact exposed between the source an

Abstract: A semiconductor device includes an oxide semiconductor thin film layer primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (101) orientation.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter of the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: In an organic electro-luminescent display, a pixel circuit is disposed in a unit pixel region defined on a substrate. A passivation layer covers the entire unit pixel region including the pixel circuit. An organic light emitting diode (“OLED”) including a transparent lower electrode formed on a portion of the passivation layer which does not overlap the pixel circuit, an OLED layer, and an upper electrode are sequentially formed on the passivation layer. The transparent lower electrode is a transparent anode of the OLED. A protective layer is formed of the same material as the transparent lower electrode and disposed on a portion of the passivation layer corresponding to the pixel circuit to cover and protect the pixel circuit.

Abstract: A thin film transistor and method of fabrication a thin film transistor and a pixel structure are provided. First, a gate is formed on the substrate. Then, a gate-isolating layer is formed on the substrate to cover the gate electrode. After that, a source/drain is formed on the gate-isolating layer and exposes a portion of the gate-isolating layer above the gate electrode. Then, a channel is formed on the portion of the gate-isolating layer above the gate. The source/drain layer is formed before forming the channel to prevent the channel from over etching as forming the source/drain layer. Therefore, the yields of manufacturing thin film transistor and pixel structure can be improved.

Abstract: There is provided a semiconductor device comprising an n-type and a p-type field effect transistors, meeting the conditions that in terms of a crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {100} plane substantially orthogonal to the {100} plane, and that in terms of a crystal orientation of the protruding semiconductor region constituting the p-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {110} plane substantially orthogonal to the {100} plane.

Abstract: One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein.

Abstract: The invention provides a semiconductor device which consumes less power in pending. The invention further provides a semiconductor device in which a gate electrode is provided over both sides of a semiconductor thin film which forms a transistor, a logic signal is applied to a first gate electrode, a threshold value control signal is applied to a second gate electrode, and a threshold value of a transistor which forms the semiconductor device is controlled by a potential of the second gate electrode, and a driving method thereof. Then, the invention provides a semiconductor device provided with a plurality of logic circuits formed of such a transistor with a back gate and a driving method thereof.

Abstract: A thin film transistor including a gate, a gate insulating layer, a channel layer, a spiral source and a spiral drain is provided. The gate insulating layer covers the gate. The channel layer is disposed on the gate insulating layer above the gate. The spiral source and the spiral drain are disposed on the channel layer above the gate. The spiral source and spiral drain are curled with each other. By the design of spiral source and spiral drain, the ratio of width/length (W/L) can be increased, and the Cgd is reduced as well.

Abstract: A thin film transistor (TFT) including a gate, a semiconductor layer, a source and a drain is provided. The gate has a control part, a connection part and a capacitance compensation part. The connection part is disposed between the control part and the capacitance compensation part for joining the two parts together. The semiconductor layer is disposed over the gate, the source and the drain are disposed on the semiconductor layer. An end of the drain overlaps the control part of the gate with a first region for composing a first parasitic capacitance; while another end of the drain overlaps the capacitance compensation part of the gate with a second region for composing a second parasitic capacitance. In a TFT array with the TFT, the sum of the first parasitic capacitance and the second parasitic capacitance is a constant.

Abstract: A pixel structure including a scan line, a data line, a first thin film transistor, a second thin film transistor, a first pixel electrode and a second pixel electrode, is described. The first thin film transistor is electrically connected to the scan line and the data line and has a first device width/length ratio. The second thin film transistor is also electrically connected to the scan line and the data line and has a second device width/length ratio. The first pixel electrode is electrically connected to the first thin film transistor while the second pixel electrode is electrically connected to the second thin film transistor.

Abstract: A co-planar thin film transistor, TFT (22), and a method of fabricating the same, in which an additional insulating layer is provided on the source contact (30) and the drain contact (32) and defined such that a first region (34) of the additional insulating layer occupies substantially the same area as the source contact (30) and a second region (36) of the additional insulating layer occupies substantially the same area as the drain contact (32). This tends to provide a reduction in the gate (62) to source capacitance, and the gate (62) to drain capacitance. In some geometries this can be achieved without any additional masks or defining steps.

Abstract: Provided is a liquid crystal display (LCD) device and a fabrication method thereof. An array substrate for the LCD includes a gate line formed on a substrate, and a gate electrode extending from the gate line; a data line intersected with the gate line, wherein the data line is configured with a gate insulating layer, a semiconductor layer and a data metal layer; a pixel electrode formed of a first transparent metal layer at a pixel which is defined by an intersection of the gate line and the data line; a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode by a predetermined distance to expose a channel; and a second transparent metal layer pattern formed on the data line, the source electrode and the drain electrode, wherein the second transparent metal layer connects the drain electrode and the pixel electrode to each other.

Abstract: The present invention relates to a thin film transistor substrate and a metal wiring method thereof, more particularly to a thin film transistor substrate comprising self-assembled monolayers between the substrate and the metal wiring, and a metal wiring thereof. Since a thin film transistor substrate of the present invention comprises three-dimensionally cross-linked self-assembled monolayers between the Si surface and the metal wiring, it has good adhesion ability and anti-diffusion ability.

Abstract: A thin film transistor array panel is provided, which includes: a plurality of gate lines formed on a substrate and including a plurality of oblique portions and a plurality of gate electrodes; a first insulating layer on the gate line; a semiconductor layer formed on the first insulating layer; a plurality of data lines formed at least on the semiconductor layer and intersecting the gate lines to defined trapezoidal pixel areas; a plurality of drain electrodes separated from the data lines; a second insulating layer formed at least on portions of the semiconductor layer that are not covered with the data lines and the drain electrodes; a plurality of pixel electrodes formed on the second insulating layer and connected to the drain electrodes, at least two of the pixel electrodes disposed in each pixel area; and a plurality of common electrodes formed on the second insulating layer, arranged alternate to the pixel electrodes and connected to the drain electrodes, each common electrode having an edge spaced ap

Abstract: The invention provides an electro-optical device in which a voltage drop due to the wiring resistance of a cathode is reduced and therefore steady image signals are transmitted such that erroneous image display, such as low contrast, is reduced or prevented. The invention also provides an electronic apparatus including such an electro-optical device. An electro-optical device includes red, green, and blue luminescent power-supply lines to apply currents to light-emitting elements arranged in an actual display region in a matrix; and a cathode line disposed between the light-emitting elements and a cathode. The cathode line has a width larger than a width of red, green, and blue luminescent power-supply lines.

Abstract: A gallium nitride-based semiconductor device has a p-type layer that is a gallium nitride compound semiconductor layer containing a p-type impurity and exhibiting p-type conduction. The p-type layer includes a top portion and an inner portion located under the top portion. The inner portion contains the p-type impurity element and, in combination therewith, hydrogen.

Abstract: An electronic device comprises a body including a single crystal region on a major surface of the body. The single crystal region has a hexagonal crystal lattice that is substantially lattice-matched to graphene, and a at least one epitaxial layer of graphene is disposed on the single crystal region. In a currently preferred embodiment, the single crystal region comprises multilayered hexagonal BN. A method of making such an electronic device comprises the steps of: (a) providing a body including a single crystal region on a major surface of the body. The single crystal region has a hexagonal crystal lattice that is substantially lattice-matched to graphene, and (b) epitaxially forming a at least one graphene layer on that region. In a currently preferred embodiment, step (a) further includes the steps of (a1) providing a single crystal substrate of graphite and (a2) epitaxially forming multilayered single crystal hexagonal BN on the substrate.

Abstract: A semiconductor device and a method of forming thereof has a base body has a field stopping layer, a drift layer, a current spreading layer, a body region, and a source contact region layered in the order on a substrate. A trench that reaches the field stopping layer or the substrate is provided. A gate electrode is provided in the upper half section in the trench. In a section deeper than the position of the gate electrode in the trench, an insulator is buried that has a normal value of insulation breakdown electric field strength equal to or greater than the value of the insulation breakdown electric field strength of the semiconductor material of the base body. This inhibits short circuit between a gate and a drain due to insulation breakdown of an insulator film at the bottom of the trench to realize a high breakdown voltage in a semiconductor device using a semiconductor material such as SiC.

Abstract: A semiconductor light emitting device including a transparent compound semiconductor substrate whose lattice constant is inconsistent with the compound semiconductor emitting the light and exhibiting high light output is obtained. A semiconductor light emitting device includes a GaP substrate, an active layer located above GaP substrate and including an n-type AlInGaP layer and a p-type AlInGaP layer, and an ELO layer located between GaP substrate and active layer and formed by epitaxial lateral growth.

Abstract: A MQW LED structure is provided herein, which contains a carrier supply layer joined to a side of the MQW light emitting layer to provide additional carriers for recombination and to avoid/reduce the use of impurity in the light emitting layer. The carrier supply layer contains multiple and interleaving well layers and barrier layers, each having a thickness of 5˜300 ?, with a total thickness of 1˜500 nm. The well layers and the barrier layers are both made of AlpInqGa1-p-qN (p, q?0, 0?p+q?1) compound semiconductor doped with Si or Ge, but with different compositions and with the barrier layers having a higher bandgap than that of the well layers. The carrier supply layer has an electron concentration of 1×1017˜5×1021/cm3.

Abstract: A nitride-based semiconductor light emitting device having an improved structure in which light extraction efficiency is improved and a method of manufacturing the same are provided. The nitride-based semiconductor light emitting device comprises an n-clad layer, an active layer, and a p-clad layer, which are sequentially stacked on a substrate, wherein the n-clad layer comprises a first clad layer, a second clad layer, and a light extraction layer interposed between the first clad layer and the second clad layer and composed of an array of a plurality of nano-posts, the light extraction layer diffracting or/and scattering light generated in the active layer.

Abstract: A light emitting element is provided, which comprises a pair of electrodes, a p-type semiconductor layer, and an n-type semiconductor layer. The p-type semiconductor layer and the n-type semiconductor layer are interposed between the pair of electrodes. The p-type semiconductor layer includes a first sulfide, and the n-type semiconductor layer includes a second sulfide. At least one of the p-type semiconductor layer and the n-type semiconductor layer includes a light emitting center.

Abstract: The present invention provides a method of manufacturing a Group III nitride substrate that has less variations in in-plane carrier concentration and includes crystals grown at a high growth rate.

Abstract: A light source having a substrate having first and second surfaces is disclosed. The substrate has first and second conducting traces on the first surface. A heat conducting metallic layer is attached to the second surface. First and second LEDs are disposed on the first surface, each LED having first and second contacts for powering that LED. The first contact is connected to a corresponding one of the first and second conducting traces. First and second conducting vias are in contact with the first and second LEDs, respectively. The first and second conducting vias extend from the first surface through the substrate and contact the heat conducting metallic layer. The second contacts of the first and second LEDs are electrically connected to the first and second conducting vias, respectively. The LEDs are powered by applying potentials between the external terminals and the heat-conducting layer.

Abstract: A facet extraction LED improved in light extraction efficiency and a manufacturing method thereof. A substrate is provided. A light emitting part includes an n-type semiconductor layer, an active layer and a p-type semiconductor layer sequentially stacked on the substrate. A p-electrode and an n-electrode are connected to the p-type semiconductor layer and the n-type semiconductor layer, respectively. The p- and n-electrodes are formed on the same side of the LED. The light emitting part is structured as a ring.

Abstract: Light-emitting systems, and related components, systems and methods are disclosed.

Abstract: A semiconductor light emitting element, manufacturing method. thereof, integrated semiconductor light emitting device, manufacturing method thereof, illuminating device, and manufacturing method thereof are provided. An n-type GaN layer is grown on a sapphire substrate, and a growth mask of SiN, for example, is formed thereon. On the n-type GaN layer exposed through an opening in the growth mask, a six-sided steeple-shaped n-type GaN layer is selectively grown, which has inclined crystal planes each composed of a plurality of crystal planes inclined from the major surface of the sapphire substrate by different angles of inclination to exhibit a convex plane as a whole. On the n-type GaN layer, an active layer and a p-type GaN layer are grown to make a light emitting element structure. Thereafter, a p-side electrode and an n-side electrode are formed.

Abstract: An illuminating device is provided for enhancing evenness of a brightness distribution or a chromaticity distribution of a light-emitting diode device. The illuminating device is made up of a substrate, one or more light-emitting diode devices located on the substrate, a reflector plate located on the substrate, and a transparent resin for sealing the light-emitting diode. The transparent resin has a concave portion above the light-emitting diode device. Part of a ray emitted from the light-emitting diode device is reflected on the concave portion and then irradiated through the transparent resin. This allows the light-emitting diode device to have a maximum value of a luminous intensity in the perpendicular direction to a predetermined inclined direction against the substrate.

Abstract: The invention provides a light-emitting device 10 including an light-emitting element 12 and a substrate 11 where the light-emitting element 12 is arranged, characterized in that a housing part 28 housing the light-emitting element 12 and having a shape that is tapered upward from the substrate 11 and a metal frame 15 surrounding the light-emitting element 12 and including the side face 28A of the housing part 28 made into an almost mirror-polished surface are provided on the substrate 11.

Abstract: A method of producing a semiconductor device, comprising: a first plasma processing step of processing a surface of a resin layer laid on a semiconductor element and containing silicon, with a first plasma generated from a gas containing oxygen and fluorine, thereby forming an oxide film; and an electrode pad forming step of forming an electrode pad of a metal on the oxide film.

Abstract: An LED illumination includes an insertable and removable LED illumination source having a feeder terminal on one surface of a substrate on which an LED has been mounted; a thermal conductor member, which contacts with a back surface of the substrate on which the LED is not present; at least one connector to be connected to the feeder terminal; and a lighting drive circuit to be electrically connected to the LED illumination source by way of the connector, wherein, in the LED illumination source, a center of the substrate is shifted from a center of a light outgoing region of the substrate where the mounted LED is located.

Abstract: The present invention provides a semiconductor device having a structure which is suitable for reduction in thickness and weight. The semiconductor device 1 comprises a housing 12 which has the recess 24 in the front surface 14, the pair of lead electrodes 20 which have the distal ends 34 exposed in the recess 24, protrude from the external surface of the housing 12 and are bent along the bottom surface 16 of the housing 12, and a semiconductor element 36 which is housed in the recess 24 and is electrically connected to the pair of lead electrodes 20. The housing 12 has the grooves 30 which are formed on the pair of side surfaces 18 which adjoin the front surface 14 and the bottom surface 16 on the right and left sides so as to penetrate the housing 12 from the top surface 28 toward the bottom surface 16 of the housing 12. The grooves 30 preferably have width substantially equal to the thickness of the lead electrode 20.

Abstract: An LED unit (20) having increased light output. The LED unit (20) includes a submount substrate (22) having a cavity (24). An LED chip (30) is electrically mounted within the cavity (24) and a phosphor layer (34) is deposited in the cavity (24) that converts blue light from the LED chip (30) into white light suitable for a vehicle headlight (10). The walls of the cavity (24) are metalized (40) to increase the light output intensity. In one embodiment, a clear protective layer (46) is deposited in the cavity (24) over the phosphor layer (34).

Abstract: A wafer level package for image sensor components includes an image sensor chip and several metal pillars. Several vias formed in the image sensor chip are aligned with several bonding pads. The metal pillars are formed in the vias. First ends of the metal pillars are bonded to the bonding pads. Second ends of the metal pillars protrude from a back surface of the image sensor chip. The length of the metal pillars is greater than the thickness of the image sensor chip. The image sensor chip is mounted to a printed circuit board through the metal pillars formed in the vias instead of wire bonding or redistribution line (RDL) process. There is no need to dispensing underfil between the image sensor chip and the printed circuit board to protect the metal pillars.

Abstract: A composite growth-assisting substrate 10 is formed by epitaxially growing a separation-assisting compound semiconductor layer 10k composed of a non-GaAs III-V compound semiconductor single crystal, and then a sub-substrate 10e composed of a GaAs single crystal in this order, on a first main surface of a substrate bulk 10m composed of a GaAs single crystal. The sub-substrate portion 10e is then separated from the composite growth-assisting substrate 10, so as to be left as a residual substrate portion 1 on a second main surface of the main compound semiconductor layer 40, and a portion of the residual substrate portion 1 is cut off to thereby form a cut-off portion 1j having a bottom surface used as a light extraction surface. By this configuration, the light emitting device is provided as allowing effective use of the GaAs substrate, and increasing the light extraction efficiency.

Abstract: Disclosed are a nitride semiconductor light emitting device and a method for manufacturing the same. The nitride semiconductor light emitting device includes a first nitride layer, an active layer including at least one delta-doping layer on the first nitride layer through delta-doping, and a second nitride layer on the active layer.

Abstract: The disclosure relates to organic light emitting diode devices for area illumination. The devices include an organic light emitting diode lamp responsive to electrical power for emitting light. A controller regulates the light output from the organic light emitting diode lamp using a range selection switch for varying a power range, and a power switch responsive to the range selection switch to provide power to organic light emitting diode.

Abstract: A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer.

Abstract: A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.

Abstract: A semiconductor device and method of forming the same. The semiconductor device includes an epitaxially grown and conductive buffer layer having a contact covering a substantial portion of a bottom surface thereof and a lateral channel above the buffer layer. The semiconductor device also includes another contact above the lateral channel and an interconnect that connects the lateral channel to the buffer layer, operable to provide a low resistance coupling between the contact and the lateral channel.

Abstract: A HEMT-type field-effect semiconductor device has a main semiconductor region formed on a silicon substrate. The main semiconductor region is a lamination of a buffer layer on the substrate, an electron transit layer on the buffer layer, and an electron supply layer on the electron transit layer. A source and a drain overlie the electron supply layer. A carrier storage layer overlies the electron supply layer via an insulator, and a gate overlies the carrier storage layer via another insulator. Upon application of an initializer voltage to the gate, the carrier storage layer has stored therein a sufficient amount of carriers to hold the device off even without voltage application to the gate. An initializer circuit is also disclosed whereby the device is initialized automatically for normally-off operation.

Abstract: This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Abstract: A light sensing panel includes a scan line transmitting a scan signal, a power source line transmitting a bias voltage, a readout line transmitting a light sensing signal and a light sensing device. The light sensing device includes a control electrode that is electrically connected to the scan line to receive the scan signal, a first current electrode that is electrically connected to the power source line to receive the bias voltage, and a second current electrode that is electrically connected to the readout line to apply a light sensing signal to the readout line when the light sensing signal senses an external light. The light sensing panel requires only one thin film transistor in order to detect a position wherein the external light is incident. Therefore, electrical coupling between devices is reduced and aperture ratio is increased, thereby enhancing a display quality.

Abstract: A semiconductor device includes first and second unit circuits. Each first unit circuit has first transistors connected in series, wherein each of the first transistors includes a first gate structure having a pitch. Each second unit circuit has second transistors connected in series, wherein each of the second transistors includes a second gate structure having the pitch. A third transistor and a fourth transistor electrically isolate each of the first and second unit circuits, respectively. An insulation layer covers the first through the fourth transistors. Plugs in the insulation layer are connected to a first gate structure, a second gate structure, a first source region, a first drain region, a second source region or a second drain region. A wiring is connected to the plugs.

Abstract: An imager apparatus and associated starting material are provided. In one embodiment, an imager is provided including a silicon layer of a first conductivity type acting as a junction anode. Such silicon layer is adapted to convert light to photoelectrons. Also included is a semiconductor well of a second conductivity type formed in the silicon layer for acting as a junction cathode. Still yet, a barrier is formed adjacent to the semiconductor well. In another embodiment, a starting material is provided including a first silicon layer and an oxide layer disposed adjacent to the first silocon layer. Also included is a second silicon layer disposed adjacent to the oxide layer opposite the first silicon layer. Such second silicon layer is further equipped with an associated passivation layer and/or barrier.

Abstract: A two-branch outputting solid-state imaging device is provided and includes: two output amplifiers including a first output amplifier and a second output amplifier, each outputting a voltage signal in accordance with the signal charge transferred toward the output end through the charge transfer path; and a branching part that distributes the signal charge transferred through the charge transfer path toward the first output amplifier in a case the signal charge corresponds to the first signal charge, toward the second output amplifier in a case the signal charge corresponds to the second signal charge, and toward the first output amplifier in a case the signal charge corresponds to the third signal charge.