Abstract: The pixel for use in an image sensor comprises a low-doped semiconductor substrate (A). On the substrate (A), an arrangement of a plurality of floating areas e.g., floating gates (FG2-FG6), is provided. Neighboring floating gates are electrically isolated from each other yet capacitively coupled to each other. By applying a voltage (V2-V1) to two contact areas (FG1, FG7), a lateral steplike electric field is generated. Photogenerated charge carriers move along the electric-field lines to the point of highest potential energy, where a floating diffusion (D) accumulate the photocharges. The charges accumulated in the various pixels are sequentially read out with a suitable circuit known from image-sensor literature, such as a source follower or a charge amplifier with row and column select mechanisms. The pixel of offers at the same time a large sensing area, a high photocharge-detection sensitivity and a high response speed without any static current consumption.

Abstract: A process and apparatus for a high-k gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extend beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.

Abstract: A solid-state imaging device includes a two-dimensional array of photosensor sections on a semiconductor substrate, and a vertical transfer section including two-layer vertical transfer electrodes. The photosensor sections store signal charges generated by photoelectric conversion. The vertical transfer section reads signal charges from the photosensor sections and vertically transfers the read signal charges. The two-layer vertical transfer electrodes have first transfer electrode layers and second transfer electrode layers, and the first transfer electrode layers serve as read electrodes for reading the signal charges from the photosensor sections. The first transfer electrode layers have a larger electrode width with respect to the photosensor sections than the second transfer electrode layers.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

Abstract: The normally on transistor comprises a source, a drain and a channel. The source, drain and channel materials are chosen such that, for a NMOS type transistor, the electronic affinity of the drain material is lower than the electronic affinity of the channel material and the electronic affinity of the source material is higher than the electronic affinity of the channel material. Moreover, the materials are selected such that, for a PMOS type transistor, the upper level of the valence band of the drain material is higher than the upper level of the valence band of the channel material and the upper level of the valence band of the source material is lower than the upper level of the valence band of the channel material.

Abstract: Example embodiments relate to a unipolar carbon nanotube having a carrier-trapping material and a unipolar field effect transistor having the unipolar carbon nanotube. The carrier-trapping material, which is sealed in the carbon nanotube, may readily transform an ambipolar characteristic of the carbon nanotube into a unipolar characteristic by doping the carbon nanotube. Also, p-type and n-type carbon nanotubes and field effect transistors may be realized according to the carrier-trapping material.

Abstract: Example embodiments may provide memory devices having a charge trap layer which includes a hole trap and an electron trap. The memory device may generate a relatively large flat band voltage gap according to an applied bias voltage. Accordingly, a stable multilevel cell may be realized.

Abstract: Methods for forming a wire from silicon or other semiconductor material are disclosed. Also disclosed are various devices including such a semiconductor wire. According to one embodiment, a wire is spaced apart from an underlying substrate, and the wire extends between a first end and an opposing second end, each of the first and second ends being affixed to the substrate. Other embodiments are described and claimed.

Abstract: A source region and drain region are formed in a surface region of a first semiconductor region. Moreover, a second semiconductor region connected to the drain region is formed in the surface region of the first semiconductor region. A third semiconductor region is formed in the first semiconductor region under the second semiconductor region, connected to the second semiconductor region, and accumulates signal charges in accordance with an incident light. A fourth semiconductor region is formed in the surface region of the first semiconductor region between the drain region and source region. Moreover, these source region, drain region, second semiconductor region, and third semiconductor region constitute a pixel, and different voltages are supplied to the drain region in an accumulation period of the signal charges in the pixel, signal readout period, and discharge period of the signal charges.

Abstract: A photodetector including a photodiode formed in a semiconductor substrate and a waveguide element formed of a block of a high-index material extending above the photodiode in a thick layer of a dielectric superposed to the substrate, the thick layer being at least as a majority formed of silicon oxide and the block being formed of a polymer of the general formula R1R2R3SiOSiR1R2R3 where R1, R2, and R3 are any carbonaceous or metal substituents and where one of R1, R2, or R3 is a carbonaceous substituent having at least four carbon atoms and/or at least one oxygen atom.

Abstract: A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface.

Abstract: A first hydrogen barrier film and an intermediate layer are formed on an interlayer dielectric film. A ferroelectric capacitor is formed on the intermediate layer, and a second hydrogen barrier film is formed over the entire surface including on the upper surface and side surfaces of the ferroelectric capacitor and on the intermediate layer. Then, the second hydrogen barrier film and the intermediate layer are removed while leaving at least portions on the upper surface and side surfaces of the ferroelectric capacitor. Then, a third hydrogen barrier film is formed on the second hydrogen barrier film, on side surfaces of the second hydrogen barrier film and the intermediate layer, and on the first hydrogen barrier film.

Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

Abstract: A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.

Abstract: A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell stud can be employed in a dynamic random-access memory device. An electrical system is also disclosed that includes the storage cell stud.

Abstract: A three-dimensional capacitor structure has a first conductive layer, a second conductive layer disposed above the first conductive layer, and a plug layer disposed therebetween. The first conductive layer includes a plurality of grid units arranged in a matrix, where in odd rows of the matrix, a first conductive grid is located in each odd column, and a first circular hole is located in each even column. Additionally, a first conductive island is located within each first circular hole. The pattern of the second conductive grids, the second circular holes, and the second conductive island of the second conductive layer is mismatched with that of the first conductive layer. The plug layer has a plurality of plugs disposed in between each first conductive island and each second conductive grid, and in between each first conductive grid and each second conductive island.

Abstract: A capacitance cell 21 is wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers T1 and T2 orthogonally to opposed lateral end faces out of lateral end faces X1, X2, Y1, and Y2 that section the cell in a plane direction. Contact surfaces of the electrode surfaces T1 and T2 with the lateral end faces are second connection terminals T12 and T22. For longitudinal pathways, first and second via contact layers V1 and V2are connected. The first via contact layer V1 interconnects the wiring layers Ma and Mb. The second via contact layer V2 is connected to a wiring layer located outside beyond an upper or lower end face Z2, Z1. The second via contact layer V2 is connected to a first connection terminal T11, T21 located on the upper or lower end faces Z2, Z1. The capacitance cells 21 are linked via the first and second connection terminals so that a capacitance element having a free shape is formed.

Abstract: In a thin film transistor substrate, a method of manufacturing the same, and a display apparatus having the same, a thin film transistor, a gate member, and a storage member are formed on an insulating substrate. The gate member has a gate line and a gate electrode electrically connected to the gate line, and the storage member has a storage line, a first storage electrode, and a second storage electrode. A data member is formed on an active layer. The data member includes a data line crossing the gate line, a third storage electrode overlapped with the first storage electrode and a fourth storage electrode overlapped with the second storage electrode. Thus, a capacitance variation of a storage capacitor may be prevented, thereby improving display quality of a display apparatus.

Abstract: The disclosure concerns a semiconductor memory device including an insulating film; a semiconductor layer provided on the insulating film; a source layer and a drain layer formed on the semiconductor layer; a body region provided between the source layer and the drain layer, the body region being in an electrically floating state, accumulating or emitting charges for storing data, and including a first body part and a second body part, the first body part being smaller than the second body part in a thickness measured in a direction perpendicular to a surface of the insulating film; a gate insulating film provided on the first body part and the second body part; and a gate electrode provided on the gate insulating film.

Abstract: A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

Abstract: The invention relates to integrated circuits, a memory device, a method of producing an integrated circuit, a method of producing a memory device, and a memory module.

Abstract: According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate belo

Abstract: In a nonvolatile semiconductor memory device, a semiconductor substrate has trenches formed to extend in parallel. A first electrode formed on the semiconductor substrate through an insulating film in each of the trenches, and a second electrode is formed on the first electrodes and the semiconductor substrate through the insulating film. A diffusion layer is formed in a predetermined depth of the semiconductor substrate in association with each of the trenches, and a trap film as a part of the insulating film configured to trap electric charge. A channel region is formed between adjacent two of the diffusion layers without any diffusion layer.

Abstract: A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride storage regions are isolated from each other by a depression in the control gate. In a vertical embodiment, the split nitride storage regions are separated by an oxide pillar. The cell is programmed by creating a positive charge on the nitride storage regions and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the nitride storage region that is adjacent to the pinched off channel region.

Abstract: Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.

Abstract: A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

Abstract: A superjunction power semiconductor device which includes spaced drift regions each extending from the bottom of a respective gate trench to the substrate of the device.

Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

Abstract: A memory cell with a vertical transistor has a semiconductor silicon substrate with a deep trench, in which the deep trench has a first sidewall region and a second sidewall region. A first insulating layer is formed overlying the first sidewall region. A second insulating layer is formed overlying the second sidewall region, in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer. A gate electrode layer is sandwiched between the first insulating layer and the second insulating layer. A buried strap out-diffusion region is formed in the substrate adjacent to the second sidewall region, in which the buried strap out-diffusion region is located near the lower portion of the second insulating layer.

Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Abstract: The size of BVDSS distribution is controlled by the active manipulation of the distribution of silicon parameters across a wafer to offset opposing effects inherent in the wafer fabrication process. Thus, the resistivity of the silicon wafer is increased toward the edge of the wafer. This offsets the drop-off of BVDSS across the wafer caused in wafer fabrication by deeper trenches at the edge of the wafer. This causes a flatter BVDSS profile across the wafer and significantly reduced BV distribution over the wafer.

Abstract: A non-volatile memory cell and method of fabrication are provided. The non-volatile memory cell includes a substrate of a first conductivity type, a first dopant region of a second conductivity type in the substrate, a second dopant region of the first conductivity type in the first dopant region, a first isolation region overlaying a portion of the substrate, the first dopant region, and the second dopant region, a second isolation region overlaying another portion of the substrate, the first dopant region, and the second dopant region, a contact region of the first conductivity type in the second dopant region, the contact region extending between the first isolation region and the second isolation region and being more heavily doped than the second dopant region, a gate dielectric atop the first isolation region and a portion of the contact region, and a gate conductor atop the gate dielectric.

Abstract: A metal source power transistor device and method of manufacture is provided, wherein the metal source power transistor having a source which is comprised of metal and which forms a Schottky barrier with the body region and channel region of the transistor. The metal source power transistor is unconditionally immune from parasitic bipolar action and, therefore, the effects of snap-back and latch-up, without the need for a body contact. The ability to allow the body to float in the metal source power transistor reduces the process complexity and allows for more compact device layout.

Abstract: The present disclosure provides an example of a semiconductor device. In addition, a method for fabricating a semiconductor device is outlined. The semiconductor device may be fabricated by providing a semiconductor substrate, forming a gate over the substrate, forming diffusion barrier ion regions, forming halo regions, forming a source, and forming a drain.

Abstract: Provided is a high-performance n-type Schottky barrier tunneling transistor with low Schottky barrier for electrons due to a Schottky junction formed on a Si (111) surface created through anisotropic etching. The Schottky barrier tunneling transistor includes: a silicon on insulator (SOI) substrate; a source and a drain formed on the SOI substrate; a channel formed between the source and the drain; a gate insulating layer and a gate electrode sequentially formed on the channel; and a sidewall insulating layer formed on both sidewalls of the gate insulating layer and the gate electrode, wherein an interface between the source/drain and the channel is on a Si (111) in the channel, and the source and drain consists of metal silicide through silicidation with a predetermined metal and forms a Schottky junction with the silicon channel.

Abstract: A method of fabricating a display apparatus includes depositing a first layer on a substrate while a mask is disposed at a first distance from the substrate, and forming a second layer on the substrate while the mask is disposed at a second distance larger than the first distance from the substrate after forming the first layer. Thus, the present invention provides a method of fabricating a display apparatus, in which a single mask is used in forming an electron injection layer and a common electrode.

Abstract: A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.

Abstract: The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semiconductor film to the semiconductor film containing a rare gas element by a heat treatment. Furthermore, a first impurity region and a second impurity region formed in a semiconductor layer of a first n-channel TFT are provided outside a gate electrode. A third impurity region formed in a semiconductor layer of a second n-channel TFT is provided so as to be partially overlapped with a gate electrode. A third impurity region is provided outside a gate electrode. A fourth impurity region formed in a semiconductor layer of a p-channel TFT is provided so as to be partially overlapped with a gate electrode. A fifth impurity region is provided outside a gate electrode.

Abstract: A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.

Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a substrate with a pad, an internal circuitry region, and a protection resistance formed on the substrate. The pad is connected to a first electrode of the protection resistance by wiring, the internal circuitry region is connected to a second electrode of the protection resistance by wiring, and the protection resistance protects the internal circuitry region from electrostatic discharging. The semiconductor apparatus is characterized in that the pad is placed between the protection resistance and the internal circuitry region.

Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

Abstract: A manufacturing method of a semiconductor device with a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film, a gate electrode, a source/drain layer, and a germanide layer. The gate insulating film is formed on the semiconductor substrate. The gate electrode is formed on the gate insulating film. The source/drain layer is formed on both sides of the gate electrode, contains silicon germanium, and has a germanium layer in a surface layer portion. The germanide layer is formed on the germanium layer of the source/drain layer.

Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device.

Abstract: Disclosed are embodiments of a structure that comprises a first device, having multiple FETs, and a second device, having at least one FET. Sections of a first portion of a semiconductor layer below the first device are doped and contacted to form back gates. A second portion of the semiconductor layer below the second device remains un-doped and un-contacted and, thus, functions as an insulator. Despite the performance degradation of the first device due to back gate capacitance, the back gates result in a net gain for devices such as, SRAM cells, which require precise Vt control. Contrarily, despite marginal Vt control in the second device due to the absence of back gates, the lack of capacitance loading and the added insulation result in a net gain for high performance devices such as, logic circuits.

Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.

Abstract: In a semiconductor device 10, an electrode terminal 18 of a semiconductor element 14 embedded in an insulating layer 12 formed by a resin forming a substrate and a land portion 20 forming an external connecting terminal are electrically connected to each other through a wiring pattern 22 formed on the insulating layer 12. The wiring pattern 22 including the land portion 20 is formed by a plating metal 26. A metallic wire 24 having one of ends connected to the electrode terminal 18 is provided in the plating metal 26 along the wiring pattern 22.

Abstract: The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOx) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the layer provides the functionality of a thinner silicon dioxide layer, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.

Abstract: A semiconductor device is provided with a stressed channel region, where the stress film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surrounds the channel region, and may apply stress from all sides of the channel. Consequently, the stress film better surrounds the channel region of the semiconductor device and can apply more stress in the channel region.