Abstract: An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.

Abstract: Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the channel region. The first insulator is thicker than the gate oxide. The floating gate is electrically insulated from other structures. Also, a second insulator is positioned between a programming gate and the floating gate. Voltage in the logic gate causes the transistor to switch on and off, while stored charge in the floating gate adjusts the threshold voltage of the transistor. The transistor can comprise a fin-type field effect transistor (FinFET), where the channel region comprises the middle portion of a fin structure and the source and drain regions comprise end portions of the fin structure.

Abstract: A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.

Abstract: A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.

Abstract: A non-volatile memory device including a control gate pattern having a tunnel insulation pattern, a trap-insulation pattern, a blocking insulation pattern and a control gate electrode, which are stacked on a semiconductor substrate. A selection gate pattern is disposed on the semiconductor substrate at one side of the control gate pattern. A gate insulation pattern is interposed between the selection gate electrode and the semiconductor substrate, and between the selection gate electrode and the control gate pattern. A cell channel region includes a first channel region defined in the semiconductor substrate under the selection gate electrode and a second channel region defined in the semiconductor substrate under the control gate electrode.

Abstract: A method of manufacturing a semiconductor device provided with a MOS field effect transistor having a channel region of a first conduction type formed in a surface layer portion of a semiconductor substrate, a source region of a second conduction type formed on a rim portion of a trench made to penetrate through the channel region, and a base region of the first conduction type formed in the surface layer portion of the semiconductor substrate adjacently to the source region. The method includes: a step of forming a mask layer having a base-region forming opening corresponding to the base region and a trench forming opening corresponding to the trench on the semiconductor substrate in which the channel region is formed; a base-region forming step of introducing impurities through the base-region forming opening; a trench forming step of forming the trench through the trench forming opening; and a step of forming a gate insulation film on an inner wall surface of the trench.

Abstract: A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gate formed on top of the fin structure. A gate around MOSFET includes multiple fins, a first sidewall gate structure formed adjacent one of the fins, a second sidewall gate structure formed adjacent another one of the fins, a top gate structure formed on one or more of the fins, and a bottom gate structure formed under one or more of the fins.

Abstract: There is provided a power MISFET which includes a semiconductor region of a first conductivity, a semiconductor base region of a second conductivity, a pillar region, a first major electrode region of a first conductivity on the base region, a second major electrode region connected with at least the semiconductor region and a part of the pillar region, a control electrode and an electrode pad connected with the control electrode. The pillar region including a first region of a first conductivity type and a second region of a second conductivity type is not formed under the electrode pad. Also, a method for manufacturing a MISFET is provided.

Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.

Abstract: A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well region provided in the support substrate under the MOSFET.

Abstract: It is an object of the present invention to provide a semiconductor display device using a protective circuit in which dielectric breakdown is prevented more effectively. In the invention, in the cases that a first interlayer insulating film is formed covering a TFT used for a protective circuit and a second interlayer insulating film, which is an insulating coating film, is formed covering a wiring formed over the first interlayer insulating film, a wiring for connecting the TFT to other semiconductor elements is formed so as to be in contact with the surface of the second interlayer insulating film so as to secure a path discharging charge accumulated in the surface of the second interlayer insulating film. Note that the TFT used for the protective diode is a so-called diode-connected TFT in which either of the first terminal or the second terminal is connected to a gate electrode.

Abstract: A non-volatile memory device includes a fin body protruded from a semiconductor substrate. The fin body has first and second side surfaces opposite to each other. An inner dielectric layer pattern is formed on an upper surface, and the first and second side surfaces of the fin body. A floating gate electrode is formed on the inner dielectric layer pattern. The floating gate electrode has an uneven upper surface. An outer dielectric layer is formed on the floating gate electrode. A control gate electrode is formed on the outer dielectric layer.

Abstract: A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the first interlayer insulating film interposed therebetween. The second interlayer insulating film has a lower relative permeability than the first interlayer insulating film.

Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately 5.16 eV to 7.8 eV. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.

Abstract: A micromechanical component includes: a substrate; a micromechanical functional plane provided on the substrate; a covering plane provided on the micromechanical functional plane; and a printed circuit trace plane provided on the covering plane. The covering plane includes a monocrystalline region which is epitaxially grown on an underlying monocrystalline region, and the covering plane includes a polycrystalline region which is epitaxially grown on an underlying polycrystalline starting layer at the same time.

Abstract: The invention generally relates to the field of spintronics, a branch of electronics using the magnetic spin properties of electrons. More particularly, the invention relates to the field of spin-valve transistors which can be used in numerous fields of electronics. The invention aims to propose an original arrangement for producing high-level and high-contrast collector currents simultaneously. The inventive spintronics transistor comprises a semiconductor emitter, a base fanning a spin valve and a metallic collector separated from the base by an insulating deposit. The emitter/base interface constitutes a Schottky barrier and the base/collector interface constitutes a tunnel-effect barrier.

Abstract: A semiconductor substrate of a solid state imaging device is connected to a cover glass, and then a backgrind is performed so as to make the thickness smaller. On a first face of the semiconductor substrate is formed plural units which is constructed of image sensors and plural contact terminals. At positions of the contact terminals, plural through-holes are formed on the bottom side of the semiconductor substrate, and the contact terminals appear on a second surface of the semiconductor substrate. On an interconnection circuit pattern of the assembly substrate are formed stud bumps. When the semiconductor substrate is assembled onto the assembly substrate, the stud bumps enter into the through-holes to contact to the contact terminals. Thus the interconnection circuit pattern is electrically connected to the image sensors.

Abstract: In a semiconductor photodetector 1 according to the present invention, flat surfaces of three steps with different heights are formed in a top surface portion of a semi-insulating GaAs substrate 2. An n-type GaAs layer 3, an i-type GaAs layer 4, and a p-type GaAs layer 5 are successively deposited on the lower step surface formed in a central region of the semi-insulating GaAs substrate 2. Furthermore, a p-side ohmic electrode 6 is provided astride and above a flat surface formed by the p-type GaAs layer 5 and the upper step surface of the semi-insulating GaAs substrate 2, and an n-side ohmic electrode 7 is provided astride and above a flat surface formed by the n-type GaAs layer 3 and the middle step surface of the semi-insulating GaAs substrate 2.

Abstract: A fast switching diode includes an n? layer having an upper surface and a lower surface and a first edge and a second edge, the second edge provided on an opposing side of the first edge. A converted region is provided proximate the upper surface of the n? layer. The converted region includes platinum and has a first depth. The converted region has a platinum concentration that is substantially greater than an n-type dopant concentration in the converted region. First and second n+ regions are provided proximate the first and second edges of the n? layer, respectively, and extend from the upper surface of the n? layer to second and third depths, respectively. Each of the second and third depths is greater than the first depth to reduce leakage current. A first electrode is provided proximate the upper surface of the n? layer. A second electrode is provided proximate the lower surface of the n? layer.

Abstract: A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolation material arranged on the second layer. The pattern of voids has a fourth layer of a third isolation material which closes off at least some of the spaces and cannot be deposited on the first isolation material. The fourth layer is arranged on the third layer and has a second layer surface. Spaces that are not closed off by means of the fourth layer are filled with electrically conductive material. In the method for producing a pattern of voids in an integrated circuit, a second layer of a first isolation material is applied to a first layer surface of a first layer. A third layer of a second isolation material is applied to the second layer, the third layer acquiring a second layer surface which is arranged parallel to the first layer surface.

Abstract: A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

Abstract: Methods of forming a pattern of filled dielectric material on a substrate by thermal transfer processes are disclosed comprising exposing to heat a thermally imageable donor element comprising a substrate and a transfer layer of dielectric material. The exposure pattern is the image of the desired pattern to be formed on the substrate, such that portions of the layer of dielectric material are transferred onto the substrate where the electronic device is being formed. The filled dielectric material can be patterned onto a gate electrode of a thin film transistor. The pattern dielectric material may also form an insulating layer for interconnects. Donor elements for use in the process are also disclosed. Methods for forming thin film transistors and donor elements for use in the thermal transfer processes are also disclosed.

Abstract: In one embodiment, an optoelectronic device is provided having a pin photo diode including a semi-insulating substrate or layer, with a patterned implant region of a first dopant type. The pin photo diode includes an upper layer having semiconductor material with a second dopant type. An intermediate layer is provided having a substantially intrinsic semiconductor material. An upper layer contact is provided having a portion with a generally circular interior facing edge. The implant region has a first portion having an outer periphery substantially nonoverlapping with the interior facing edge of the upper layer contact. The implant region includes a contact portion located beyond the upper layer contact. A connecting portion couples the first portion and the contact portion of the implant region. In one embodiment, the device includes a heterojunction bipolar transistor coupled to the pin photo diode.

Abstract: A heat spreader (20) is added to a package to enhance thermal and advantageously electrical performance. In manufacture, a heat spreader precursor (24) is advantageously placed over a group of dies and secured after bonding (e.g., wire or tape bonding or flip-chip bonding) and before matrix/block mold. For example, a package strip (10) may consist of a row (linear array) of groups of die attach areas (e.g. in a rectangular array of four). The heat spreader precursor (20) may accommodate one such group or multiple groups along the package strip (10). The package strip (10) may then be singulated to form the individual packages. Each singulated package includes a die (14), its associated substrate 16 (e.g., either a lead frame or interposer type substrate) and a portion of the heat spreader precursor (24) as a heat spreader (20).

Abstract: A packaging assembly (100) includes a plurality of dissimilar die (102, 104, 106) bonded to a base board (110) and ground coupled to a heat sink (108) through an opening (132). A mating board (112) is coupled to the base board (110) to provide separate surface mountable contacts (148-158, 166) with which to independently bias each die (102, 104, 106) while the heat sink (108) provides thermal dissipation for the die. Assembly (100) provides a surface mountable package well suited to multiband applications.

Abstract: Disclosed herein is a flip-chip type nitride semiconductor light emitting diode. The light emitting diode comprises an n-type nitride semiconductor layer formed on a transparent substrate and having a substantially rectangular upper surface, an n-side electrode which comprises at least one bonding pad adjacent to at least one corner of the upper surface of the n-type nitride semiconductor layer, extended electrodes formed in a band from the bonding pad along four sides of the upper surface of the n-type nitride semiconductor layer and one or more fingers extended in a diagonal direction of the upper surface from the bonding pad and/or the extended electrodes, an active layer and a p-type nitride semiconductor layer sequentially stacked on a region of the n-type nitride semiconductor layer where the n-side electrode is not formed, and a highly reflective ohmic contact layer formed on the p-type nitride semiconductor layer.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is received. A heat spreader has a first surface and a second surface. The first heat spreader surface is attached to the second substrate surface. A plurality of solder balls are attached to the second substrate surface outside an outer dimensional profile of the heat spreader. The second heat spreader surface is configured to be coupled to a printed circuit board (PCB).

Abstract: A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprises forming a metal seal on the substrate proximate a perimeter of the MEMS device using a method such as photolithography. The metal seal is formed on the substrate while the MEMS device retains a sacrificial layer between conductive members of MEMS elements, and the sacrificial layer is removed after formation of the seal and prior to attachment of a backplane.

Abstract: A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices is then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are connected to traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The input/output leads provide means for connecting the housing with the electronic device or system into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and prevents moisture or other contaminants which may impede the proper functionality of the die from entering the housing.

Abstract: Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a microfeature device having a plurality of device contacts, and a conductive structure electrically connected to the contacts. The conductive structure can have first and second package contacts accessible for electrical coupling to at least one device external to the package, with the first package contacts accessible from a first direction and the second package contacts configured to receive solder balls and accessible from a second direction opposite the first. An encapsulant can be disposed adjacent to the microfeature device and the conductive structure and can have apertures aligned with the second package contacts to contain solder balls carried by the second package contacts.

Abstract: A system and method for electrically and thermally coupling adjacent IC packages to one another in a stacked configuration is provided. A flex circuit is inserted in part between ICs to be stacked and provides a connective field that provides plural contact areas that connect to respective leads of the ICs. Thus, the flex does not require discrete leads which must be individually aligned with the individual leads of the constituent ICs employed in the stack. The principle may be employed to aggregate two or more contact areas for respective connection to leads of constituent ICs but is most profitably employed with a continuous connective field that provides contact areas for many leads of the ICs.

Abstract: Solder balls may be arranged in hexagonal array on an integrated circuit package. The hexagonal array may increase the solder ball density, reducing solder ball fatigue. In some embodiments, the hexagonal array may be utilized under the die shadow and an orthogonal array may be used outbound thereof.

Abstract: The invention provides a semiconductor chip manufacturing method, including a step of forming a front-surface-side concave portion in a semiconductor substrate having a front surface and a rear surface, a functional device being formed on the front surface, the front-surface-side concave portion being formed in the front surface and having a predetermined depth smaller than a thickness of the semiconductor substrate; a dummy plug forming step of supplying nonmetallic material into the front-surface-side concave portion and embedding a dummy plug made of the nonmetallic material; a thinning step of removing a part of the rear surface of the substrate and thinning the semiconductor substrate so that the thickness of the semiconductor substrate becomes smaller than the depth of the front-surface-side concave portion and so that the front-surface-side concave portion is formed into a through-hole; a dummy plug removing step of removing the dummy plug; and a step of supplying metallic material into the through-hol

Abstract: There is provided a semiconductor device including a semiconductor chip which includes a semiconductor substrate and a multilayer interconnection structure formed thereon, the multilayer interconnection structure including an interlayer insulating film smaller in relative dielectric constant than an SiO2 film, an encapsulating resin layer which covers a major surface of the semiconductor chip on a side of the multilayer interconnection structure and covers a side surface of the semiconductor chip, and a stress relaxing resin layer which is interposed between the semiconductor chip and the encapsulating resin layer, covers at least a part of an edge of the semiconductor chip on the side of the multilayer interconnection structure, and is smaller in Young's modulus than the encapsulating resin layer.

Abstract: Heat dissipation apparatus applies to a package device on a substrate. The package device has an upper surface, a bottom surface, and a sidewall between the upper and bottom surfaces, in which the bottom surface thermally contacts the substrate through multitudes of conductive bumps. For dissipating heat from the bottom surface, the heat dissipation apparatus includes a first heat-dissipating structure contacting a portion of the bottom surface and a second heat-dissipating structure on the upper surface. With the surrounding association of the first and the second heat-dissipating structures, these structures release heats from the sidewall of the die. Such a heat dissipation apparatus is capable of discharging heat at three dimensions, preventing the conductive bumps from collapsing, and enhancing reliability.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is received. A heat spreader has a first surface and a second surface. The first heat spreader surface is attached to the second substrate surface. A plurality of solder balls are attached to the second substrate surface outside an outer dimensional profile of the heat spreader. The second heat spreader surface is configured to be coupled to a printed circuit board (PCB).

Abstract: A technique for improving the thermal power dissipation of an integrated circuit includes reducing the thermal resistivity of the integrated circuit by increasing heat transfer in vertical and/or lateral directions. These results are achieved by increasing the surface area of the backside and/or the surface area of the lateral sides of the integrated circuit die. In some embodiments of the invention, an integrated circuit includes circuit elements formed closer to a first surface of a semiconductor substrate than to a second surface of the semiconductor substrate. The semiconductor substrate has a varying profile that substantially increases the surface area of a thermal interface formed on the second surface as compared to the second surface being substantially planar. A maximum depth of the profile is less than the thickness of the semiconductor substrate.

Abstract: A semiconductor module includes a supporting substrate having a connecting section on a first major surface thereof. A first semiconductor chip includes a first MIS transistor a source of which is formed on the bottom thereof. A second semiconductor chip includes a second MIS transistor a drain of which is formed on the bottom thereof. The first and second semiconductor chips are on the supporting substrate such that the source of the first MIS transistor and the drain of the second MIS transistor are connected to the connecting section and connected each other through the connecting section. An IC chip is provided on the first major surface and connected to gates of the first and second MIS transistors. An insulative envelope covers the supporting substrate, first and second semiconductor chips and IC chip. Partly exposed connecting terminals are electrically connected to the connecting section and first and second semiconductor chips.

Abstract: Aspects of the invention recite wire bonding on thinned portions of a lead-frame that is configured for use in an IC package. A harder lead-frame material, improved adhesive tape, and various structural features of the lead-frame itself, in various combinations or subcombinations, facilitate the attachment of wire bonds to thinned areas of the lead-frame. This eliminates the need for supports placed directly under the bond sites, removing unwanted conductive areas on the outer surface of an IC package.

Abstract: A contact hole fabrication method for semiconductor device includes forming a dielectric layer on a semiconductor substrate, forming an antireflective layer on the dielectric layer, forming an amine source layer on the antireflective layer, forming a photoresist layer on the amine source layer, forming a first hole pattern having a T profile and a footing profile by exposing and developing the photoresist layer, forming a second hole pattern in which the profiles are changed by reflowing the photoresist layer, and forming a contact hole by selectively removing the amine source layer, the antireflective layer, and the dielectric layer using the photoresist layer as a mask.

Abstract: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

Abstract: A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

Abstract: An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected and vertically twisted in a vertical twisting region between the first and second regions. The interconnection array subunit also includes a second pair of line conductors adjacent to the first pair of line conductors in the first and second regions, the second pair of line conductors including a second true line conductor and a second associated complementary line conductor.

Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, etc., and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.

Abstract: Exemplary embodiments of the present invention are drawn to improved systems and process for anodically bonding multiple substrate wafers to each other at low temperatures. At least one circuit wafer having printed circuits thereon is bonded to an interposer wafer by applying an amorphous thin film between the wafers. A low voltage is applied across the wafers to heat the wafers and to cause bonding of the wafers. Multiple circuit and interposer wafers can be used. The bonding temperature is low enough that soldered connections on the circuit wafers will not flow or otherwise distort, thus maintaining electrical integrity.

Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.

Abstract: The present invention discloses a structure of wafer level packaging. The structure comprises a first patterned isolation layer, a conductive layer and a second patterned isolation layer. The first patterned isolation layer is formed with a passivation layer of an IC (Integrated Circuit). The conductive layer is configured to have a curved or winding conductive pattern. The second patterned isolation layer is formed over the conductive layer to have a plurality of openings, and contact metal balls can be formed on the openings to electrically couple to a print circuit board.

Abstract: A truck includes an auxiliary power unit having components specifically selected such that they form a stand-alone unit that can fit within an auxiliary compartment of a vehicle and deliver heating, cooling, and additional electric power to the vehicle. Included is an auxiliary engine, an auxiliary alternator, and an auxiliary condenser to provide coolant for a personnel compartment mounted evaporator. An auxiliary voltage regulator provides a ramp-up feature to minimize excessive start-up loads, limits maximum available current from the auxiliary alternator when the auxiliary compressor is engaged, and selectively disables power to electrical components in the event of low vehicle battery voltage. The auxiliary engine includes a radiator system to provide heated fluid for a personnel compartment mounted heat exchanger.