Abstract: The field of the invention is that of devices for detecting non-metallic objects concealed on human subjects. These devices are more particularly dedicated to the surveillance and protection of reserved access areas, such as airport areas. The device according to the invention comprises a portable detector comprising a transmitter and a receiver of microwave frequency signals disposed in an enclosure of chaotic geometry including a plurality of measurement holes. The microwave frequency signal measured by this detector depends on the nature of the objects disposed under the holes. A processing device linked to this detector is used to correlate the measured signals with prerecorded signals. When the correlation exceeds a certain threshold corresponding to the presence of suspect objects, an alarm is generated.

Abstract: A method and apparatus for detecting an impedance across a pair of terminals. A sensing circuit is AC coupled to the terminals which produces an output related to a time constant associated with the impedance.

Abstract: A surface capacitance sensor system is implemented as an array of sensor electrodes near the surface of the integrated circuit and an array of stimulus electrodes below the sensor electrodes. Rows of stimulus electrodes are driven by sources while the voltages at the respective sensor electrodes are measured. Voltage measurements at each sensor electrode allow the surface capacitance at each sensor electrode location to be determined. The capacitance data is used to determine the positions of target electrodes above the array surface as required in the location fingerprint artifacts.

Abstract: A sensor device for measuring frequency and amplitude of a varying force signal is provided. The sensor device comprises a sensing element defined by a plurality of even numbered planar segments symmetrically disposed about a central axis, a protective housing for housing, an interface element comprising a pick up member, a planar mechanical actuator, a transfer member adapted to receive varying signals from the pick up, amplify the signals picked up and transfer the amplified signals to the said mechanical actuator; and leads for transmitting said output signals outside the sensing device for processing.

Abstract: A method for determining a fuel-dilution condition of a lubricant used in transportation and industrial equipment. The method uses apparatus that applies a high frequency and optionally a low frequency oscillating signal to electrodes immersed in the fluid and quantifies fluid response to the signals. Apparatus can further include means to control the lubricant temperature, or a temperature sensor to monitor the lubricant temperature at the electrodes. The method monitors response of the lubricant to the applied electrical signals and determines ratios of lubricant properties. The high-frequency lubricant property ratio or change of high frequency lubricant property as a function of a lubricant use-measure is compared to a predicted ratio based on lubricant use and an estimate of the lubricant's fuel dilution determined. The optional low-frequency lubricant property ratio is compared to thresholds to determine when the lubricant loses the ability to control fuel dilution.

Abstract: A twisting fixture probe for cleaning oxides, residues or other contaminants from the surface of a solder bead probe and probing a solder bead probe on a printed circuit board during in-circuit testing.

Abstract: A shielded probe apparatus is provided with a shielded probe and a tri-axial cable that are electrically connected within a shielded chassis. The shielded probe apparatus is capable of electrically testing a semiconductor device at a sub 100 fA operating current and an operating temperature up to 300 C.

Abstract: A test system for testing semiconductor components includes an interconnect having a substrate and contacts on the substrate for electrically engaging terminal contacts on the components. The interconnect also includes one or more cavities in the substrate which form flexible segments proximate to the interconnect contacts. The flexible segments permit the interconnect contacts to move independently in the z-direction to accommodate variations in the height and planarity of the terminal contacts. In addition, the cavities can be pressurized, or alternately filled with a polymer material, to adjust a compliancy of the flexible segments. Different embodiments of the interconnect contacts include: metallized recesses for retaining the terminal contacts, metallized projections for penetrating the terminal contacts, metallized recesses with penetrating projections, and leads contained on a polymer tape and cantilevered over metallized recesses.

Abstract: A method and apparatus for testing semiconductor wafers in which certain contact areas of dies not used in the testing and required to be at a predetermined voltage during testing are connected to the predetermined voltage via an integrated circuit in the die.

Abstract: A method, system and apparatus for testing an electronic device. The method including: (a) forming a temporary liquid heat transfer layer on a surface of the electronic device; after step (a), (b) placing a surface of a heat sink into physical contact with a surface of the heat transfer layer; after step (b), (c) electrically testing the electronic device; after step (c), (d) removing the heat sink from contact with the heat transfer layer; and after step (d), (e) removing any heat transfer layer remaining on the electronic device from the surface of the electronic device.

Abstract: A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components.

Abstract: In one embodiment, a first integrated circuit (IC) chip may comprise one or more bonding pads to which bonding wires from respective external leads may be connected. Other bonding wires connect the same bonding pads on the first IC chip to a second IC chip. This can be used, for example, to reduce the need for connections integral to the first IC chip for routing the signals received over the bonding wires internally in the first IC chip to the second IC chip.

Abstract: A method for testing a generator including a plurality of phase groups is provided. The method includes electrically isolating a first phase group from remaining phase groups by substantially encapsulating at least a portion of a plurality of stator bars electrically coupled together within the first phase group with an insulative member, electrically grounding at least a second phase group, and inducing a high voltage to the first phase group to facilitate proof testing the first phase group.

Abstract: Methods and apparatus for selectively allowing and disallowing changes to an impedance control signal applied to bus driver circuits coupling a device or system to a common, shared bus where impedance of the bus may vary over time. Well known impedance sensing circuits may be coupled to a common bus, such as a PCI bus, and may be used to generate an impedance control signal to be applied to well-known bus driver circuits, including, for example, PCI bus driver circuits, to vary the drive level of such bus driver circuits in accordance with the present electrical impedance sensed on the bus. Features and aspects hereof permit selectively allowing and disallowing changes to such impedance control signals as applied to the driver circuits based upon the present state of the bus and/or the present state of signals driven on the bus by the system embodying the features and aspects hereof.

Abstract: A system, method and device for managing power distribution on a shared bus system that interconnects multiple devices each containing a signal termination component are disclosed herein. In one embodiment, the method of the invention includes detecting and communicating thermal indicia of one or more of the devices in the shared bus system to a memory controller device. The memory controller includes an on-die termination control circuit for setting and resetting the enablement of the signal termination components of the one or more devices. In a preferred embodiment, the on-die termination control circuit sets and resets the enablement of the signal termination components in accordance with the determined thermal indicia.

Abstract: An apparatus comprising an integrated circuit and a logic portion. The integrated circuit may have a plurality of regions each (i) pre-diffused and configured to be metal-programmed and (ii) configured to connect the integrated circuit to a socket. The logic portion may be implemented on the integrated circuit. The plurality of metal programmable regions are each (i) independently programmable and (ii) located in one of said pre-diffused regions. Each of the metal programmable regions comprises (a) a regulator section configured to generate an operating voltage from a common supply voltage, (b) a logic section configured to implement integrated circuit functions and operate at the operating voltage, and (c) a level shifter configured to shift the operating voltage to an external voltage level.

Abstract: Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC.

Abstract: A tri-state detection circuit includes a first input port for receiving a tri-state input signal, a clock input port for receiving a clocking signal, a first output port, a second output port coupled to the first input port, a D-flip-flop and a buffer. The D-flip-flop has a D input, a clock input CLK, and a Q output. The D input is tied high. The clock input CLK is coupled to the first input port. The Q output is coupled to the first output port. The buffer has a buffer input and a buffer output. The buffer input is coupled to the clock input port. The buffer output is coupled to the clock input CLK of the D-flip-flop.

Abstract: A bus switch chip is limited to operating with a power-supply voltage of 1.8 volts relative to a 0-volt ground. Differential bus signals switched through the bus switch chip swing from 2.7 to 3.3 volts, well above the chip's specified power-supply voltage. The bus switch chip is level-shifted by applying a 1.5-volt signal as the chip's ground, and a 3.3-volt signal as its power supply, so the chip's net power supply is within the specification at 1.8 volts. High-Definition Multimedia Interface (HDMI) and Digital Visual Interface (DVI) require that the differential signals are never driven to ground. However, some non-compliant video transmitters drive differential signals to ground when disabled. External pullup resistors or internal pullup transistors in the bus switch chip are added to the bus signals from non-compliant transmitters to pull disabled signals above the 1.5-volt chip ground to prevent damage from signals below the chip's 1.5-volt ground.

Abstract: A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data input signal in response to a first control signal and a second control signal. The second circuit may be configured to (i) generate the first control signal and the second control signal and (ii) determine whether the first circuit is coupled to (a) a first logic level circuit when in a first state and (b) an impedance circuit and a second logic level circuit when in a second state.

Abstract: An output driver is responsive to an input signal and a swing width control signal (TE). The output driver is configured to generate an output signal having a first swing width (e.g., less than rail-to-rail) when the swing width control signal designates a normal mode of operation and a second swing width (e.g., rail-to-rail) when the swing width control signal designates a test mode of operation.

Abstract: A unit circuit includes: a capacitive element having a first electrode, a second electrode, and a dielectric layer interposed between the first and second electrodes; a transistor having a gate electrode connected to the first electrode; a first switching element that controls an electrical connection between the first electrode and a predetermined electric potential; and a second switching element connected to the second electrode. The electric potential of the first electrode is set to the predetermined electric potential by turning on the first switching element, and then, under a state in which the first electrode is electrically disconnected from the predetermined electric potential by turning off the first switching element, the electric potential of the first electrode is set to a first electric potential by a first operation signal supplied to the second electrode through the second switching element which is set to an ON state.

Abstract: A chain of processing element (10a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic (14) of a next processing element (10a, 10, 10b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (10b) includes loading time points of loading all processing elements (10a, 10) other than the final processing element (10).

Abstract: A frequency detection circuit and method of detecting the frequency of a clock signal, and a latency signal generation circuit for a semiconductor memory device that includes the frequency detection circuit. The frequency detection circuit includes a frequency detector and an output controller, which determines whether or not the frequency of the clock signal is higher than a predetermined value. Embodiments of the invention have an increased accuracy, increased efficiency, and a reduced current consumption over conventional art.

Abstract: A voltage (UE1, UE2), other than a supply voltage (UV1, UV2), is monitored and controlled to avoid damage to circuit components by maintaining a required voltage level. Dissipation power losses are reduced by switching off a monitoring circuit when monitoring is not required. For this purpose a stepped down voltage is derived from the voltage to be monitored at a tap (N1) of a voltage divider connected between ground potential and the voltage to be monitored. The derived voltage is then evaluated, for example by comparing with a reference voltage. A controllable switch is connected in series with two voltage divider elements. The switch is controlled to open for switching off the voltage divider when monitoring is not needed. The switch is closed to activate the voltage divider when monitoring is needed.

Abstract: A low-voltage detection circuit detects a terminal voltage of a power supply terminal. The low-voltage detection circuit includes a first voltage-dividing circuit, a second voltage-dividing circuit, and a comparator. The second voltage-dividing circuit includes a bias circuit and a metal-oxide-semiconductor (MOS) transistor. The comparator compares and receives a voltage generated by the first voltage-dividing circuit and a voltage generated by the second voltage-dividing circuit to generate a voltage detection signal.

Abstract: The present invention discloses a clock switching circuit, which comprises: a clock generator, receiving two different clock signals; a logic gate, coupled to an enable-signal generator and an output-clock generator, wherein during clock switching, the logic gate turns off output clock according to the signal edges of those two clock signals to avoid the problems of clock glitch and timing insufficiency, and the logic gate will not restore clock output until an appropriate timing occurs.

Abstract: In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. With this semiconductor device, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.

Abstract: An integrated circuit architecture comprises a phase lock loop (PLL) circuit that includes a feedback circuit that receives a reference signal. A voltage controlled oscillator (VCO) generates an output signal to an input of the feedback circuit. A master transistor has a control terminal, a first terminal, and a second terminal that communicates with the VCO. The feedback circuit compares the output signal of the VCO to the reference signal and outputs a drive signal to the control terminal of the master transistor based on the comparison. N slave transistors have control terminals that communicate with the control terminal of the master transistor, first terminals, and second terminals.

Abstract: A clock synchronization circuit (200, FIG. 2) includes a signal selector (202), phase detector (204), and delay line (206). The signal selector compares an external clock signal (220) and a feedback signal (222) to evaluate the jitter present in the external clock signal. When the jitter falls within an acceptable range, the circuit operates in DLL mode. In DLL mode, the external clock signal is provided to the delay line, and the delayed external signal is output (224) from the circuit. If the jitter falls outside the acceptable range and the circuit is locked, the circuit is switched to PLL mode. In PLL mode, a clock signal based on the feedback signal is provided to the delay line, and the delayed feedback signal is output from the circuit. The PLL mode is only allowed to operate briefly before switching the circuit back into DLL mode.

Abstract: A method and apparatus are provided for implementing a fault tolerant phase locked loop (PLL). The PLL circuit includes a divide by N circuit defined by a plurality of sub-divide by N functions, each providing a feedback frequency signal applied to a voter circuit. The voter circuit provides an output feedback frequency signal based upon a majority vote of the sub-divide by N functions.

Abstract: A switch mode power converter is provided which includes a switching cell with a supply input, an output and a control input. A summing comparator has first and second differential input pairs and an output. The output is connected to the control input of the switching cell. An oscillator provides a periodic waveform that is applied to a first one of the inputs of the first differential input pair of the summing comparator. An adjustable reference voltage source provides an adjustable reference voltage a predetermined fraction of which is applied to a second one of the inputs of the first differential input pair of the summing comparator. An error amplifier has differential outputs coupled to the second pair of differential inputs of the summing comparator and a differential input pair.

Abstract: A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty cycle irrespective of the duty cycle of the clock input to the DCC circuit. A DCC initialization scheme selectively activates the frequency division and edge detection operations in the DCC based on the lock status of the DCC during initialization. Upon initialization, the frequency division and edge detection operations are turned off or disabled. After the DCC is properly locked, these operations are enabled to obtain the 50% duty cycle output clock. This approach initializes the reduced-frequency DCC without output glitches, which can affect locking of a DLL with which the DCC may be used. The prevention of instability in locking of the DCC and DLL upon system initialization results in swift establishment of DCC and DLL locks without significant power consumption or loss of clock cycles.

Abstract: A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage current associated with these nodes. The additional circuitry, including a positive feedback circuit, improves the performance of a true single phase clock latch circuit at lower frequencies without significant degradation in high frequency operation of the latch.

Abstract: Circuits, methods, and apparatus for training a phase shift circuit to provide a phase shift for improved data recovery. A specific embodiment of the present invention provides a variable delay cell. A delay through the variable delay cell is changed while training patterns are received. The presence of errors in the received data pattern is tracked, and from the presence or absence of errors a preferred delay is selected and used for receiving data.

Abstract: An integrated semiconductor memory includes a clock generator circuit driven by an external clock signal and a control circuit driven by the external clock signal. The clock generator circuit generates an internal clock signal with a first level if the external clock signal level lies above a sensitivity level of the clock generator circuit for at least the duration of a sensitivity time of the clock generator circuit, and generates the internal clock signal with a second level if the external clock signal level lies below the sensitivity level for at least the duration of the sensitivity time of the clock generator circuit. The control circuit controls the clock generator circuit such that the control circuit selects the sensitivity time of the clock generator circuit in response to characteristics of the external clock signal.

Abstract: Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

Abstract: A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.

Abstract: A level shift circuit with high switching speed and low power dissipation is described. The circuit includes two short channel transistors, two long channel transistors, and two switching transistors. Short channel transistors are arranged to receive a high input voltage presenting relatively low impedance and low capacitance. Long channel transistors are arranged to receive a first voltage from the short channel transistors and provide an output voltage and an inverted output voltage, which are also employed to control the short channel transistors. A first switching transistor of the switching circuit enables the short channel and the long channel circuits to provide the output voltage based on a low input voltage and a logic input voltage. A second switching transistor enables the same circuits to provide the inverted output voltage based on the logic input voltage.

Abstract: A step-up/step-down circuit can be simplified as compared with conventional circuits by including a step-down unit for receiving a system clock pulse alternately providing a reference voltage (GND) and a system voltage VDD in a repeated manner to output a voltage V4 lower than the reference voltage (GND) by using a potential difference between the reference voltage (GND) and the system voltage VDD, a level shift unit for receiving the system clock pulse and the voltage V4 output from the step-down unit to output a pulse signal Vo having a greater potential difference than the potential difference between the reference voltage (GND) and the system voltage VDD, and a step-up unit for receiving the pulse signal Vo output from the level shift unit to output a voltage V7 higher than the reference voltage (GND).

Abstract: A voltage booster and regulator usable with Dickson-type charge pump device is specifically adapted to maintain efficiency with both high and low supply voltages. For high voltage supplies (e.g., 2.6 volts or more), the charge pump reduces overall power consumption resulting in a more efficient design. For low voltage applications (e.g., for supply voltages less than 2.6 volts), the charge pump uses a booster circuit to increase a clock input potential beyond the supply voltage available to a typical Dickson array. Further, the charge pump avoids inherent diode voltage drops in a typical Dickson array.

Abstract: In one embodiment, a capacitor of a charge pump circuit is referenced to a high side voltage or top voltage rail.

Abstract: An auto voltage sense circuit uses voltage controlled current sources to generate a desired reference voltage level that closely tracks the variations and changes of a first voltage level and a second voltage level. The auto voltage sensing circuit includes a first voltage controlled current source operable to receive the first voltage level to generate a reference current that is proportional to the first voltage level. The auto voltage sensing circuit also includes a second voltage controlled current source operable to receive the second voltage level and the reference voltage to generate an output current that is proportional to the difference between the second voltage level and the reference voltage. The reference voltage causes the output current to be approximately equal to the reference current so as to generate a reference voltage that is proportional to the difference between the second voltage level and the first voltage level.

Abstract: A bias-voltage supply circuit of a radio-frequency amplification circuit has the constant-voltage power supply generating a constant voltage higher than the bias voltage, a rectifier transistor and a constant-current power supply supplying a constant current to the rectifier transistor. The rectifier transistor is connected between a supply point of a bias voltage connected to an input terminal of the radio-frequency amplification transistor via an element for bias supply and a power supply voltage supply line, wherein a control terminal is kept by the constant voltage that the constant-voltage power supply generates. Since descent of the electric potential of the input terminal of a radio-frequency signal does not arise because of circuit composition, the radio-frequency amplification circuit has a good saturation characteristic.

Abstract: The present invention provides a method for single-ended compensation of an operational amplifier, which comprises: designing an operational amplifier having a single-ended offset style, preparing a common-mode circuit, a switch circuit, a comparator, a digital circuit and a compensation circuits. When a single-ended offset voltage of the operational amplifier is converted, output of the comparator will change state and will be detected by the digital circuit, so that the digital circuit will fix a group of digital signals, and instruct the switch circuit to block an average signal of the common-mode circuit, allowing a set of double-end input signals to be inputted to the operational amplifier directly.

Abstract: An apparatus for effecting signal chopping in an amplifier device having an amplifier section, a modulation section, a ramp generating section and a clock section includes: at least one signal treating unit coupled among the clock section, the amplifier section and the ramp generating section. The at least one signal treating unit cooperates with the clock section to effect providing a chopping signal to the amplifying unit at a chopping frequency and to effect providing a ramping signal at a ramping frequency to the ramp generating section. The chopping frequency is neither a fundamental frequency nor a harmonic frequency of the ramping frequency.

Abstract: Systems and methods for detecting the impedance of an output load coupled to a digital amplifier and compensating for changes in the response of the amplifier. One embodiment of the invention is implemented in a Class D pulse width modulated (PWM) amplifier. In this embodiment, a digital PCM test signal is generated. This test signal is processed by the amplifier to produce a corresponding analog audio output signal that is used to drive a speaker. A sense resistor placed in series with the speaker is used to generate a test voltage that is compared to a reference voltage. When the test voltage reaches the reference voltage, the current through the sense resistor (hence the speaker) is at a known level, so the value of the digital test signal is noted. The impedance of the speaker is then determined from the test signal value and the speaker current.

Abstract: In an amplifier circuit with reduced power-on transients, an amplifier has a gain to generate an output signal from an input signal and a reference signal when it is enabled, and a control circuit generates a control signal, based on the output signal and the reference signal, to be supplied to the amplifier during a power-on event. The amplifier is enabled by the control signal when the reference signal reaches the level of the output signal.

Abstract: A plurality of variable gain amplifier stages are coupled by an attenuation circuit that receives a voltage input to be amplified. A control circuit activates each of the variable gain amplifier stages in a seamless manner in accordance with a control signal applied to a voltage control node, while maintaining no more than one of the stages active at any time. Fractions of the reference signal voltage level are set to define boundaries between control voltage level ranges of the amplifier stages. A unique control voltage level range is thus established for each amplifier stage. A control voltage hysteresis range can be provided to avoid oscillations between stages at the transition voltages.