Patents Issued in September 11, 2007
  • Patent number: 7268406
    Abstract: A mask in which a plurality of mask chips are connected to one another via a supporting member, includes: a plurality of first opening sections that are provided in the plurality of mask chips and that correspond to a pattern to be formed; a cutout section provided at at least one of side faces opposing to each other of the mask chips adjacent to each other; a gap section provided at a connected section connecting the mask chips adjacent to each other, the gap section being composed of the cutout section and including a second opening section corresponding to a pattern to be formed; and a block section that is provided at at least one of the mask chips adjacent to each other and that covers the gap section other than the second opening section.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: September 11, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Shinichi Yotsuya, Takayuki Kuwahara, Hiroshi Koeda
  • Patent number: 7268407
    Abstract: Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: September 11, 2007
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Moon Gyu Jang, Yark Yeon Kim, Jae Heon Shin, Seong Jae Lee
  • Patent number: 7268408
    Abstract: A wiring board which can realize a small and thin passive component such as solid condenser, resistor, coil, transistor or so on is provided. A wiring board which forms an electronic component by mounting a passive element, comprising an insulating board provided with an opening having predetermined pattern, a wiring formed with predetermined pattern on said insulating board, and an external terminal filled to said opening, connected with said wiring by said filling, and exposed to a bottom of said insulating board where said wiring is formed.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: September 11, 2007
    Assignee: Hitachi Cable Ltd.
    Inventors: Akira Chinda, Akira Matsuura, Takayuki Yoshiwa, Mamoru Mita, Takashi Kageyama, Katsutoshi Taga
  • Patent number: 7268409
    Abstract: A microelectronic device including, in one embodiment, a plurality of active devices located at least partially in a substrate, at least one dielectric layer located over the plurality of active devices, and an inductor located over the dielectric layer. At least one of the plurality of active devices is located within a columnar region having a cross-sectional shape substantially conforming to a perimeter of the inductor. The at least one of the plurality of active devices may be biased based on a desired Q factor of the inductor or and/or an operating frequency of the microelectronic device.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Min Tseng, Chih-Sheng Chang
  • Patent number: 7268410
    Abstract: Improvements in the level of integration of a core buck and/or boost DC-DC voltage regulator sub-circuit lead to a lower manufacturing cost structure, an improved performance from lessened intrinsic parasitic resistance, a smaller die size and, thus, higher wafer yield. Further, by integrating certain components on-chip, the cost and complexity of the conventional hybrid circuit implementation is improved.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: September 11, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Robert Drury
  • Patent number: 7268411
    Abstract: A capacitor includes a first electrode, an insulating film and a second electrode. The insulating film includes n layers of barrier layers each consisting of a material having a bandgap larger than a first bandgap and having a relative permittivity smaller than a first relative permittivity, and (n?1) layers of well layers each consisting of a material having a bandgap smaller than the first bandgap and having a relative permittivity larger than the first relative permittivity. The barrier layers and the well layers are stacked by turns. Discrete energy levels are formed in each of the well layers by a quantum effect. Thicknesses of the n layers of the barrier layers are not smaller than 2.5 angstroms. A thickness dm (angstrom) and a relative permittivity ?m of an m-th barrier layer satisfying the condition: 2.5 >(d1/?1+d2/?2+. . . +dn/?n).
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hideki Satake
  • Patent number: 7268412
    Abstract: A bipolar transistor with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and spaced from the emitter structure. A dielectric layer is deposited over the substrate and connections are formed to the extrinsic base structure, the emitter structure and the collector region.
    Type: Grant
    Filed: February 12, 2005
    Date of Patent: September 11, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Purakh Raj Verma, Shao-fu Sanford Chu
  • Patent number: 7268413
    Abstract: Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching speed and current gain of bipolar transistors. Current fabrication techniques involve high temperature procedures that melt desirable low-resistance substitutes, such as aluminum, during fabrication. Accordingly, one embodiment of the invention provides an emitter contact structure that includes a polysilicon-carbide layer and a low-resistance aluminum, gold, or silver member to reduce emitter resistance. Moreover, to overcome manufacturing difficulties, the inventors employ a metal-substitution technique, which entails formation of a polysilicon emitter, and then substitution or cross-diffusion of metal for the polysilicon.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7268414
    Abstract: A semiconductor package mounted on a printed circuit board using improved-reliability solder joints is described. The semiconductor package includes a lead frame pad and lead frame lead attached to the solder joints, a semiconductor chip mounted on top of the lead frame pad, wires electrically connecting the semiconductor chip and the lead frame lead, an epoxy molding compound that exposes the lower portion surface of the lead frame pad and part of the lead frame lead, and protrusions fixed to the lower portion surface of the epoxy molding compound and positioned between the solder joints, with the protrusions supporting the semiconductor package when the epoxy molding compound is mounted on the printed circuit board.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: September 11, 2007
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Seung-yong Choi, Seung-han Paek
  • Patent number: 7268415
    Abstract: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The device further has a semiconductor chip (103) attached to the mount pad and electrical interconnections (107) between the chip and the first segment ends. Encapsulation material (120) covers the chip, the bonding wires and the first segment ends, yet leaves the second segment ends exposed. At least portions of the second segment ends have the base metal covered by a layer of solderable metal (130, e.g., nickel) and by an outermost layer of noble metal (140, e.g., stack of palladium and gold).
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Edgar R. Zuniga-Ortiz
  • Patent number: 7268416
    Abstract: A mounting structure includes a mounting substrate on which a plurality of mounting pads each constituting a portion of a conductive pattern extending in a Y direction are arranged in an X direction, the X direction and the Y direction being two directions orthogonal to each other, and a member that is mounted on the mounting substrate so as to be electrically connected to the mounting pads. In the mounting structure, a first conductive layer, an insulating layer, a second conductive layer, and a third conductive layer are formed on the mounting substrate in this order from a lower side to an upper side.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: September 11, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Hiroaki Furihata
  • Patent number: 7268417
    Abstract: A electronic circuit device is provided with an electronic component provided with an electrode, a substrate having an upper surface on which the electronic component is mounted, external electrode that is formed near the electronic component mounted on the upper surface of the substrate and that is connected to the electrode, an insulating protrusion that is provided across the upper surface of the external electrode, and a sealing resin that seals the electronic component without covering the external electrode. The upper surface of the external electrode is partitioned by the protrusion into a first area that is located on the sealing resin side and a second area that is located the side opposite to the first area. The adherence of fine particles such as flakes of the sealing resin to the external electrode is suppressed, so that a stable electric connection between the external electrode and the electric equipment can be maintained.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: September 11, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takao Ochi, Takashi Takata
  • Patent number: 7268418
    Abstract: A multi-chips stacked package at least comprises a substrate, a lower chip, an upper chip, an adhesive layer, a supporting body and an encapsulation. The lower chip is disposed on the substrate and the upper chip is attached to the lower chip via the adhesive layer. In addition, the lower chip and the upper chip are electrically connected to the substrate via first electrically conductive wires and second electrically conductive wires respectively. Furthermore, the supporting body is disposed on the lower chip and at the periphery of the upper surface of the lower chip, and covered by the upper chip. The top of the supporting body is apart from the back surface of the upper chip with a distance. Accordingly, when the second electrically conductive wires are bonded the upper chip to the substrate with a larger bonding force to cause the upper chip to be tilted more, the supporting body will support the upper chip and prevent the upper chip from contacting the first electrically conductive wires.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: September 11, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Sung-Fei Wang
  • Patent number: 7268419
    Abstract: One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: September 11, 2007
    Assignee: Apple Inc.
    Inventor: William P. Cornelius
  • Patent number: 7268420
    Abstract: A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: September 11, 2007
    Assignee: Elpida Memory, Inc.
    Inventor: Yukitoshi Hirose
  • Patent number: 7268421
    Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a metal pillar, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The chip and the metal pillar are embedded in the encapsulant, the routing line extends laterally beyond the metal pillar towards the chip, and the metal pillar is welded to the routing line.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: September 11, 2007
    Assignee: Bridge Semiconductor Corporation
    Inventor: Charles W. C. Lin
  • Patent number: 7268422
    Abstract: What is invented is a semiconductor device (10) comprising a pellet (12) having a ground electrode (18), an outside signal terminal (15) connected to the pellet (12), so as to receive signal which is likely to include noise. Therein, said outside signal terminal (15) is surrounded with a ground terminal (17) connected to said ground electrode (18) in at least a half periphery.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: September 11, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura
  • Patent number: 7268423
    Abstract: The present invention describes a rewiring plate for components with connection grids of between approx. 100 nm and 10 ?m, which rewiring plate includes a base body and passages with carbon nanotubes, the lower end of the passages opening out into contact connection surfaces, and the carbon nanotubes forming an electrically conductive connection from the contact connection surfaces to the front surface of the base body.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Jochen Dangelmaier, Alfred Haimerl, Manfred Mengel, Klaus Mueller, Klaus Pressel
  • Patent number: 7268424
    Abstract: A semiconductor device comprises a substrate, an external terminal provided on the substrate, an internal wiring pattern electrically connected to the external terminal, a semiconductor chip mounted on the substrate and electrically connected to the internal wiring pattern, and an antenna pattern. The antenna pattern provided at each of adjacent two corner portions of the substrate and is grounded.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minori Kajimoto, Osamu Ikeda, Masaki Momodomi
  • Patent number: 7268425
    Abstract: A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink. One ore more chips are bonded to the wiring layer, and an array of connectors, such as solder balls are provided around the periphery of the chip(s) for connection to a printed circuit board. In some embodiments, the printed circuit board has a hole that the chip(s) extend into to allow smaller external-connection solder balls. In some embodiments, a second heat sink is connected to the back of the chip through the PCB hole.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: September 11, 2007
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Robert L. Sankman
  • Patent number: 7268426
    Abstract: A packaged semiconductor chip includes features such as a chip carrier having a large thermal conductor which can be solder-bonded to a circuit panel so as to provide enhanced thermal conductivity to the circuit panel and electromagnetic shielding and a conductive enclosure which partially or completely surrounds the packaged chip to provide additional heat dissipation and shielding. The packaged unit may include both an active semiconductor chip and a passive element, desirably in the form of a chip, which includes resistors and capacitors. Inductors may be provided in whole or in part on the chip carrier.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: September 11, 2007
    Assignee: Tessera, Inc.
    Inventors: Michael Warner, Lee Smith, Belgacem Haba, Glenn Urbish, Masud Beroz, Teck-Gyu Kang
  • Patent number: 7268427
    Abstract: A holding fixture that holds a component and mounts the component on an electronic circuit board includes a holding member that holds the component at a side of a first surface of the electronic circuit board, a first fixing member that includes a first base that is engageable with the holding member, and an elastic member that is pivotally attached to the base, sandwiches the electronic circuit board at a side of a second surface of the electronic circuit board, and elastically supports the holding member at the side of the first surface, the second surface opposing to the first surface, and a second fixing member that includes a second base that is engageable with the holding member, and a projection member that projects from the second surface of the electronic circuit board and is engageable with the elastic member.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: September 11, 2007
    Assignee: Fujitsu Limited
    Inventor: Hisao Anzai
  • Patent number: 7268428
    Abstract: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of the die extends between the lid and the substrate, contains the thermal compound, and flexes in response to expansion and contraction of both the substrate and the lid during cycling of the semiconductor module. More particularly, either the barrier is formed of a flexible material or has a flexible connection to the substrate and/or to the lid. The barrier effectively contains the thermal compound between the die and the lid and, thereby, provides acceptable and controlled coverage of the thermal compound over the die for heat removal.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: David L. Edwards, Sushumna Iruvanti, Hilton T. Toy, Wei Zou
  • Patent number: 7268429
    Abstract: A technique for manufacturing an electronic assembly uses a mold that has a first mold portion and a second mold portion. The first mold portion includes a plurality of spaced mold pins extending from an inner surface. A cavity of the first and second mold portions provides a mold cavity, when joined. A backplate is also provided that includes a plurality of support pedestals and an integrated heatsink extending from a first side of the backplate. A substrate includes a first side of an integrated circuit (IC) die mounted to a first side of the substrate. The backplate and the substrate are placed within the cavity of the second mold portion and the support pedestals are in contact with the first side of the substrate. The first and second mold portions are joined and the mold pins contact a second surface of the substrate during an overmolding process.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: September 11, 2007
    Assignee: Delphi Technologies, Inc.
    Inventors: Scott D. Brandenburg, David A. Laudick, Thomas A. Degenkolb, Matthew R. Walsh, Jeenhuei S. Tsai
  • Patent number: 7268430
    Abstract: The present invention relates to a semiconductor device in which electrodes formed on a semiconductor chip and electrodes formed on a wiring board are electrically connected via projecting elastic electrodes, and further relates to a mounting method of reducing a pressure applied to electrodes formed on a substrate or underlying wirings when a semiconductor chip and a wiring board are bonded.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: September 11, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tadatomo Suga, Toshihiro Itoh
  • Patent number: 7268431
    Abstract: In a shadow mask vapor deposition system, a first conductor is vapor deposited on a substrate and an insulator is vapor deposited on the first conductor. A second conductor is then vapor deposited on at least the insulator. The insulator layer is plasma etched either before or after the vapor deposition of the second conductor to define in the insulator layer a via hole through which at least a portion of the first conductor is exposed. An electrical connection is established between the first and second conductors by way of the via hole.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: September 11, 2007
    Assignee: Advantech Global, Ltd
    Inventors: Thomas P. Brody, Joseph A. Marcanio
  • Patent number: 7268432
    Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Matthew E. Colburn, Satya V. Nitta, Sampath Purushothaman, Charles Black, Kathryn Guarini
  • Patent number: 7268433
    Abstract: A wiring layer is provided on a semiconductor substrate and extends in a predetermined direction. An external connection electrode terminal is provided on the wiring layer through a plurality of column-shaped conductors. The column-shaped conductors are located under the external connection electrode terminal. A density of arrangement of the column-shaped conductors is varied according to a direction of extension of the wiring layer.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: September 11, 2007
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Matsuoka, Kazuyuki Imamura, Masao Oshima, Takashi Suzuki, Toyoji Sawada
  • Patent number: 7268434
    Abstract: There is disclosed a semiconductor device comprising at least one first insulating film provided above a substrate, being formed with at least one first recess having a first width, and being formed with at least one second recess having a second width which is 1/x (x: positive numbers larger than 1) a size of the first width and having a same depth as the first recess, a second insulating film provided at both sides of the first recess and at a lower part of the second recess, and a conductor provided inside of the second insulating films provided at the both sides of the first recess with extending from an opening of the first recess to a bottom surface thereof, and provided with extending from an opening of the second recess to an upper surface of the second insulating film provided at the lower part of the second recess.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuichi Nakashima
  • Patent number: 7268435
    Abstract: In a capacitive semiconductor sensor, a sensor chip and a circuit chip are contained in a package. First bump members are mounted on second electrodes disposed on a second surface of the circuit chip, respectively. The sensor chip is mounted at its first surface on the second surface of the circuit chip so that first electrodes disposed on the first surface of the sensor chip are electrically mechanically connected to the second electrodes through the first bump members, respectively. Second bump members are mounted on third electrodes disposed on the second surface of the circuit chip, respectively. The third electrodes are electrically mechanically connected to lead electrodes disposed to the package through the second bump members, respectively.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: September 11, 2007
    Assignee: DENSO CORPORATION
    Inventor: Tameharu Ohta
  • Patent number: 7268436
    Abstract: An electronic device can include a top side with circuit structures. The circuit structures form the bottom region of a cavity. Each cavity can be surrounded by a cavity frame made of plastic and can have a cavity cover made of semiconductor material.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Robert Aigner, Albert Auburger, Frank Daeche, Guenter Ehrler, Andreas Meckes, Horst Theuss, Michael Weber
  • Patent number: 7268437
    Abstract: A semiconductor package with an encapsulated passive component mainly includes at least a substrate having a surface, a passive component and a molding compound. A plurality of SMD pads (Solder Mask Defined pads) and a solder mask are formed on the surface of the substrate. Each SMD pad has an exposed sidewall portion exposed out of the solder mask. A blocking bar is formed between the exposed sidewall portions of the SMD pads. There is at least a flowing channel formed between the blocking bar and the exposed sidewall portions. The passive component is mounted on the surface of the substrate and connected to the SMD pads, the flowing channel is located under the passive component. It is advantageous to fill the molding compound into the flowing channel.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: September 11, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Sheng-Tsung Liu
  • Patent number: 7268438
    Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: September 11, 2007
    Assignee: NEC Corporation
    Inventors: Tomohiro Nishiyama, Masamoto Tago
  • Patent number: 7268439
    Abstract: A semiconductor device having a molded sealing resin for sealing a semiconductor chip on a circuit board thereof reduces resin burrs resulting from the leakage of the sealing resin, and also restrains the occurrence of disconnection caused by a wiring layer being crushed. In the semiconductor device, the sealing resin for sealing the semiconductor chip is molded on the circuit board that has a plurality of wiring patterns and a solder resist for insulatively covering the wiring patterns formed on the front surface thereof, the interval of the wiring patterns is set to range from 50% to 200% of its adjacent interval in a molding line area of the sealing resin.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: September 11, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Shuichi Matsuda
  • Patent number: 7268440
    Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of active circuit die areas has four sides. An overcoat covers both the active circuit die areas and the dicing line region. An inter-layer dielectric layer is disposed underneath the overcoat. A reinforcement structure includes a plurality of holes formed within the dicing line region. The plurality of holes are formed by etching through the overcoat into the inter-layer dielectric layer and are disposed along the four sides of each active circuit die area. A die seal ring is disposed in between the active circuit chip area and the reinforcement structure.
    Type: Grant
    Filed: January 9, 2005
    Date of Patent: September 11, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Zong-Huei Lin, Hung-Min Liu, Jui-Meng Jao, Wen-Tung Chang, Kuo-Ming Chen, Kai-Kuang Ho
  • Patent number: 7268441
    Abstract: In the control device for motor generator in which an engine is started and power generation is performed while a vehicle is running, a field current limit value Ifm in electric driving to start the engine is larger than a field current limit value Ifg in power generation. In the power generation, an inverter mode in a low rotation speed zone for boosting and an alternator mode in a high rotation speed zone for rectifying and outputting a generated voltage without boosting are provided. A field current limit value Ifgi in the inverter-mode power generation and a field current limit value Ifga in the alternator-mode power generation are set differently from each other, and the larger value is set as the value Ifg.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: September 11, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihito Asao, Shinji Nishimura
  • Patent number: 7268442
    Abstract: A method is disclosed for estimating engine power output for an engine in a hybrid electric vehicle powertrain that includes an electric motor and an electric generator. Selected powertrain variables, including electric motor torque and electric generator torque, are used in determining desired vehicle traction wheel torque and an estimated engine power. A calibrated delay in calculating estimated engine power following a time sampling of the values for motor torque and generator torque avoid inertial effects.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: September 11, 2007
    Assignee: Ford Global Technologies, LLC
    Inventors: Fazal Syed, Ming Kuang, John Czubay
  • Patent number: 7268443
    Abstract: A wind turbine generator system can regulate the rotational velocity of the wind turbine within an operation range even when the wind velocity suddenly changes and can perform continuous operation of the wind turbine. The wind turbine generator system includes a generator connected to the shaft of the wind turbine and a converter connected to the generator. When the rotational velocity of the wind turbine is within a predetermined range, power outputted from the generator is controlled so as to follow the instruction concerning the generator output given from the wind turbine to the converter. When the rotational velocity of the wind turbine is out of the predetermined range, the power outputted from the generator is controlled without following the instruction concerning generator output given from the wind turbine to the converter.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: September 11, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Akira Kikuchi, Masaya Ichinose, Motoo Futami, Mitsugu Matsutake, Kouichi Miyazaki
  • Patent number: 7268444
    Abstract: A supply line structure for supplying energy to the electrical components of an automotive vehicle and for transmitting information between at least some of the electrical components, the supply lines being disposed, in particular in a star structure having at least one star point; in order to be able to transmit high supply currents, the supply line structure is configured in such a way that at least a part of the supply lines includes a coaxial arrangement of a plurality of outer litz wires about a central litz wire.
    Type: Grant
    Filed: October 13, 2003
    Date of Patent: September 11, 2007
    Assignee: Robert Bosch GmbH
    Inventors: Thorsten Enders, Juergen Schirmer, Frank Stiegler, Timo Kuehn, Klaus Dostert
  • Patent number: 7268445
    Abstract: An airbag device includes a squib, an ignition circuit, and a noise protection circuit. The noise protection circuit includes two zener diodes whose cathodes are facing each other and connected with each other. Further, the noise protection circuit is connected in parallel with the ignition element to thereby protect the ignition circuit from noise. This decreases the number of components in the noise protection circuit to thereby achieve the compact and low-cost airbag device.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: September 11, 2007
    Assignee: DENSO CORPORATION
    Inventors: Yutaka Uono, Makoto Aso
  • Patent number: 7268446
    Abstract: An automotive power control center that includes a housing, a first conductor coupled to the housing, a second conductor, a control circuit, which is coupled to the housing, and a semiconductor. The second conductor is coupled to the housing and insulated from the first conductor. The solid-state device includes a first terminal, which is electrically coupled to the first conductor, a second terminal, which is electrically coupled to the second conductor, and a third terminal, which is electrically coupled to the control circuit. The solid-state device is configured to selectively control transmission of electricity between the first and second terminals in response to a signal transmitted from the control circuit through the third terminal. In some embodiments the solid-state device may be removably coupled to the housing. In other embodiments, the solid-state device may be fixedly coupled to the various conductors and terminals.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: September 11, 2007
    Assignee: Yazaki North America, Inc.
    Inventors: James L Jones, Kenneth J Russel, Baris Arakelian, Alexander Shoshiev
  • Patent number: 7268447
    Abstract: An automotive power control center that includes a housing, a first conductor coupled to the housing, a second conductor, a control circuit, which is coupled to the housing, and a semiconductor. The second conductor is coupled to the housing and insulated from the first conductor. The solid-state device includes a first terminal, which is electrically coupled to the first conductor, a second terminal, which is electrically coupled to the second conductor, and a third terminal, which is electrically coupled to the control circuit. The solid-state device is configured to selectively control transmission of electricity between the first and second terminals in response to a signal transmitted from the control circuit through the third terminal. In some embodiments the solid-state device may be removably coupled to the housing. In other embodiments, the solid-state device may be fixedly coupled to the various conductors and terminals.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: September 11, 2007
    Assignee: Yazaki North America, Inc.
    Inventors: Kenneth J Russel, James L Jones, Baris Arakelian, Alexander Shoshiev
  • Patent number: 7268448
    Abstract: Disclosed are a control circuit and control method for a comparator-controlled type DC-DC converter that can prevent the generation of audible noise due to the difference between relevant switching frequencies and prevent the increase in the input power source ripple voltage. A phase comparator FC outputs a compared-result signal CONT in correspondence with the phase difference between an output signal FP2 and a delay signal FR1. A delay circuit DLY2 performs a feedback control for adjusting the amount of retardation time in correspondence with the compared-result signal CONT. And, the delay circuit DLY2 outputs a delay signal FR2 after the passage of a prescribed amount of retardation time from the time when the falling edge of an output signal SQB2 has been input.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: September 11, 2007
    Assignee: Fujitsu Limited
    Inventor: Morihito Hasegawa
  • Patent number: 7268449
    Abstract: A stopper member is included in a linear actuator comprising a stator assembly, a rotor assembly, an output shaft, and a stopper pin which is fixedly disposed at a frontward portion of the output shaft, and which is adapted to axially control the mode and amount of movement of the output shaft initiated by rotation of the rotor assembly. The stopper member is disposed fixedly with respect to the stator assembly and stops the axial movement of the output shaft without making it happen that the stopper pin which moves together with the output shaft touches the rotor assembly.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: September 11, 2007
    Assignee: Minebea Co., Ltd.
    Inventors: Yuzuru Suzuki, Shinji Tamaki
  • Patent number: 7268450
    Abstract: A permanent magnet type generator includes a rotor having 4n (n is a positive integer) permanent magnet poles disposed in a circumferential direction of the rotor to have circumferential gap between adjoining poles and a stator that has 3n teeth and coils wound around the teeth. The stator core includes a pair of core end plates and a laminate core disposed between the core end plates. Each core end plate has a circumferential width that relates to the gap distance at portions opposite the permanent magnet poles.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: September 11, 2007
    Assignees: Denso Corporation, Denso Trim Co., Ltd.
    Inventor: Norikazu Takeuchi
  • Patent number: 7268451
    Abstract: A motor resolver assembly includes a resolver stator and a resolver rotor positioned radially inward of and rotatable with respect to the resolver stator. First and second relatively rotatable shield components generally surround the resolver stator and rotor to shield them from electromagnetic energy from a radially outward motor rotor and motor stator. A method of measuring speed and position of the motor rotor relative to the motor stator is also employed.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: September 11, 2007
    Assignees: General Motors Corporation, DaimlerChrysler AG, DaimlerChrysler Corporation
    Inventors: Erik M. Hertz, Christopher J. Bowes, Alan G. Holmes, James A. Raszkowski
  • Patent number: 7268452
    Abstract: A spindle motor is provided in which an end portion of a winding of a coil maintains insulation from a base and the end portion of the winding of the coil can be easily threaded through a hole of a printed circuit board when the end portion of the winding of the coil is drawn out. For this, the spindle motor includes a base fixed with a stator having a coil, an insulating sheet provided between the stator and the base, and a printed circuit board provided in the base on an outer side of the motor. Holes are formed in the base, insulating sheet and printed circuit board so as to communicate with each other, and an winding end portion of the coil is led out to the outside of the motor. The diameter C of the hole 19 in the printed circuit board and the diameter B of the hole 18 of the insulating sheet are smaller than the diameter A of the hole 17 of the base, and the diameter C of the hole 19 is larger than the diameter B of the hole 18.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: September 11, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nobuhiro Yoshino, Takeyoshi Yamamoto
  • Patent number: 7268453
    Abstract: In axial magnetic bearing apparatus in which a rotary disc made of a magnetic material is fixedly attached to a rotating shaft, and electromagnets are disposed on opposite sides of the rotary disc so as to have suitable very small distances therefrom respectively, so as to bear the rotating shaft axially in a non-contact state, a deep groove for forming an air layer having large magneto-resistance is provided all over the outer circumference of the rotary disc. Thus, formation of a magnetic circuit not contributing to position control is relieved, and the weight of the disc is reduced so that the position control performance of the axial magnetic bearing and the natural frequency of a rotor are improved.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: September 11, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akihiro Shimada
  • Patent number: 7268454
    Abstract: A power generating system includes a torque converter system receiving a rotational motion having a first torque from a source and producing a rotational output having a second torque different from the first torque, a transfer system having a first portion coupled to the rotational output of the torque converter system and a second portion magnetically coupled to the first portion, and a generator system coupled to the transfer system to produce and electrical output.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: September 11, 2007
    Assignee: Magnetic Torque International, Ltd.
    Inventor: Richard J. Wise
  • Patent number: 7268455
    Abstract: A phase winding of a stator winding comprises one or more pairs of interconnected partial coil, each partial coil formed of sequentially connected U-shaped segment pairs, each pair comprising a large segment and small segment. Two segment legs, of the large and small segment respectively of such a pair, constitute first and second conductor layers of a first stator slot and have their tip portions mutually connected. The remaining two segment legs respectively constitute fourth and third conductor layers of a second slot that is distant by one pole pitch, and have their respective tip portions mutually connected.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: September 11, 2007
    Assignee: Denso Corporation
    Inventors: Shinji Kouda, Masahiro Seguchi