Abstract: A white light LED for use in backlighting or otherwise illuminating an LCD is described where the white light LED comprises a blue LED over which is affixed a preformed red phosphor platelet and a preformed green phosphor platelet. In one embodiment, to form a platelet, a controlled amount of phosphor powder is placed in a mold and heated under pressure to sinter the grains together. The platelet can be made very smooth on all surfaces. A UV LED may also be used in conjunction with red, green, and blue phosphor plates. The LED dies vary in color and brightness and are binned in accordance with their light output characteristics. Phosphor plates with different characteristics are matched to the binned LEDs to create white light LEDs with a consistent white point for use in backlights for liquid crystal displays.

Abstract: A light emitting diode (LED) array with beam directors outputting a high-intensity collimated beam. The LED array is constructed from a substrate component on which the LEDs and necessary electronics are disposed and a director attachment having a plurality of beam directors. The beam directors have a unique structure that is designed to shape the light beam into a collimated form. The LEDs are arranged in a pattern on the substrate, and the beam directors are arranged within the director attachment to coincide with the LEDs. The substrate and the director attachment may be manufactured and processed as separate components; they are then affixed together for operation.

Abstract: A light emitting device 1 has, as a light source, a light emitting semiconductor element such as a light emitting diode 2. Light radiated from the light emitting diode 2 is converted to visible light in a light emitting part 8 having a plurality of phosphors 9 different in emission color, and the visible light is emitted. In such a light emitting device 1, a maximum value (?x, ?y) of color difference (absolute value) between emission chromaticity (x, y) and emission chromaticity (x1, y1) satisfies conditions of ?x<0.05 and ?y<0.05, where (x, y) is emission chromaticity measured directly above the light source and (x1, y1) is emission chromaticity measured for each of front lights and side leakage lights in all directions from the light emitting device 1.

Abstract: A light reflection sheet includes a transparent buffering layer and a reflection layer, formed on two opposite surfaces of a transparent substrate, respectively. With the buffering effect provided by the transparent buffering layer, the possible damage caused to the light reflection sheet or a V-cut light guide plate when they engage with each other can be avoided.

Abstract: An insulation structure for high temperature conditions and a manufacturing method thereof. In the insulation structure, a substrate has a conductive pattern formed on at least one surface thereof for electrical connection of a device. A metal oxide layer pattern is formed on a predetermined portion of the conductive pattern by anodization, the metal oxide layer pattern made of one selected from a group consisting of Al, Ti and Mg.

Abstract: A semiconductor light-emitting element mounting member with an improved effective light reflectivity in a metal film serving as an electrode layer and/or a reflective layer, in which the metal layer has improved adhesion to a substrate, mechanical strength, and reliability and superior light-emitting characteristics. The semiconductor light-emitting element mounting member (a submount) is made by forming on a substrate metal films formed from Ag, Al, or an alloy containing these metals. The particle diameter of the crystal grains of the metal films is no more than 0.5 ?m and the center-line average roughness Ra of the surface is no more than 0.1 ?m. In a semiconductor light-emitting device, a semiconductor light-emitting element is mounted in the submount.

Abstract: A light emitting diode package structure having a heat-resistant cover and a method of manufacturing the same include a base, a light emitting diode chip, a plastic shell, and a packaging material. The plastic shell is in the shape of a bowl and has an injection hole thereon. After the light emitting diode chip is installed onto the base, the plastic shell is covered onto the base to fully and air-tightly seal the light emitting diode chip, and the packaging material is injected into the plastic shell through the injection hole until the plastic shell is filled up with the packaging material to form a packaging cover, and finally the plastic shell is removed to complete the LED package structure.

Abstract: A gallium arsenide (GaAs) integrated circuit device is provided. The GaAs circuit device has a GaAs substrate with a copper contact layer for making electrical ground contact with a pad of a target device. Although copper is known to detrimentally affect GaAS devices, the copper contact layer is isolated from the GaAs substrate using a barrier layer. The barrier layer may be, for example, a layer of nickel vanadium (NiV). This nickel vanadium (NiV) barrier protects the gallium arsenide substrate from the diffusion effects of the copper contact layer. An organic solder preservative may coat the exposed copper to reduce oxidation effects. In some cases, a gold or copper seed layer may be deposited on the GaAs substrate prior to depositing the copper contact layer.

Abstract: A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. Abase region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A region having a low breakdown voltage is formed on the first surface around the IGBT, and a carrier collecting region is formed in the vicinity of the region having the low breakdown voltage. The IGBT is prevented from being broken down due to an avalanche phenomenon, because the breakdown occurs in the region having the low breakdown voltage, and carriers of the breakdown current are collected through the carrier collecting region. The breakdown of the IGBT is further effectively prevented by forming a guard ring for suppressing electric field concentration around the region having the low breakdown voltage.

Abstract: A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode, a first gate positioned between the supply electrode and the drain electrode and capacitively coupled to the semiconductor element to form a first portion of the transistor and a second gate positioned adjacent to the first gate, and between the supply electrode and the drain electrode to form a second portion of the transistor, wherein the second gate is also capacitively coupled to the semiconductor element.

Abstract: A photo-detector comprising: a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers from the photo absorbing layer to the contact area and block the flow of thermalized majority carriers from the photo absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, and conductance band energy levels of the barrier and photo absorbing layers are equalized.

Abstract: A group III-V nitride-based semiconductor substrate has: a first layer made of GaN single crystal; and a second layer formed on the first layer, the second layer made of group III-V nitride-based semiconductor single crystal represented by AlxGa1-xN, where 0<x?1, wherein a top surface and a back surface of the substrate are flattened.

Abstract: A method of manufacturing a field effect transistor of the present invention includes: applying a coating liquid 20 containing a solvent 13 as well as first and second organic molecules 11 and 12 that have been dissolved in the solvent 13; and forming a first layer and a second layer by removing the solvent 13 contained in the coating liquid 20 that has been applied. The first layer contains the first organic molecules 11 as its main component. The second layer adjoins the first layer and contains the second organic molecules 12 as its main component. The first organic molecules 11 are a semiconductor material or a precursor of a semiconductor material. The second organic molecules 12 are an insulator material or a precursor of an insulator material. The first organic molecules 11 and the second organic molecules 12 are not compatible with each other.

Abstract: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.

Abstract: A semiconductor optical device includes a GaAs substrate of a first conductivity type; a III-V compound semiconductor layer provided on the GaAs substrate; an active layer provided on the III-V compound semiconductor layer; and a cladding layer of a second conductivity type provided on the active layer, wherein the band gap energy of the III-V compound semiconductor layer is larger than the band gap energy of the GaAs substrate, wherein the band gap energy of the active layer is smaller than the band gap energy of the GaAs substrate, and wherein the thickness of the III-V compound semiconductor layer is not more than 0.2 ?m.

Abstract: A compound semiconductor epitaxial substrate and a process for producing the same are provided. The compound semiconductor epitaxial substrate comprises a single crystal substrate, a lattice mismatch compound semiconductor layer and a stress compensation layer, wherein the lattice mismatch compound semiconductor layer and the stress compensation layer are disposed on the identical surface side of the single crystal substrate, there is no occurrence of lattice relaxation in the lattice mismatch compound semiconductor layer, as well as the stress compensation layer, and Ls representing the lattice constant of the single crystal substrate, Lm representing the lattice constant of the lattice mismatch compound semiconductor layer, and Lc representing the lattice constant of the stress compensation layer satisfy the formula (1a) or (1b).

Abstract: An integrated circuit includes a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon. The integrated circuit also includes a single transistor dynamic random access memory (1T DRAM) cell arranged adjacent to and integrated with the bulk IC.

Abstract: A semiconductor chip for producing a controllable frequency is disclosed, for example in transceivers. The semiconductor chip includes a voltage-controlled oscillator located in a first chip region of the semiconductor chip, a heat source, in particular in the form of a power amplifier and/or in the form of a phase-locked loop, that is located in a second chip region of the semiconductor chip, and contacts for contacting the semiconductor chip in a bonding process. At least a part of the contacts is located between the first and second chip regions in such a manner that it functions as thermal shielding between the first and second chip regions.

Abstract: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

Abstract: A pixel having a MOS-type transistor formed in and above a semiconductor substrate of a first doping type, a buried semiconductor layer of a second doping type being placed in the substrate under the MOS transistor and separated therefrom by a substrate portion forming a well. The buried semiconductor layer comprises a thin portion forming a pinch area placed under the transistor channel area and a thick portion placed under all or part of the source/drain areas of the transistor.

Abstract: A circuit comprises a bulk silicon integrated circuit (IC). A first metallization layer is arranged adjacent to said bulk silicon IC. Phase change memory (PCM) is arranged adjacent to said first metallization layer and comprises a plurality of PCM cells each including a phase-change material, a heater that selectively heats said phase-change material, and a diode in series with said phase-change material.

Abstract: An MTJ MRAM cell is formed by using a reactive ion etch (RIE) to pattern an MTJ stack on which there has been formed a bilayer Ta/TaN hard mask. The hard mask is formed by patterning a masking layer that has been formed by depositing a layer of TaN over a layer of Ta on the MTJ stack. After the stack is patterned, the TaN layer serves at least two advantageous purposes: 1) it protects the Ta layer from oxidation during the etching of the stack and 2) it serves as a surface having excellent adhesion properties for a subsequently deposited dielectric layer.

Abstract: A solid-state imaging device is disclosed. In the solid-state imaging device, plural unit areas, each having a photoelectric conversion region converting incident light into electric signals are provided adjacently, in which each photoelectric conversion region is provided being deviated from the central position of each unit area to a boundary position between the plural unit areas, a high refractive index material layer is arranged over the deviated photoelectric conversion region, and a low refractive index material layer is provided over the photoelectric conversion regions at the inverse side of the deviated direction being adjacent to the high refractive index material layer, and optical paths of the incident light are changed by the high refractive index material layer and the low refractive index material layer, and the incident light enters the photoelectric conversion region.

Abstract: A three-dimensional integrated device includes at least two integrated circuit substrates laminated to each other, each of the integrated circuit substrates having at least one ground plane, at least one aperture provided at a desired location in the ground plane, the end of a microstrip line formed in a pair with the ground plane and placed in the aperture, and a transmitter and/or a receiver that is connected to the microstrip line and transmits and/or receives signals at a frequency substantially corresponding to the perimeter ? of the aperture. Each of the apertures in each of the integrated circuit substrates is superimposed on at least one of the apertures in the other integrated circuit substrates in the direction perpendicular to the ground planes, and the signals are transported in a contactless manner between the integrated circuit substrates through the apertures at a frequency substantially corresponding to the perimeter ? of the apertures.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes an offset body region.

Abstract: A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the multi-step gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure. The channel length of the multi-step gate structure is the summation of the lateral width and the vertical depth of the multi-step gate structure, which is dramatically increased such that problems originated from the short channel effect can be effectively solved. Further, the plurality of doped regions under the multi-step structure are prepared by implanting processes having different dosages and dopants, which can control the thickness of the gate oxide layer and the threshold voltage of the multi-step gate structure.

Abstract: This disclosure concerns a method of manufacturing a semiconductor device including preparing a support substrate including a surface region consisting of a semiconductor single crystal; forming a porous semiconductor layer by transforming the surface region of the support substrate into a porous layer; epitaxially growing a single-crystal semiconductor layer on the porous semiconductor layer; forming an opening reaching the porous semiconductor layer by removing a part of the single-crystal semiconductor layer; forming a cavity between the single-crystal semiconductor layer and the support substrate by removing the porous semiconductor layer through the opening; and filling the cavity with an insulating film or a conductive film.

Abstract: Provided is a technology capable of manufacturing, in a short TAT, a mask ROM having a small memory cell area and high reliability. According to the manufacturing method of a semiconductor integrated circuit device according to the present invention, a memory cell is formed of a first MISFET equipped with an n type gate electrode composed of a polycrystalline silicon film having an n conductivity type impurity introduced therein and a second MISFET equipped with a p type gate electrode composed of a polycrystalline silicon film having a p conductivity type impurity introduced therein. In the n type gate electrode and p type gate electrode, an n conductivity type impurity is introduced further, whereby a threshold voltage of the first MISFET is made lower than that of the second MISFET.

Abstract: A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

Abstract: A MOS transistor includes an etch stop layer presenting a density of less than a determined threshold value, below which the material of said stop layer is permeable to molecules of dihydrogen and/or water. The material may comprise a nitride. A material used for the etch stop layer preferably has a density value of less than about 2.4 g/cm3.

Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least a gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises an at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

Abstract: A double-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is fabricated from a silicon-on-insulator (SOI) substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A photodiode set is formed in the SOI substrate, including a first and second photodiode formed as a double-junction structure in the Si substrate. A third photodiode is formed in the Si top layer. A (imager sensing) transistor set is formed in the top Si layer. The transistor set is connected to the photodiode set and detects an independent output signal for each photodiode. The transistor set may be an eight-transistor (8T), a nine-transistor (9T), or an eleven-transistor (11T) cell.

Abstract: A backside imaging device includes a bump that is disposed overlapping with a sensor array region or a photodiode in a planar view. By this configuration, the bump becomes a support, and the semiconductor substrate is prevented from being damaged because of a bending applied to the semiconductor substrate.

Abstract: A ferroelectric memory device is equipped with a ferroelectric capacitor having a first electrode, a second electrode, and a ferroelectric layer between the first and second electrodes, and the ferroelectric memory device includes: a wiring that is connected to one of the first electrode and the second electrode, wherein the wiring includes a first wiring layer composed of titanium nitride oriented along a <111> direction, and a second wiring layer formed on the first wiring and composed of titanium aluminum nitride orientated along a <111> direction.

Abstract: A memory cell in a nonvolatile semiconductor memory device includes a tunneling insulating film, a floating gate electrode made of a Si containing conductive material, an inter-electrode insulating film made of rare-earth oxide, rare-earth nitride or rare-earth oxynitride, a control gate electrode, and a metal silicide film formed between the floating gate electrode and the inter-electrode insulating film.

Abstract: There is provided a semiconductor storage device including a substrate area, a first and a second isolation area, a first well area where the first transistor is placed, a second well area where the second transistor to output a first voltage to bring the first transistor into non-conduction is placed, and a third well area where the third transistor to output a second voltage to bring the first transistor into conduction is placed. The second and third well areas and the second isolation area are formed between two of the first well area, the second isolation area is formed between the second well area and one of the first well area, and the third well area is formed between the second well area and another one of the first well area.

Abstract: Provided is an electric double layer capacitor including a large capacity single cell having a large electrostatic capacity and a small capacity single cell are connected to the same exterior case in parallel, and a thickness of a separator of the large capacity single cell is made thicker than a thickness of a separator of the small capacity single cell. With this structure, a supply amount of an electrolyte solution to the large capacity single cell is markedly increased compared with the small capacity single cell, thereby being capable of preventing degradation of the large capacity single cells and the small capacity single cells and providing the electric double layer capacitor having an excellent cycle life and having a large power storage amount while keeping characteristics capable of instantaneously allowing large current to flow.

Abstract: In a semiconductor device in which a semiconductor element 10 in which plural electrode terminals 16 are formed along the peripheral edge inside a region of a predetermined width along the peripheral edge excluding the center and the vicinity of the center is mounted on a pad formation surface of a substrate 12 on which pads 14 corresponding to each of the electrode terminals 16 are formed and connection parts 26 between the semiconductor element 10 and the substrate 12 are sealed with an underfill material 24, it is wherein a dam 20 surrounding an inward region 28 is formed so as to separate a connection part region in which the connection parts 26 are present from the inward region 28 inward beyond the connection part region and the connection part region is sealed with the underfill material 24 and plural through holes 22 extending through the substrate 12 are formed inside the inward region 28 of the substrate 12 surrounded by the dam 20.

Abstract: Capacitors configured in a switched-capacitor circuit on a semiconductor device may comprise very accurately matched, high capacitance density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer as a shield, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining.

Abstract: A nonvolatile semiconductor memory device according to the embodiments of the invention includes a first insulating film on a channel, a floating gate electrode on the first insulating film, a second insulating film on the floating gate electrode, and a control gate electrode on the second insulating film. Each of the first and second insulating films comprises at least two layers, one layer directly in contact with the floating gate electrode is formed by an insulating material (A) including a metal element having a d-orbital, and the other at least one layer is formed by an insulating material (B) chiefly including one of a metal element without the d-orbital, and a semiconductor element.

Abstract: A memory cell has a control gate electrode disposed on a main surface of a semiconductor substrate through a gate insulating film, an ONO film disposed along a side surface of the control gate electrode and the main surface of semiconductor substrate, a memory gate electrode disposed on a side surface of the control gate electrode and also on the main surface of the semiconductor substrate through the ONO film. The control gate electrode and the memory gate electrode are formed, over the upper portions thereof, with a silicide film and an insulating film formed by oxidation of the surface of the silicide film, respectively.

Abstract: A non-volatile memory cell is made in a substrate of a substantially single crystalline semiconductive material having a first conductivity type and a surface. A trench is in the surface and extends into the substrate to a first depth and to a second depth, which is deeper than the first depth. The trench has a first sidewall along the trench extending to the first depth, and a second sidewall along the trench extending from the first depth to the second depth, and a bottom wall along the bottom of the trench. A first region of a second conductivity type is in the substrate, along the bottom of the trench. A second region of the second conductivity type is in the substrate, along the surface of the trench. A channel region is in the substrate between the first region and the second region; the channel region has a first portion and a second portion, with the first portion between the surface and the first depth and is along the first sidewall.

Abstract: A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.

Abstract: It is an object of the present invention to provide a semiconductor device that enables cost increase to be inhibited and enables cell size to be reduced, and a method for manufacturing the same. A semiconductor device includes a semiconductor substrate, a gate electrode, a first sidewall, and a second sidewall. The gate electrode is formed above the semiconductor substrate. The first sidewall is formed above the semiconductor substrate to be adjacent to the gate electrode. The second sidewall is formed above the semiconductor substrate to face the first sidewall across the gate electrode. The first sidewall includes a first sloping surface. The first sloping surface faces the gate electrode. The first sloping surface slopes so as to close the gap with a second sidewall as it gets closer to the semiconductor substrate. The first sidewall includes a second sloping surface. The second sloping surface faces the gate electrode.

Abstract: A semiconductor device includng: a well layer that is formed on a semiconductor substrate; a first impurity diffusion layer that is formed on the well layer; a floating gate that is formed on the well layer in one region isolated from the first impurity diffusion layer, with a gate insulating film therebetween, and that is drawn over the first impurity diffusion layer and over the well layer in other region isolated from the first impurity diffusion layer, respectively; a source or drain layer that is formed on the well layer in such a manner that the source or drain layer sandwiches the floating gate disposed on the gate insulation film with another source or drain layer and in isolation from the first impurity diffusion layer; and a second impurity diffusion layer that is formed on the well layer adjacently to the other region, the well layer being of a first conductivity type while the source or drain layer, the first impurity diffusion layer and the second impurity diffusion layer being each of a second c

Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

Abstract: Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.

Abstract: A static random access memory (SRAM) unit comprising a substrate, a gate dielectric layer, a gate, a trench capacitor, a pair of source/drain regions, a first contact and a second contact is provided. The substrate has a trench formed therein. The gate dielectric layer is disposed on the substrate and the gate is disposed on the gate dielectric layer. The trench capacitor is disposed in the trench near one side of the gate. The source/drain regions are disposed in the substrate near the respective sides of the gate with one of the source/drain region positioned between the gate and the trench capacitor. The first contact is electrically connected to the trench capacitor and the second contact is electrically connected to the other source/drain region.

Abstract: Thinning a semiconductor substrate has been needed for reducing on-resistance in a semiconductor device such as a vertical MOS transistor, IGBT, or the like where a high current flows in the semiconductor substrate in a vertical direction. In this case, the thinning is performed to the extent that the semiconductor substrate does not warp with a heat treatment, so that there is a limitation in reduction of on-resistance. In the invention, openings such as trench holes are formed on a back surface side of a semiconductor substrate. Then, a drain electrode is formed being electrically connected with bottoms of these openings. In this case, a current path is formed short corresponding to the depths of the openings, thereby easily achieving low on-resistance.

Abstract: A low voltage power device includes a plurality of quasi-vertical LDMOS device cells. A conductive trench sinker is formed through the epitaxial layer and adjacent a selected one of the source and drain regions in each cell. The trench sinker electrically couples the selected one of the source and drain regions to the substrate for coupling current from the channel to the substrate. The resulting device exhibits a vertical current flow between the metal electrode covering the front surface and the second electrode formed at the back side of the wafer. The device cells are arranged in a closed cell configuration.