Abstract: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.

Abstract: The substrate successively comprises a base, a diamond-like carbon layer, a dielectric layer and a semi-conducting material layers which is designed to constitute microelectronic elements. A nucleation layer is preferably disposed between the base and the diamond-like carbon layer. The dielectric material is chosen such that the upper level of the valence band of the dielectric material is lower than the upper level of the valence band of the diamond-like carbon. The semi-conducting material is chosen such that the upper level of the valance band of the semi-conducting material is higher than the upper level of the valence band of the diamond-like carbon. The substrate can be achieved by successive depositions of by assembly of first and second stacks.

Abstract: A thin film transistor device with high symmetry is disclosed, in which the symmetrical structure of transistor is utilized to enable currents flowing in the channels of each transistor formed on a polysilicon film of a specific crystallization direction to pass the same amount of grain boundaries, thereby improving the uniformity of electrical characteristics of the device. By the thin film transistor device of the invention, not only the freedom of circuit design is increased, but also the circuit area of a TFT device occupied is reduced.

Abstract: In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity

Abstract: The semiconductor device which has the resistor element which was formed in the SOI layer of an SOI substrate and suppressed the influence of leak to the minimum is obtained. N+ diffusion region is selectively formed in an SOI layer, and a full isolation region is formed covering all the peripheral regions of N+ diffusion region. A full isolation region penetrates an SOI layer, and reaches a buried oxide film, and N+ diffusion region is electrically thoroughly insulated from the outside by the full isolation region. N+ diffusion region extends in the longitudinal direction in a drawing, and is formed in lengthwise rectangular shape in plan view. And a silicide film is formed in the front surface at the side of one end of N+ diffusion region, a silicide film is formed in the front surface at the side of the other end, and a metal plug is formed on a silicide film, respectively.

Abstract: Provided is a light control device including: a thin film transistor; and a light control element including an electrode electrically connected to the thin film transistor, in which a semiconductor region of the thin film transistor and an pixel electrode are composed of the same semiconductor layer, and the same semiconductor layer is an amorphous oxide layer including at least one of In, Ga, and Zn.

Abstract: A new communications system is described in which the phased array heater used to create an artificial ionized plasma pattern in the atmosphere (AIPA) has an integrated phased array transmitter. By combining these two functions a simplified telecommunications system is created. The new system is called the Integrated Plasma Mirror. Another advantage is that a portion of the telecommunications signal is absorbed in the plasma pattern and contributes to the maintenance power level.

Abstract: An exemplary computer includes a host machine, and a display device. The host machine defines a recessed portion in a side panel thereof to receive the display device therein. The display device includes a frame, and an LCD panel installed in the frame. The recessed portion includes a pair of elongated grooves defined in one pair of sidewalls thereof, and a plurality of vents defined in a base wall thereof. The frame includes a pair of posts extending from side portions thereof to engage in the elongated grooves. The posts are surrounded with resilient materials and tightly received in the elongated grooves in an interferential fit. The display device is pivotable about more than one axis relative to the host machine.

Abstract: A semiconductor device includes a diode region having a plurality of protection diodes and a pad region overlapped with an upper part of the diode region. The pad region having a pad installed corresponding to an external connection terminal. The semiconductor device further includes a contact plug unit which connects at least one of a plurality of active regions constituting the diode region and the pad within the diode region.

Abstract: A disclosed semiconductor device includes: a semiconductor substrate; at least one normal transistor disposed on the semiconductor substrate; and at least one LOCOS offset transistor disposed on the semiconductor substrate. The normal transistor has an LDD region between a channel and a source and between the channel and a drain. And the LOCOS offset transistor has no LDD region between a channel and a source and between the channel and a drain.

Abstract: A manufacturing method of a semiconductor device according to an embodiment of this invention, includes: forming a gate dielectric film on a substrate and forming a gate electrode layer for a P-type FET on the gate dielectric film, ranging from a P-type FET region to a N-type FET region; in the P-type FET region and the N-type FET region, processing the gate electrode layer for the P-type FET, to form a gate electrode for the P-type FET in the P-type FET region, and to form a dummy gate electrode in the N-type FET region; and in the N-type FET region, forming a trench by removing the dummy gate electrode on the gate dielectric film, and forming a gate electrode for the N-type FET on the gate dielectric film by burying a gate electrode material in the trench.

Abstract: The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide.

Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.

Abstract: A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped region is placed under semiconductor devices of the first polarity and under the well region contact region. Additionally, the structure may further include a deep trench (DT) structure and trench isolation (TI) structure to further improve latchup robustness.

Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

Abstract: A magnetic tunneling junction structure for magnetic random access memory is disclosed. A composite structure includes at least a pinning layer, a barrier layer, a ferromagnetic layer and a free layer, and the material of the pinning layer and the free layer are perpendicularly anisotropic ferrimagnetic. As the structures include of several barrier layers, free layers and ferrimagnetic layers, that lower coercivity and high squareness for the hysteresis curves can be obtained, and reduction of the coercivity of the free layer can be achieved.

Abstract: It is made possible to reduce the contact resistance of the source and drain in an n-type MISFET. A semiconductor device includes: a source and drain regions provided in a p-type semiconductor substrate so as to separate each other, each including: a silicide layer containing a first metal element as a main component having a vacuum work function of 4.6 eV or greater; and a layer containing at least one second metal element selected from the group of scandium elements and lanthanoid, the layer containing the second metal element including a segregating layer in which the highest areal density is 1×1014 cm?2 or higher, each region of the segregating layer with areal density of 1×1014 cm?2 or higher having a thickness smaller than 1 nm; a gate insulating film provided a region between the source and drain regions on the semiconductor substrate; and a gate electrode provided on the gate insulating film.

Abstract: A gate dielectric structure and an organic thin film transistor based thereon, wherein the gate dielectric structure comprises: an organic-inorganic composite layer and an organic insulation layer, and the gate dielectric structure is applied to an organic thin film transistor. As the organic-inorganic composite layer of the gate dielectric structure has an organic insulation matrix blended with inorganic surface-modified particles, it can achieve a high dielectric constant. Further, as the organic insulation layer can modify the surface of the organic-inorganic composite layer, not only the leakage current is reduced, but also the crystalline structure of the organic semiconductor layer becomes more orderly. Thus, the carrier mobility is raised, the current output of the element is increased, and the performance of the element is also greatly enhanced.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

Abstract: A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the channel region, a first conductive layer pattern may be on the insulating layer, and a second conductive layer pattern may be on the first conductive layer pattern. The insulating layer pattern may be between the first conductive layer pattern and the channel region, and the first conductive layer pattern may include boron doped polysilicon with a surface portion having an accumulation of silicon boronide. The first conductive layer pattern may be between the second conductive layer pattern and the insulating layer pattern, and the second conductive layer pattern may include tungsten. Related methods are also discussed.

Abstract: Fabrication methods disclosed herein provide for a nanoscale structure or a pattern comprising a plurality of nanostructures of specific predetermined position, shape and composition, including nanostructure arrays having large area at high throughput necessary for industrial production. The resultant nanostracture patterns are useful for nanostructure arrays, specifically sensor and catalytic arrays.

Abstract: A method of manufacturing a vertical comb structure for a micro electromechanical (MEMS) device. Tooth structures are formed on a first wafer. A second wafer is then bonded to the tooth structures of the first wafer. The tooth structures are then released to form a comb structure. Forming the tooth structures on the first wafer includes using oxidation, photolithography, etching, epitaxy, and chemical and mechanical polishing to create the tooth structures on the first wafer.

Abstract: A microelectromechanical system (MEMS) assembly comprises a MEMS transducer, an integrated circuit (IC), and a substrate. The integrated circuit and the MEMS transducer are being electrically coupled to the substrate. The substrate may be a single layer or multiple layers. A coupling circuit resides in the substrate and may comprise a low pass filter (LPF) to provide a path to ground for undesirable co-propagating RF signals while allow direct current (DC) or low frequency signals to pass through the IC.

Abstract: A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced.

Abstract: Structure for capacitive micromachined ultrasonic transducer (CMUT) device or other vibrating membrane device having non-uniform membrane so that membrane mass and stiffness characteristics may be substantially independently adjusted. CMUT having trenched membrane and/or membrane with non-uniform thickness or density. Method for operating transducer or vibrating membrane device. Array of devices at least some of which have non-uniform membrane properties. CMUT comprising substrate, support for membrane, and membrane extending over support to create cavity, membrane having non-uniform membrane thickness resulting from at least one of: thickening on upper surface of the membrane outside of cavity, thickening on lower surface of membrane inside cavity, trench on upper surface of membrane, trench on lower surface of the membrane, and any combination of two or more of these. Method for fabricating CMUT or vibrating membrane device having non-uniform membrane.

Abstract: Provided is a micro-mechanical structure and method for manufacturing the same, including a hydrophilic surface on at least a part of a surface of the micro-mechanical structure, so as to prevent generation of an adhesion phenomenon in the process of removing a sacrificial layer to release the micro-mechanical, wherein the sacrificial layer comes into contact with the surface of the micro-mechanical structure.

Abstract: A piezoresistance element formed in a semiconductor substrate, includes a pair of contact regions formed in the semiconductor substrate; a groove formed between the pair of contact regions; a resistance layer formed in the groove, the resistance layer having a conductive type opposing to the semiconductor substrate; and a silicon layer formed on the resistance layer, the silicon layer having a conductive type corresponding to the semiconductor substrate.

Abstract: A system and a method for reducing critical current of magnetic random access memory (MRAM) are disclosed. The magnetic device includes at least a pinned layer, a spacer layer and a free layer, and the material of the pinned layer and the free layer is perpendicularly anisotropic ferrimagnetic. The spacer layer is an insulator. By the modified Landau-Lifshitz-Gilbert equations, the varying trend of the critical current can be estimated.

Abstract: A photodiode includes a semiconductor having front and backside surfaces and first and second active layers of opposite conductivity, separated by an intrinsic layer. A plurality of isolation trenches filled with conductive material extend into the first active layer, dividing the photodiode into a plurality of cells and forming a central trench region in electrical communication with the first active layer beneath each of the cells. Sidewall active diffusion regions extend the trench depth along each sidewall and are formed by doping at least a portion of the sidewalls with a dopant of first conductivity. A first contact electrically communicates with the first active layer beneath each of the cells via the central trench region. A plurality of second contacts each electrically communicate with the second active layer of one of the plurality of cells. The first and second contacts are formed on the front surface of the photodiode.

Abstract: An electro-optical device includes an insulating substrate, a switching element, at least one PIN diode, and at least one reflector. The switching element includes a first polysilicon semiconductor layer formed on the insulating substrate, and a gate electrode formed between the insulating substrate and the first semiconductor layer. Each of the at least one PIN diode includes a second polysilicon semiconductor layer formed on the insulating substrate. The at least one reflector is formed in the same layer as the gate electrode and opposite the second semiconductor layer or layers of the at least one PIN diode.

Abstract: A semiconductor device having a unit capable of temporarily storing electrical signals, may include an electrical signal generation unit, a first signal transmission unit electrically connected to the electrical signal generation unit, a first signal storage unit electrically connected to the first signal transmission unit, a second signal transmission unit electrically connected to the first signal storage unit, a second signal storage unit electrically connected to the second signal transmission unit, a reset unit electrically connected to the second signal storage unit, an amplification unit electrically connected to the second signal storage unit, a selection unit electrically connected to the amplification unit, and an output unit electrically connected to the selection unit, for stable signal processing.

Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.

Abstract: An image sensor package structure includes a plastic substrate, frame layer, a chip, wires, a transparent layer, and an encapsulate layer. The plastic substrate has an upper surface, which is formed with first electrodes, and a lower surface, which is formed with second electrodes. The frame layer is arranged on the upper surface of the plastic substrate, a cavity is formed between the plastic substrate and the frame layer. The chip is mounted on the upper surface of the plastic substrate, and is located within the cavity. The plurality of wires are electrically connected the chip to the first electrodes of the plastic substrate. The transparent layer is mounted on the frame layer to cover the chip. And the encapsulate layer is encapsulated the frame layer, and is covered on the periphery the transparent layer.

Abstract: A compact resistive thermal sensor is provided for an integrated circuit (IC), wherein different sensor components are placed on different layers of the IC. This allows the lateral area needed for the sensor resistance wire on any particular IC layer to be selectively reduced. In a useful embodiment, a plurality of first linear conductive members are positioned in a first IC layer, in spaced-apart parallel relationship with one another. A plurality of second linear conductive members are similarly positioned in a second IC layer in spaced-apart parallel relationship with one another, and in orthogonal relationship with the first linear members or in parallel with existing wiring channels of the second IC layer. Conductive elements respectively connect the first linear members into a first conductive path, and the second linear members into a second conductive path.

Abstract: According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, a lower electrode film formed on the semiconductor substrate, a dielectric film formed on the lower electrode film, and an upper electrode film formed on the dielectric film, wherein the lower electrode film, the dielectric film and the upper electrode film construct a capacitor in a predetermined region on the semiconductor substrate, the dielectric film is separated from the upper electrode film outside the predetermined region, and the dielectric film is formed continuously with respect to an adjacent cell.

Abstract: Aiming at obtaining stable and uniform element isolation characteristics without forming the oxide film liner or the like on the inner wall surface of the isolation trench, and ensuring a sufficient level of adhesiveness of the insulating material filled in the isolation trench, and obtaining uniform and excellent element isolation characteristics and a sufficient level of adhesiveness of the buried insulating material, even when applied to large-diameter semiconductor substrates, a thermal oxide film is formed on the inner wall surface of isolation trenches, and a silicon semiconductor substrate is then annealed using a lamp annealer at a temperature higher than in the process of forming thermal oxide film, typically at 950° C. for a predetermined short time (30 seconds herein, for example), wherein the annealing modifies at least the surficial portion of thermal oxide film to have a further complete and uniform state of oxidation.

Abstract: The specification describes an integrated passive device (IPD) that is formed on a silicon substrate covered with an oxide layer. Unwanted accumulated charge at the silicon/oxide interface are rendered immobile by creating trapping centers in the silicon surface. The trapping centers are produced by a polysilicon layer interposed between the silicon substrate and the oxide layer.

Abstract: Provided is a resistance random access memory (RRAM) device and a method of manufacturing the same. A resistance random access memory (RRAM) device may include a lower electrode, a first oxide layer on the lower electrode and storing information using two resistance states, a current control layer made of a second oxide on the first oxide layer and an upper electrode on the current control layer.

Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.

Abstract: A SiGe-HBT having a base region made of SiGe mixed crystal. The base region includes: an intrinsic base region having junctions with a collector region and an emitter region; and an external base region for connecting the intrinsic base region with a base electrode. The intrinsic base region and the external base region are doped with a first impurity of a given conductivity type. The external base region is further doped with a second impurity. As the first impurity, an element smaller in atomic radius than Si (such as boron, for example) is selected, and as the second impurity, an element larger in atomic radius than the first impurity (such as Ge, In and Ga, for example) is selected.

Abstract: A vertical semiconductor power switch has a semiconductor body having a first surface and a second surface. At least one anode and one control electrode are positioned on the first surface and at least one cathode is positioned on the second surface. The cathode comprises a multi-layer contact structure which comprises an inner contact layer positioned directly on the second surface of the semiconductor body, and an outermost layer consisting essentially of a Ni-alloy.

Abstract: Bipolar power semiconductor component comprising a p-type emitter and more highly doped zones in the p-type emitter, and production method The invention relates to a bipolar power semiconductor component comprising a semiconductor body (1), in which a p-doped emitter (8), an n-doped base (7), a p-doped base (6) and an n-doped main emitter (5) are arranged successively in a vertical direction (v). The p-doped emitter (8) has a number of heavily p-doped zones (82) having a locally increased p-type doping. The invention furthermore relates to a method for producing a power semiconductor component.

Abstract: A method of forming an iron-doped gallium nitride for a semi-insulating GaN substrate is provided. A substrate 1, such as a sapphire substrate having the (0001) plane, is placed on a susceptor of a metalorganic hydrogen chloride vapor phase apparatus 11. Next, gaseous iron compound GFe from a source 13 for an iron compound, such as ferrocene, and hydrogen chloride gas G1HCl from a hydrogen chloride source 15 are caused to react with each other in a mixing container 16 to generate gas GFeComp of an iron-containing reaction product, such as iron chloride (FeCl2). In association with the generation, the iron-containing reaction product GFeComp, first substance gas GN containing elemental nitrogen from a nitrogen source 17, and second substance gas GGa containing elemental gallium are supplied to a reaction tube 21 to form iron-doped gallium nitride 23 on the substrate 1.

Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 ?m. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.

Abstract: Embodiments of the invention provide a substrate with a first layer having a first crystal orientation on a second layer having a second crystal orientation different than the first crystal orientation. The first layer may have a uniform thickness.

Abstract: A novel chip packaging structure is disclosed. The chip packaging structure includes a flip chip having a chip backside, at least one concave stress-relieving structure provided in the chip backside, a carrier substrate bonded to the flip chip and an adhesive material interposed between the flip chip and the carrier substrate. During thermal testing and/or functioning of the flip chip, the stress-relieving structure reduces stresses between the flip chip and the carrier substrate and dissipates heat from the flip chip to reduce thermally-induced delamination stresses applied to the adhesive material and thereby enhances reliability of the flip chip.

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract: A phase change memory device and method of forming a phase change memory device is disclosed. The method includes forming a memory device with a plurality of memory cells, each memory cell having a pillar containing a region of an active material, said method comprising the steps of: depositing at least a thermally insulating base layer on a surface that comprises said pillars; depositing a top layer on top of said base layer, said base layer having a higher resistance against polishing than said top layer; and planarizing a top surface by polishing such that at least the parts of said base layer above said pillars are exposed. The invention further relates to a memory device fabricated by this method.

Abstract: A semiconductor device includes a plurality of semiconductor chips packaged in a common housing. The semiconductor chips include signal pads to pass critical signals to respective chips and are terminated by a terminating resistance. At least one set of signal pads, arranged on different chips and in close proximity to one another, are connected and pass the same signal. The signal pads are terminated by the terminating resistance.

Abstract: A semiconductor chip assembly comprises a semiconductor chip including a first contact and a second contact positioned at a first side of the first contact, a first lead including an inner end, a second lead including a body positioned at a second side of the first lead and an inner segment positioned between the contacts of semiconductor chip and the inner end of the first lead, a first bonding wire connecting the first contact to the inner end of the first lead and a second bonding wire connecting the second contact and the inner segment of the second lead. The first side of the first contact is in the opposite direction to the second side of the first lead, and the first bonding wire and the second bonding wire do not cross each other. Preferably, the second lead further includes a middle portion between the body and the inner segment, or the second lead is L-shaped.