Abstract: A method to manufacture a package that encases at least one integrated circuit device and the package so manufactured. The method includes the steps of (1) providing a leadframe having a die pad, leads, at least one ring circumscribing the die pad and disposed between the die pad and the leads, a plurality of tie bars projecting outwardly from the at least one ring, and at least one connecting bar electrically interconnecting and mechanically supporting the die pad to the ring; (2) affixing the at least one integrated circuit device to a first side of the die pad and electrically interconnecting the at least one integrated circuit device to the leads and to the at least one ring; (3) encapsulating the at least one integrated circuit device, the first side of the die pad and a first side of the ring in a molding resin while retaining an opposing second side of the ring external to said molding resin; and (4) severing the at least one connecting bar to electrically isolate the die pad from the ring.

Abstract: A tape with a chip-bonding area is provided. The tape is suitable for a chip on film configuration, wherein a chip is suitable for being disposed on the tape and in the chip-bonding area. The tape includes a dielectric base film, a first wiring pattern, and at least a second wiring pattern. The first wiring pattern is disposed on the dielectric base film and has multiple inner leads disposed in the chip-bonding area. The second wiring pattern is disposed on the dielectric base film and in the chip-bonding area. The chip is suitable for being electrically connected to at least a part of the inner leads and being disposed above the second wiring pattern.

Abstract: A wafer treating method for making adhesive chips is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform an adhesive film having B-stage property which has a glass transition temperature between ?40 and 175 degree C. for example. After positioning the wafer, the wafer is singulated to form a plurality of chips with adhesive for chip-to-chip stacking, chip-to-substrate or chip-to-lead frame attaching.

Abstract: A chip package structure including a carrier, a chip, first bonding wires, second bonding wires, and an encapsulant is provided. The carrier has first contacts and at least one second contact, and the chip has at lease one first bonding pad and at least one second bonding pad. In addition, the first bonding wire electrically connects the first bonding pad and the first contact, and the second bonding wire electrically connects the second bonding pad and the second contact, wherein each of the first bonding pads electrically connects at least two first contacts through at least two first bonding wires, and each second bonding pad electrically connects the second contact through one single second bonding wire. Further, the encapsulant is disposed on the carrier to encapsulate the chip, the first bonding wires, and the second bonding wires.

Abstract: An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are connected to at least one of bond pads with a single bond wire. A single bond wire is ball or wedge bonded to a first bond pad or inner lead and subsequently wedge bonded to one or more second bond pads or inner leads, then it is connected to a third or last bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and/or inner lead(s). The bond pad(s) of the die and/or inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: Manufacturing processes of a leadframe-based BGA package and a leadless leadframe implemented in the processes are disclosed. The leadless leadframe has a plurality of bottom leads and a plurality of top soldering pads formed in different layers. After encapsulation and before solder ball placement, a half-etching process is performed to remove the bottom leads to make the top soldering pads electrically isolated, exposed and embedded in the encapsulant for solder ball placement where the soldering area of the top soldering pads is defined without the need of solder mask(s) to solve the diffusion of solder balls on the leads during reflow. Moreover, mold flash can easily be detected and removed. The overall package cost can be reduced.

Abstract: An electronic component has at least one semiconductor power switch with at least one anode and at least one control electrode positioned on a first surface and at least one cathode positioned on a second surface and a heat sink with a die attach region with an upper surface. The electronic component also comprises a plurality of leads. A control lead has an upper surface which lies in a plane generally coplanar with the upper surface of the die attach region in its inner portion and above the upper surface of the inner portion in its centre portion. The anode of the semiconductor power switch is mounted on the die attach region of the heat sink and at least one control electrode is mounted on the upper surface of the inner portion of the control lead.

Abstract: A power semiconductor package that includes a die having one electrode thereof electrically and mechanically attached to a web portion of a conductive clip.

Abstract: A LED package structure is disclosed. The LED package structure includes a substrate, a light emitting diode, a plasma chemical vapor deposition layer and a transparent material layer, wherein the substrate has a plurality of contacts. The light emitting diode is disposed on the substrate and electrically contacted to the contacts. The plasma chemical vapor deposition layer is disposed on the light emitting diode and the refractive index of the plasma chemical vapor deposition layer is smaller than that of the light emitting diode. The transparent material layer is disposed on the plasma chemical vapor deposition layer and the refractive index of the transparent material layer is smaller than that of the plasma chemical vapor deposition layer.

Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a base plate, an insulating substrate on the base plate, and a wiring patterned layer on the insulating substrate. Also, it includes at least one semiconductor chip bonded on the wiring patterned layer, the semiconductor chip having a surface electrode. A main terminal is connected via a conductive adhesive layer onto at least either one of the surface electrode and the wiring patterned layer. Also, a resin package covers the insulating substrate, the wiring patterned layer, the semiconductor chip, the conductive adhesive layer, and at least a portion of the main terminal.

Abstract: The purpose of the present invention is to provide a cover tape for packaging semiconductor device which protects the outer shape of the semiconductor device, and is capable of improving the mounting speed of the semiconductor device by shipment in tape, and a package for semiconductor device using the cover tape for packaging semiconductor device. The cover tape for packaging semiconductor device of the present invention has a net-like structure 20 at least in a portion, and the cover tape for packaging semiconductor device is pasted onto an embossed tape which has a number of pockets containing semiconductor devices so as to cover the pockets. The package for semiconductor device of the present invention contains an embossed tape which has a number of pockets which contain semiconductor devices, and the cover tape for packaging semiconductor device of the present invention.

Abstract: According to this invention, a semiconductor package includes: a plurality of semiconductor chips, each having through electrodes; and a semiconductor interposer, on which the plurality of semiconductor chips are mounted. Each of the semiconductor chips includes: a semiconductor substrate; a wiring layer formed on the semiconductor substrate; an opaque resin layer sealing the wiring layer and a side surface of the semiconductor chip; and conductive bumps to be connected to the through electrodes.

Abstract: Plural via portions formed on a package substrate of a BGA include a first through-hole portion extended in the plane direction by an extension wiring connected to a land portion and a second through-hole portion that is arranged on the land portion serving as pad-on-via, whereby high-density wiring and multi-function of the BGA can be realized by using the package substrate having a two-layer wiring structure. Accordingly, cost for the package substrate can be reduced, and hence, cost for the BGA can be reduced, compared to a multi-layer wiring structure having four or six wiring layers.

Abstract: A semiconductor package with an enhancing layer is provided. The package includes a leadframe, a chip, several bumps and an enhancing layer. The leadframe includes several leads. Several bonding pads are disposed on a surface of the chip. The bumps connect the bonding pads of the chip and the leads of the leadframe. The enhancing layer covers the leads and the bumps. The enhancing layer including copper is formed by electroplating. Or, the melting point of the enhancing layer is greater than the melting points of lead and tin.

Abstract: A blank and a semiconductor device are include a composite panel with semiconductor chips embedded in a plastic package molding compound. The blank includes a composite panel with semiconductor chips arranged in rows and columns in a plastic package molding compound with active upper sides of the semiconductor chips forming a coplanar surface area with the upper side of the composite panel. The blank further includes an orientation indicator impressed into the plastic package molding compound when the semiconductor chips are embedded within the molding compound.

Abstract: An integrated circuit package-in-package system is provided forming a first integrated circuit package having a first interface, stacking a second integrated circuit package having a second interface above the first integrated circuit package, fitting the first interface and the second interface, and attaching a third integrated circuit package on the second integrated circuit package.

Abstract: A integrated circuit package on package system is provided including providing a base substrate having a base stackable connection, attaching a base integrated circuit on the base substrate, forming a stackable package including the base integrated circuit encapsulated with the base stackable connection partially exposed, and attaching a bottom package on the stackable package.

Abstract: A multichip package system is provided forming a substrate having a plurality of molding transfer channel, connecting a first integrated circuit die on a top side of the substrate, connecting a second integrated circuit die on a bottom side of the substrate, and concurrently encapsulating the first integrated circuit die and the second integrated circuit die with a molding compound flow through the plurality of the molding transfer channels.

Abstract: A semiconductor system (100) with two substrates has a first substrate (101) with a first and a second surface, electrical contact pads (110, 120) on the first and the second surface, and a central opening (130). The second substrate (102) has a third and a fourth surface, and electrical contact pads (140, 150) on the third and the fourth surface. Metal reflow bodies (160) connect the pads (120, 140) on the second and the third surface. A first semiconductor chip (103), or chip stack, is on the first surface over the opening (130), and a second semiconductor chip (104), or chip stack, is on the third surface inside the opening.

Abstract: A semiconductor package is disclosed. In one embodiment the package includes comprises a semiconductor chip including an active surface with a plurality of chip contact areas and a package substrate including a plurality of first contact areas and a plurality of second contact areas on its bottom surface. The chip is mounted on the package substrate with its active surface facing the package substrate. A plurality of conducting means provide electrical contact between the chip contact areas and the first contact areas. A heat spreading means comprises a planar area and at least one protrusion. The planar area is attached to the upper surface of the chip and the protrusion is attached to the upper surface of the package substrate.

Abstract: An integrated circuit package system is provided forming a carrier having a top side and a bottom side, forming an edge terminal pad on the top side and an inner terminal pad on the bottom side, connecting an integrated circuit die to an inner portion of the edge terminal pad, and encapsulating the integrated circuit die and the inner portion of the edge terminal pad with the outer portion of the edge terminal pad exposed.

Abstract: A power semiconductor device has a first chip carrier part (11) and a second chip carrier part (12), the first chip carrier part (11) and the second chip carrier part (12) being spaced apart from one another and being electrically conductive in each case. A first chip with a power transistor is arranged on the first chip carrier part (11) and a second chip (14) is arranged on the second chip carrier part (12). The terminal for a first potential (DC?) of a supply voltage is electrically connected to the first chip (13) via the first chip carrier part and the terminal for the second potential of a supply voltage (DC+) is electrically connected to the second chip (14) via the second chip carrier part.

Abstract: An electronic part mounting method, a semiconductor module, and a semiconductor device, which can reduce a mounting area and a device thickness. In an electronic part mounting method for bonding an electrode formed on a substrate and an electrode formed on an electronic part to each other, the method comprises the step of bonding both the electrodes through a metal layer made up of aggregated particles of at least one kind of metal. Then, the metal particles have an average particle size of 1 to 50 nm. Preferably, the metal particles form a metal layer having a thickness of 5 to 100 ?m.

Abstract: A power semiconductor module having an increased reliability against thermal fatigue includes a power semiconductor element, a lower-side electrode connected to the lower side of the element, a first insulating substrate connected to the upper side of the lower-side electrode and having metallic foils bonded on both surfaces thereof, an upper-side electrode connected to the upper side of the power semiconductor element, a second insulating substrate connected to the upper side of the upper-side electrode and having metallic foils bonded on both surfaces thereof, a first heat spreader connected to the lower side of the first insulating substrate, and a second heat spreader connected to the upper side of the second insulating substrate. The power semiconductor element and the first and second insulating substrates are sealed with a resin.

Abstract: Microelectronic assemblies interconnected using a separable network interface and electronic systems using the microelectronic assemblies to physically separate high performance signals and lower performance signals to enhance system performance are disclosed.

Abstract: Consistent with an example embodiment, in integrated circuit chip includes an electrostatic discharge (ESD) protection device. A feature of the ESD protection device includes a pair of spaced center and circumferential electrodes, the center electrode being formed by the first electrically conductive layer and the circumferential electrode being formed by the second electrically conductive layer, said electrodes being separated by a steroidal spark gap cavity.

Abstract: A tape carrier package may include an interposer having a first surface and a second surface. The first surface of the interposer may be attached to an exposed active surface of a semiconductor chip. A heat sink may be attached to the second surface of the interposer.

Abstract: A composite contact includes a main body part, a first elastic piece which extends from the main body part and elastically contacts with a terminal disposed at an end part of a fluorescent tube and a second elastic piece which extends from the main body part and aims at elastically contacts with a conductive pattern which is formed on at least one of a front surface and a back surface of a circuit board, and the main body part, the first elastic piece and the second elastic piece are formed as one integrated part by a single member.

Abstract: An embodiment of the present invention is a technique to assemble multi-core dice. A first socket has first N sets of front side bus (FSB) contacts to house a first package having first 2N dice. Each of the first 2N dice has M cores. N and M are positive integers. A first chipset has 2N FSB signal groups interfacing to the first package via the first N sets of FSB contacts using first N FSB signal groups of the 2N FSB signal groups.

Abstract: A laminated IC packaging substrate includes an intermediate connecting layer having a plurality of through holes. Each of the through holes is filled with solder material protruding from a top surface and/or a bottom surface of the intermediate connecting layer. A first circuit board having thereon a first wiring pattern is adhered to the top surface of the intermediate connecting layer using a first adhesive layer. A second circuit board having thereon a second wiring pattern is adhered to the bottom surface of the intermediate connecting layer using a second adhesive layer.

Abstract: It is an object of the present invention to provide a semiconductor device that enables the transmission time of a signal and implementation area to be reduced, and a method for manufacturing the same. A semiconductor device includes a first semiconductor substrate, a capacitor chip, an external input terminal, and an external output terminal. The first semiconductor chip includes a first surface, a second surface, an eleventh through-hole electrode, a twelfth through-hole electrode, and a thirteenth through-hole electrode. The capacitor is laminated on the first semiconductor chip and includes a third surface. A capacitor element is formed on the third surface. The capacitor element functions as a condenser component in the periphery of the first semiconductor chip. The external input terminal is electrically coupled to the capacitor element and the twelfth through-hole electrode through the eleventh through-hole electrode.

Abstract: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing a semiconductor device into a mold and subjecting a curable silicone composition that fills the spaces between said mold and said semiconductor device to compression molding, wherein the curable silicone composition comprises the following components: (A) an organopolysiloxane having at least two alkenyl groups per molecule; (B) an organopolysiloxane having at least two silicon-bonded hydrogen atoms per molecule; (C) a platinum-type catalyst; and (D) a filler, wherein either at least one of components (A) and (B) contains a T-unit siloxane and/or Q-unit siloxane. By the utilization this method, a sealed semiconductor device is free of voids in the sealing material, and a thickness of the cured silicone body can be controlled.

Abstract: A heat sink includes a base adapted for absorbing heat from a heat-generating component, and a plurality of parallel fins having channels defined therebetween. Each of the fins includes a main body standing on the base. A row of protruding portions and openings is alternately arranged on the main body along a direction from a lateral side to an opposite lateral side of the heat sink. The protruding portions disturb and deflect an airflow flowing in the channels from the lateral side to the opposite side of the heat sink. The openings intercommunicate the channels with each other so that the airflow can flow from one of the channels to the other of the channels.

Abstract: The present invention provides a conductive resin composition for connecting electrodes electrically, in which metal particles are dispersed in a flowing medium, wherein the flowing medium includes a first flowing medium that has relatively high wettability with the metal particles and a second flowing medium that has relatively low wettability with the metal particles, and the first flowing medium and the second flowing medium are dispersed in a state of being incompatible with each other. Thereby, a flip chip packaging method that can be applied to flip chip packaging of LSI and has high productivity and high reliability is provided.

Abstract: A heat sink includes a base portion formed of insulating diamond, and a plurality of pressure contacting members formed of the insulating diamond and arranged on the base portion

Abstract: A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours.

Abstract: The invention includes a packaged semiconductor device in which the bond wires are bonded to the leads with an aluminum bump bond. The semiconductor device is mounted on a leadframe having leads with a nickel plating. To form the bump bond between a fine aluminum wire, such as a 2 mil diameter wire, and the lead, an aluminum bump is bonded to the nickel plating and the wire is bonded to the bump. The bump is aluminum doped with nickel and is formed from a large diameter wire, such as a 6 mil diameter wire.

Abstract: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.

Abstract: A micro-element package which can reduce manufacturing costs and can be advantageous for mass production due to simplifying its structure and manufacturing process, and also can facilitate miniaturization and promote thinness, and a method of manufacturing the micro-element package. The micro-element package includes: a substrate having a micro-element on its top surface and a comparatively thin surrounding portion provided around the micro-element; and a circuit board that is electrically connected to the micro-element by utilizing the surrounding portion as a medium.

Abstract: A capacitor structure is described, including a substrate, a first metal layer in the substrate, an etching stop layer on the substrate having therein an opening that exposes a portion of the first metal layer, a connection layer on the portion of the first metal layer, the sidewall of the opening and a portion of the etching stop layer, a second metal layer over the connection layer, and an insulating layer between the second metal layer and the connection layer.

Abstract: An integrated circuit having a multilayer capacitance arrangement and a method for producing an integrated circuit having a multilayer capacitance arrangement are disclosed.

Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.

Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

Abstract: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

Abstract: An assembly comprises a stiffener, a circuit substrate and an integrated circuit (IC) chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers the first region, while the IC chip overlies at least a portion of each of the first and second regions. Moreover, the assembly further comprises a plurality of first solder bumps and a plurality of second solder bumps. The first solder bumps contact both the IC chip and the circuit substrate. The second solder bumps are larger than the first solder bumps, contact the IC chip and are disposed above the second region of the stiffener.

Abstract: A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrode terminals are completely covered with the sealing resin layer.

Abstract: One embodiment of the present invention provides an integrated chip module and a corresponding method of manufacture that facilitates proximity communication. This module includes a base chip and a bridge chip, both of which include an active face, upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip, and the back face of the bridge chip is thinned via planarization or polishing.

Abstract: A memory card structure includes a substrate, B-Stage glue, an adhered layer, a chip, wires, and a compound layer. The substrate has an upper surface, which is formed with first electrodes and golden fingers electrically connected to the first electrodes. The B-Stage glue is coated on the periphery of upper surface of the substrate. The adhered layer is coated on the upper surface of the substrate. The chip is formed with bonding pads, and is adhered on the upper surface of the substrate by the B-Stage glue and the adhered layer. The plurality of wires are electrically connected the bonding pads of the chip to the first electrodes of the substrate. And the compound layer is encapsulated on the chip and the wires.

Abstract: A method produces semiconductor components having a substrate, a semiconductor chip and an encapsulant. Chips situated on a wafer are singulated, arranged on a substrate and electrically conductively connected to a conductor structure on the substrate. The chips on the substrate are encapsulated with an encapsulant and the semiconductor components are singulated by sawing up the encapsulant.

Abstract: The electronic component integrated module includes a wiring board; an electronic component provided on the wiring board; solder for electrically connecting the electronic component onto the wiring substrate; and an encapsulating resin for encapsulating the electronic component and the solder. The average linear thermal expansion coefficient ? of the encapsulating resin, which is calculated by using the glass transition temperature of the encapsulating resin, a linear thermal expansion coefficient ?1 obtained at a temperature lower than the glass transition temperature, a linear thermal expansion coefficient ?2 obtained at a temperature exceeding the glass transition temperature, room temperature, and a peak temperature of reflow packaging of the electronic component integrated module, is not less than 17×106/° C. and not more than 110×10?6/° C.