Abstract: A sensor unit for measuring a response characteristic of a polarization rotation liquid crystal cell, includes a measurement light source which emits measurement light, a first polarization plate which has a first polarization direction and receives the measurement light from the measurement light source to output measurement light having the first polarization direction to a polarization rotation liquid crystal cell, a second polarization plate which has a second polarization direction and receives measurement light passed through the polarization rotation liquid crystal cell, a light receiving unit which receives measurement light passed through the second polarization plate, and a measurement unit which determines a response characteristic of the polarization rotation liquid crystal cell on the basis of a drive signal of the polarization rotation liquid crystal cell and the amount of measurement light received by the light receiving unit.

Abstract: A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit.

Abstract: A level shifter may reduce leakage current and provide firewall protection between circuits of different voltage domains when one voltage domain is in a standby mode. The level shifter may either couple or decouple input circuitry from a reference voltage in response to a firewall enable signal, may translate signal having a predetermined one of either a high or low state when the firewall enable signal is asserted.

Abstract: A high speed voltage translator circuit includes a voltage divider coupled between first and second power supplies, a transconductance amplifier coupled between third and fourth power supplies including a non-inverting voltage input coupled to the voltage divider, an inverting voltage input for receiving an input signal, and a current output, and a current comparator coupled between the third and fourth power supplies having an input coupled to the current output of the transconductance amplifier, and an output for providing a translated output voltage. The translated output voltage transitions between the third and fourth power supply voltage levels, the third power supply voltage level being more positive than a first power supply voltage level, and the fourth power supply voltage level being more negative than a second power supply voltage level.

Abstract: This invention provides an interface circuit for detecting that a DQS signal from a DDR SDRAM is at an intermediate potential. An interface circuit is connected to at least a signal line which transmits the DQS signal from the DDR SDRAM and reaches an intermediate potential VM when the signal attains an inactive state. The interface circuit has a comparing portion for comparing the potential of the DQS with a threshold potential VREFH which is a potential that is different from the intermediate potential VM.

Abstract: An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.

Abstract: A complementary output driver includes a driver input that receives an input signal which alternates between a first state and a second state. A first inverter has a first input and a first output. The first input is coupled to the driver input and the first output generates a complementary output signal that is the complement of a present state of the input signal. A second inverter has a second input and a second output. The second input is coupled to the first output of the first inverter and the second output generates an output signal that is the complement of the present state of the first output. A push-pull network has a push-pull input and a push-pull output. The push-pull input is coupled to the driver input and the push-pull output is coupled to the second output.

Abstract: A current comparator includes an input node for receiving an input current, an output node, a first wide swing current mirror having an input coupled to the input node of the current comparator, a power node for receiving a first power supply voltage such as ground, and an output coupled to the output node of the current comparator, and a second wide swing current mirror having an input coupled to the input node of the current comparator, a power node for receiving a second power supply voltage such as VDD, and an output coupled to the output node of the current comparator. The output node can provide either a voltage or current output signal.

Abstract: Apparatus are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.

Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.

Abstract: A semiconductor integrated circuit device according to the present invention includes: a sample circuit in which through current to be monitored flows during switching between transistors; a non-overlap circuit for outputting an output signal for the switching in the sample circuit; a current detector for detecting the through current flowing during the switching; and a current comparator in which a reference current value with respect to the through current has been set and which compares a current value detected by the current detector with the reference current value and outputs a result of the comparison to the non-overlap circuit.

Abstract: A divider circuit comprises at least two clock edge controlled differential buffer store elements, each being clocked by complementary input clock signals, each comprising internal storage nodes which are pre-chargeable to a pre-charge potential, and each comprising a differential data input. The internal storage nodes of the buffer store elements are either pre-charged at the pre-charge potential or store a logic level, depending on the relevant input clock signals. The differential data inputs of one of the buffer store elements is connected to the internal storage nodes of the other buffer store element and pulsed signals can be tapped off at the internal differential storage node.

Abstract: A power supply system that supplies high-voltage power to a vehicle drive motor is provided to achieve reduction in size, weight and cost of power supply. The power supply system includes a plurality of battery modules connected in series. With the intermediate connection point of the battery modules as an electrical neutral point, power is supplied to a three-level inverter via a three-level-potential high-voltage power supply line having potentials of +150V and ?150V relative to this neutral point. In the three-level inverter, direct-current electric power is converted into three-phase alternating-current electric power to drive an electric motor. Accordingly, the withstand-voltage performance required of control units or control elements connected to the high-voltage power supply line can be halved as compared with the related art, thereby allowing a reduction in the size, weight, and cost of the power supply system.

Abstract: A power-on reset (POR) circuit (200) can include a voltage divider section (202) having a first divider resistor (R21), a second divider resistor (R22), and a diode connected transistor (N22). Signal generator section (204) can include a transistor N21 that is activated according to a potential generated by voltage divider section (202). A trip point of a POR circuit (200) can be based on a difference between the threshold voltages of transistors N21 and N22, and thus less susceptible to variations in threshold voltage.

Abstract: A fast lock mechanism for delay lock loops and phase lock loops. A first circuit is coupled to receive an input clock signal and to generate an output clock signal responsive to the input clock signal. The first circuit includes a charge pump and delay cells. The charge pump generates an operational bias voltage during operation of the first circuit to control a delay of the delay cells. A fast lock circuit is coupled to an output of the charge pump to precharge the output of the charge pump with a startup bias voltage prior to enabling the charge pump.

Abstract: Various embodiments for a partial cascode delay locked loop architecture are described. In one embodiment, an apparatus may include a delay locked loop circuit having a plurality of partial cascode circuits. The plurality of partial cascode circuits may be arranged to reduce phase noise from a ground power supply voltage and a power supply voltage. Other embodiments are described and claimed.

Abstract: A delay locked loop includes a variable delay unit, a phase inversion unit, a delay selecting unit, a delay control unit and an inversion control unit. The variable delay unit delays a reference clock signal based on phase difference between a first feedback clock signal and a reference clock signal, outputted from the delay control unit. The phase inversion unit selectively inverts the delayed clock signal in response to a phase inversion control signal and generates a reproduction clock signal. The delay selecting unit selectively delays the first feedback clock signal corresponding to the reproduction clock signal in response to an inversion control termination signal to generate a second feedback clock signal. The inversion control unit generates the phase inversion control signal when the phase difference between the delayed feedback clock signal and the reference clock signal is larger than a half clock-cycle, and generates the inversion control termination signal.

Abstract: Methods and arrangements to adjust a duty cycle of a clock signal are disclosed. Embodiments may include a duty cycle controller to adjust the duty cycle of the clock signal based upon a delay signal and an input clock signal. A duty cycle detector may determine signals with frequencies based upon the duty cycle of the output signal and a correction module may compare the frequencies of the detector signals to generate the delay signal. In some embodiments, once the duty cycle of the output clock signal reaches the desired duty cycle such as fifty percent, the correction module may be turned off.

Abstract: A PWM buffer circuit includes a duty cycle converting circuit and a frequency-fixed PWM signal generating circuit. The duty cycle converting circuit is used for receiving a first PWM signal and then generating a duty cycle reference voltage on the basis of the first PWM signal. The duty cycle reference voltage is a one-to-one mapping function of the first duty cycle. The frequency-fixed PWM signal generating circuit is used for receiving the duty cycle reference voltage and then outputting a second PWM signal with a fixed frequency. The second PWM signal has a second duty cycle, which is determined in accordance with the duty cycle reference voltage. In addition, the second duty cycle is a one-to-one mapping function of the duty cycle reference voltage.

Abstract: An AC power source controller includes an input side, which is electrically connected to an output side via a power source controlling interface; and a phase modulator, which is electrically connected to the power source controlling interface. The phase modulator includes a microcontroller unit, an encoding DIP switch, a control signal receiving module, and a signal detecting interface, which may accurately detect the phase variation of an input power source so that, according to chosen conducting phase Pn, the microcontroller unit may automatically adjust the time delay Dn between conducting and cutting off orders sent to the power source control interface to control the power source output accurately, whereby the inaccuracy and instability of AC power source output control and phase difference between current and voltage generated by reactance load may be improved.

Abstract: A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level inverted from that of the digital data signal within a period within which the clock has a second level; a second control stage configured to output a signal of a first level within the period within which the clock has the second level and a signal of a level within another period within which the clock has the first level; a third control stage configured to output an output signal of the first level within a period within which the signal outputted from the second control stage has the second level; and a phase adjustment circuit configured to adjust the phase to produce a second clock and supply the second clock to the third control stage.

Abstract: A semiconductor device and an electronic apparatus incorporating the semiconductor device are disclosed. The semiconductor device includes a power circuit that further includes a power transistor for providing current to a load (load current), a temperature detector for detecting the temperature of the power transistor, and a current detector for detecting the load current. If the detected temperature of the power transistor reaches a first predetermined temperature, and if the detected load current exceeds a first predetermined load current, a signal is output through an external terminal of the semiconductor device.

Abstract: A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.

Abstract: In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.

Abstract: An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.

Abstract: There is provided a semiconductor device including a first logic circuit to operate based on a first power supply and a second power supply, and a second logic circuit to operate based on the first power supply and a third power supply boosted from the second power supply. The second logic circuit includes a holding section to hold a value generated according to a first signal and a second signal operating asynchronously with respect to each other.

Abstract: Systems and methods for creating and using a conditioning signal are provided. In some embodiments, systems for creating a conditioning signal providing information regarding an input signal are provided, wherein the systems comprise: a signal conditioning developer that receives the input signal and produces the conditioning signal; a delay device that receives the input signal and produces a delayed input signal, wherein the delayed input signal is delayed to simultaneously transmit with the conditioning signal and form a vector signal with the delayed input signal and the conditioning signal; and a receiving circuit coupled to the signal conditioning developer and the delay device that receives the vector signal and dynamically adjusts according to the conditioning signal.

Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

Abstract: In one embodiment, an apparatus is constituted with a temperature sensing circuit adapted to be coupled to a current sources circuit, and configured to measure a circuit temperature and to generate a temperature-indicating signal in response to the circuit temperature and an adjustable current output by the current sources circuit; a reference voltage circuit to be coupled the current sources circuit and configured to provide a reference signal in response to a reference current output by the current sources circuit; and a trip generator circuit coupled to the temperature sensing circuit and the reference voltage circuit and configured to generate a trip point signal if a difference between the reference and the temperature-indicating signals indicates that a threshold circuit temperature has been reached or exceeded.

Abstract: A semiconductor circuit suitable for normally-on switching elements or switching elements low in threshold voltage. A negative power supply is charged by a high-voltage power supply. A high-voltage switch controls the advisability of applying a voltage to a high-voltage terminal. With deducing the power supply to power switching elements, the high-voltage switch is turned off, and even in the case where the voltage of the controlling circuits of the power switching elements is reduced, the power supply capacitors for the controlling circuits are charged by the high-voltage terminal thereby to operate the controlling circuits. Further, a negative power source voltage generating circuit utilizes the energy charged to the capacitors from output terminals. A voltage terminal is inserted between the high-voltage terminal and a reference voltage terminal. The negative power source voltage generating circuit is interposed between the voltage terminal and a plurality of the output terminals.

Abstract: A circuit is described that generates multiple voltages each having a common reference point. The circuit uses a feedback control loop to generate a center voltage, a first voltage generator, and a second voltage generator. The first voltage generator generates a first high voltage related to the center voltage plus a first offset voltage and a first low voltage related to the center voltage minus the first offset voltage, where the first offset voltage is determined by a first control input to the first voltage generator. The second voltage generator generates a second high voltage related to the center voltage plus a second offset voltage and a second low voltage related to the center voltage minus the second offset voltage, where the second offset voltage is determined by a second control input to the second voltage reference generator. An example is also presented where the multiple voltage generator circuit is advantageously employed in a deserializer data acquisition system.

Abstract: A voltage generation system for generating operating voltages for memory devices, especially non-volatile memories, from a single external high voltage source. In one embodiment, the system comprises an input terminal for receiving an external voltage, a charge pump for producing a first high voltage based on the external voltage to be higher than the external voltage, a first regulating circuit for regulating the first high voltage to a lower predetermined voltage, a second regulating circuit for generating a second high voltage based on the external voltage to be lower than the external voltage.

Abstract: A circuit of generation of a reference voltage by a first MOS transistor connected to a first terminal of application of a supply voltage, the first transistor being in series with a second MOS transistor controlled by an input stage of a transconductance amplifier and their junction point defining an output terminal providing the reference voltage, a first current source connecting the first supply terminal to a gate of the first transistor, a second current source connecting the second transistor to a second terminal of application of the supply voltage, at least one third MOS transistor connecting the two current sources, and a capacitive element directly connecting the output terminal to a conduction terminal of the third transistor to vary the conduction of this third transistor in case of a variation in output voltage.

Abstract: An object of the invention is to improve a defect caused at the time of starting a midpoint potential generating circuit for use in a semiconductor device. A bias generating circuit supplies a grounding potential as a bias voltage Vbias and sets a midpoint potential of capacitors C1 and C2 to a grounding potential when a supply voltage VDD is lower than a first reference voltage. When the supply voltage VDD is equal to or higher than the first reference voltage, the bias generating circuit supplies the supply voltage VDD as the bias voltage Vbias. When the bias voltage Vbias is equal to or higher than a second reference voltage, the bias generating circuit supplies a voltage obtained by dividing the supply voltage VPP of the booster power supply circuit as the bias voltage Vbias to a node of the capacitors C1 and C2.

Abstract: A filter circuit includes a voltage amplifier, a resistor, a capacitor, and an analog switch connected between the voltage amplifier and the capacitor. When the voltage amplifier is turned on, the analog switch is opened so that the capacitor is disconnected from the voltage amplifier. Thus, an output voltage of the voltage amplifier sharply increases to its steady state value, as soon as the voltage amplifier is turned on. When the output voltage of the voltage amplifier is fully stabilized, the analog switch is closed so that the capacitor is connected to the voltage amplifier. During the period of time when the analog switch is closed, the filter circuit is configured as an imperfect integrator circuit with filter characteristics that depend on a capacitance of the capacitor and a resistance of the resistor.

Abstract: An operational amplifier is dynamically accelerated depending on its internal state. Acceleration is disabled when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates no risk of instability, the acceleration is turned on to speed up the circuit operation.

Abstract: In a DC offset cancellation circuit, an operational amplifier is provided with an inverse terminal, a non-inverse terminal and an output terminal. A first resistor is connected to the non-inverse terminal. A second resistor connected between the inverse terminal and the output terminal. A DC offset cancellation resistor is connected between the inverse terminal and the non-inverse terminal. Also, in each of first and second DC offset cancellation circuits of the programmable gain amplifier, an operational amplifier is provided with an inverse terminal, a non-inverse terminal and an output terminal. A first resistor is connected to the non-inverse terminal. A second resistor is connected between the inverse terminal and the output terminal. A DC offset cancellation circuit is connected between the inverse terminal and the non-inverse terminal. Here, the first and second DC offset cancellation circuits are connected with each other in series.

Abstract: An active circuit includes (a) a first chopper circuit that receives an input signal and a chopping signal of a frequency higher than a base band of the input signal, and that provides a modulated input signal; (b) an amplifier that receives the modulated input signal and that provides an amplified signal resulting from amplifying the modulated input signal; and (c) a second chopper circuit that receives the amplified signal and the chopping signal to provide an output signal. The chopping signal has a frequency that may be dynamically adjusted to accommodate changes in impedance and signal spectrum as a result of the operations of the chopper circuits. The active circuit further includes a low pass filter that receives the output signal and that attenuates components of the output signal above the base band of the input signal. In this manner 1/f noise introduced by the amplifier is eliminated or reduced.

Abstract: Systems and methods for preventing violations of minimum pulse width requirements that may cause damage to PWM amplifiers. One embodiment comprises a digital PWM amplifier that includes shutdown circuitry which is configured to identify blockout intervals during which deassertion of the PWM signals would cause the generation of below-minimum-width pulses in the signals. Each blockout interval may, for example, begin 1 minimum pulse width before and end 1 minimum pulse width after a rising/falling edge the PWM signals. If a shutdown signal is asserted (or deasserted) during one of the blockout intervals, the PWM signals are deasserted (or reasserted) at the end of the blockout interval.

Abstract: A method of reducing the settling time of an amplifier includes providing a pre-set voltage on a high gain node of the amplifier when the amplifier is disabled. This pre-set voltage can be slightly less than the regulated voltage. In this manner, when the amplifier is enabled, the high gain node can quickly reach this regulated voltage. The pre-set voltage can be applied to the high gain node by operating a switch, e.g. if the amplifier is enabled (disabled), then the switch is open (closed). A startup circuit can generate the pre-set voltage. This startup circuit can include a startup current source and a transistor connected in series between VDD and VSS. The switch can be connected to the gate and drain of the transistor. Notably, the transistor can be the same type of device as the MOS device driven by the high gain node in the amplifier.

Abstract: The present invention provides a method for selecting samples for digital amplifier predistortion estimation. The method may include accessing a plurality of samples. Each sample includes information associated with an input signal and a corresponding output signal of the amplifier. The plurality of samples includes at least one first sample acquired at a first time and at least one second sample acquired at a second time displaced from the first time by at least one selected time interval. The method may also include selecting a subset of the plurality of samples based on a sample distribution and determining a transfer function associated with the amplifier based on the subset of the plurality of samples. The method further includes determining a predistortion function based on the transfer function and applying the predistortion function to the input signal of the amplifier.

Abstract: The present invention is related to low power low noise amplifiers (LNA) including on/off switching capability, which are preferably used for impulse radio (IR) ultra-wideband (UWB) receivers. In the invention a very low power and high-gain Common-Gate Capacitive Cross Coupling Cascaded LNA is proposed, to provide an optimum gain for large ON times. The invention provides also a Common-Source Cascoded LNA for shorter received pulse widths, with the aim of implementing a fast ON/OFF switching. An input signal is applied to a first amplifying stage and the switching means are coupled to a second amplifying stage so that they do not interfere with the matching network of the first stage. The invention is also related to a method of amplifying a radio frequency signal using a plurality of low noise amplifying elements.

Abstract: An amplifier, tuner, and method of amplification are provided. The amplifier has a pair of transistors. Each transistor has a control terminal and an output terminal disposed between the transistor and a power supply input. A first network is connected between each power supply input and output terminal. The first network contains a first resistor and a first switch connected in parallel with the first resistor. A second network is connected between the transistors. The second network contains a first and second combination. Each of the first and second combinations contains a second resistor and a second switch connected in parallel with the second resistor. The first and second combinations are connected by a third switch.

Abstract: A differential amplifier stage includes one active load circuit connected to a pair of cross-coupled transistors that produce a differential signal. The active load circuit controls the rise time of the differential signal. The differential amplifier stage also includes another active load circuit connected to the pair of cross-coupled transistors. The second active load circuit controls the fall time of the differential signal.

Abstract: A DC current regulator circuit comprises a first circuit node (32) which is operable to receive an external input voltage. A transistor (M1) has an input, a first leg and a second leg. The first leg of the transistor is isolated from the first circuit node (32). An amplifier (10) has an output connected to the input of the transistor (M1), a first amplifier input for receiving a reference voltage (VREF) and a second amplifier input connected to the first circuit node (32). A low-pass filter (33) connects between the output of the amplifier and the first circuit node (32). A current mirror (36) connects in series with the second leg of the transistor (M1) and has a first branch (38) for providing a regulated output current and a second branch (37) which connects to the first circuit node (32). The current regulator has reduced sensitivity to conducted EMI received at the first circuit node (32).

Abstract: An integrated circuit including a distributed amplifier is disclosed. The integrated circuit includes a plurality of amplification stages, each stage connected to an input signal and an output signal. At least one amplification stage includes an amplification transistor such as a field effect transistor (FET) having a gate, a source, and a drain, the gate connected to the input signal and a feedback path between the drain and the gate. The feedback path is implemented with another FET having a gate, a source, and a drain; its gate is connected to a control signal; its drain is connected to the drain of the amplification FET; and its source is connected to the gate of the amplification FET. The feedback path provides variable resistive feedback and allows the amplification FET to operate at its linear response portion of its characteristic curve even when its gain is controlled by a control signal.

Abstract: A circuit and method of reducing noise in the circuit comprises a first transistor and an amplifier operatively connected to the first transistor, wherein the amplifier comprises a plurality of transistors and is adapted to amplify an input signal, and wherein the input signal is differentially captured at an output of the first transistor and the amplifier. Preferably, the plurality of transistors comprises a second transistor and a third transistor. Furthermore, a noise level of the first transistor and the third transistor are preferably cancelled. The size of the second transistor may be approximately 1/50?. Preferably, a gain on an amplifier stage formed by the second transistor and the third transistor is adapted to be increased. Moreover, an equivalent transconductance of the amplifier is preferably independent of an impedance matching on the amplifier. Preferably, a noise figure level of the circuit is less than approximately 1 dB.

Abstract: An adjusting frequency device of built-in oscillator for USB interface and a method thereof are described. It is Auto detect the error of bit-rate between the USB host and the USB device, and produce tiny counting time for clocking the clock error between the USB host and the USB device by a delay lock loop. The clock error after quantification, digitization and operation outputting a quantitative code, then the oscillator adjusts the oscillation frequency according to the quantitative code. Whereby adjusting the oscillation frequency of the USB device and the frequency of the USB host to less than 1% clock error for ensuring the accuracy of data transmission.

Abstract: A spread spectrum frequency modulated oscillator circuit usable as a clock comprises a reference component such as a resistor, a voltage controlled oscillator and a first circuit coupled to the reference component and voltage controlled oscillator and configured to supply a first control signal to the oscillator to cause the oscillator to oscillate at a frequency corresponding to a value of the reference component. A second circuit configured to supply a random signal to the oscillator causes the frequency of the oscillator to dither.

Abstract: Various systems and methods for clock management. As one example, a system for clock management is disclosed that includes a controllable oscillator, an oscillation control source, and a sample and hold circuit. The sample and hold circuit is disposed between the oscillation control source and the controllable oscillator, and is operable to introduce a transfer function having a sin x/x characteristic with a null at a switch frequency applied to the sample and hold circuit.