Abstract: To provide an inverter unit with excellent manufacturing performance and with current carrying capacity increased and size reduced by further increasing the cooling efficiency of a power efficiency device. The inverter unit includes: a semiconductor chip constituting an arm of an inverter; a first conductor 33 joined to a positive side of the semiconductor chip; and a second conductor 35 joined to a negative side of the semiconductor chip. The first and second conductors are disposed above a cooler 22 cooling the semiconductor chip so that a joint surface of the first conductor 33 which is joined to a positive electrode of the semiconductor chip and a joint surface of the second conductor 35 which is joined to a negative electrode of the semiconductor chip are not in parallel to a surface of the cooler 22.

Abstract: A combined modulator and inverter for use in transmitting audio files to a receiver. The combined modulator and inverter enables the usage of various devices in a vehicle that utilize different types of power sources. Audio devices may be used with the modulator and inverter to play the devices over a radio. The device may also have the ability to play audio files received from devices enabled to store digital files.

Abstract: It is an object of the present invention to provide a PWM cycloconverter that can compensate an error between a voltage command and a real voltage generated by a commuting operation. The PWM cycloconverter for solving the above-described problem includes: an input voltage phase detector (6) for detecting the phase of the voltage of a three-phase ac power source (1); a current direction detector (7) for detecting the direction of a current supplied to a two-way semiconductor switch (3); and a commutation compensator (11) for receiving the outputs of the input voltage phase detector and the current detector as inputs to compensate for a voltage command.

Abstract: A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example embodiment, this is achieved by combining a plurality of CAM devices in a serial cascade arrangement. Each CAM device of the serial cascade arrangement receives a portion of the search word. Each of the CAM devices in the serial cascade arrangement includes a CAM, a plurality of GMAT lines, a dummy match line, and a GMAT interface circuitry. The GMAT interface circuitry facilitates driving the match signals from a substantially previous CAM to a substantially adjacent CAM. The last CAM device is coupled to a match latch and a priority encoder.

Abstract: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines on a 3F-pitch arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.

Abstract: In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current. Consequently, the time required for charging or discharging the dummy bit line differs from the desired time, and therefore, it has been unable to set optimum operation timing. To solve these problems, a semiconductor memory device of the present invention includes a dummy memory cell array in which source lines of dummy memory cells are charged simultaneously by a charge circuit configured similarly to a dummy bit line charge circuit, thus suppressing off leak current and performing appropriate timing generation.

Abstract: An apparatus, a method, and a system for a fuse array are disclosed herein. In some embodiments, fuse array may comprise a plurality of fuse cells and a single sense amplifier coupled to plurality of fuse cells to asynchronously sense one or more voltages output by the plurality of fuse cells, one fuse cell at a time.

Abstract: An apparatus, a method, and a system for a fuse cell are disclosed herein. In various embodiments, a fuse cell may comprise a standby circuitry to reduce a voltage drop across a fuse device.

Abstract: A semiconductor memory that includes a memory cell array by which power consumption can be reduced and that enables a reduction in circuit area. In the memory cell array, each of capacitor plate lines is arranged so as to connect with ferroelectric memory cells in a same row, and each of word lines is arranged so as to connect with ferroelectric memory cells in different rows in a column direction. In addition, of drive circuits for driving the capacitor plate lines and the word lines, part of word line drive circuits (WL drive circuits) are arranged in the column direction. Therefore, it is possible to drive all of the word lines without using a dummy area. As a result, circuit area can be reduced.

Abstract: There is provided a memory device including a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the memory cell, a charge transfer circuit for transferring the electric charges in the bit line to an output node, a dummy memory cell connected to the bit line, and a control circuit for controlling the charge transfer ability of the charge transfer circuit in accordance with the change in the voltage of the bit line.

Abstract: An apparatus, a method, and a system for fuse cells are disclosed herein. In various embodiments, a fuse cell may include circuitry to adjust a sensing margin.

Abstract: A memory cell having a programmable solid state electrolyte layer, a writing line and a controllable switch that is arranged between the solid state electrolyte layer and the writing line. The controllable switch has a control input that is connected with a selecting line and the switch also has a limiting element that limits a current through the solid state electrolyte layer to a predetermined amount of electric charge for a write operation.

Abstract: A method of performing a program-suspend-read operation in a PRAM device comprises programming a write block comprising N unit program blocks in response to a program operation request, and suspending the program operation after programming M unit program blocks, where M is less than N, in response to a read operation request. The method further comprises executing the requested read operation, and then resuming the programming of the write data block and programming (N?M) remaining unit program blocks.

Abstract: A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.

Abstract: A method for measuring hysteresis curves and anisotropic energy of magnetic memory units is disclosed. It comprises gradually applying different magnetic fields to a single-layer or a multilayer magnetic structure (such as a MRAM memory unit) by extra ordinary Hall effect, and recording the variation of the Hall voltage to obtain the hysteresis curve and anisotropic energy with specific instruments, and calculating the individual anisotropic energy value of the magnetic material of the single-layer or the multilayer magnetic structure.

Abstract: A magnetic recording element is disclosed for which current density required for writing is low and structure of the element is simple. It comprises a ferromagnetic fine wire formed on a Si substrate, current electrodes that contact ends of the ferromagnetic fine wire, and voltage electrodes joined to the ferromagnetic fine wire and current electrodes to measure voltage across part of the ferromagnetic fine wire in cooperation with the current electrodes. A magnetic domain wall is induced in the ferromagnetic fine wire when the element is manufactured. A depression is formed in the surface on top of the ferromagnetic fine wire between the voltage electrodes, and between one of the current electrodes and one of the voltage electrodes. Voltage is measured between the two voltage electrodes when reading current is applied, to determine whether the magnetic domain wall is present between the two voltage electrodes, whereby recorded data can be identified.

Abstract: A method prevents errors in execution of simultaneous read and verify operations on data being modified in two different partitions of a nonvolatile memory device. The errors are due to disturbances caused by turning on or by turning off a bank of sense amplifiers of a partition while a critical discrimination phase is being carried out by the bank of sense amplifiers of the other partition. The method includes establishing an increase in duration of one of the two operations for exceeding a minimum duration of a critical discrimination phase for the banks of sense amplifiers, and conditionally delaying conditioning of generation of a turn on or turn off signal of the bank of sense amplifiers for the partition in which the operation of an increase in duration is in progress by a predetermined time. The predetermined time is based on a command of termination, or a beginning of the critical discrimination phase by the bank of sense amplifiers of the other partition wherein the other operation is in progress.

Abstract: Storage of information represented by a multi-bit word in a single non-volatile memory cell is made possible by programming the threshold voltage of the non-volatile memory to a specific threshold level corresponding to the multi-bit word. Stored or generated multi-bit words are scanned and converted into a gate voltage to be applied to the non-volatile memory cell until the electrical response from the non-volatile memory cell indicates that the voltage generated from the specific multi-bit word which has been applied to the gate matches the information stored in the non-volatile memory cell. The matched multi-bit word is read out of storage and represents the stored bits in the single non-volatile memory cell.

Abstract: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

Abstract: A semiconductor memory device includes a memory-cell array, a read bit line, a write bit line, a sense amplifier, a first sense line, a second sense line, a first bit line switch, and a second bit line switch. The memory-cell array is laid out to form an array. The read bit line is shared by plural memory cells and connected to a data output node. The write bit line is shared by plural memory cells and connected to a data input node. The sense amplifier is configured to sense a difference in electric potential. The first sense line is connected to one of the input terminals. The second sense line is connected to the other input terminal. The first bit line switch is configured to control electrical connection and disconnection. The second bit line switch is configured to control electrical connection and disconnection.

Abstract: A semiconductor memory device of the present invention provides, in a memory having an hierarchical bit line structure, a test mode which causes all switches for selecting hierarchical bit lines and a main bit line in an activated memory array to be connected all the time. With this configuration, it is possible to perform a disturb refresh test on a memory cell arrays basis regardless of the hierarchical bit line structure. Possibility of an erroneous read-out, which may be caused by connecting each of the hierarchical bit lines to one another and a consequent increase in a bit line load capacity, may be prevented by providing a timing control such that the switches are connected after a normal mode operation.

Abstract: A static random access memory (SRAM) cell array is provided that reduces leakage current. The SRAM cell array is configured in a plurality of columns. Each of the columns comprises: a column virtual ground node; a column switch for selectively coupling the column virtual ground node to one of a ground or a nominal low voltage; and a plurality of segments. Each of the segments comprises: a segment virtual ground node; a plurality of SRAM cells including a virtual ground signal coupled to the segment virtual ground node; and a virtual ground switch for selectively coupling the segment virtual ground node to one of either a nominal low voltage or the column virtual ground node. A method for operating the SRAM cell array is also described.

Abstract: An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

Abstract: A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed by a voltage applied to the common line are caused to electrically float while the source and drain regions of memory cells not being programmed have voltages applied thereto. This programming technique is applied to large arrays of memory cells having either a NOR or a NAND architecture.

Abstract: The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.

Abstract: SRAM cell includes a four-terminal diode as a read device wherein the first terminal is connected to a read word line, the second terminal is connected to a storage device through a resistor, the third terminal is floating, and the fourth terminal is connected to one of two bit lines; and two MOS transistors as a write device; and each MOS transistor is connected to the bit line respectively; and a latch including two cross-coupled inverters as the storage device; and the SRAM cell can be formed from thin-film layer, thus multiple memory cells are stacked; and the heavy routing lines are driven by the bipolar drivers which are part of the invention, hence the bipolar circuits and the control MOS transistors of the peripheral circuit can be formed from the deposited thin-film layers; consequently the whole chip can be stacked over the wafer, such as silicon, quartz and others; additionally it applications are extended to a multi port memory and a content addressable memory.

Abstract: A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: This disclosure concerns a semiconductor memory device comprising memory cells; word lines connected to gates of the memory cells; bit lines connected to drains or sources of the memory cells and transmitting data of the memory cells; sense nodes connected to the bit lines and transmitting data of the memory cells; transfer gates connected to between the bit lines and the sense nodes; and latch circuits latching data to the sense nodes, wherein in a data read operation, a selection word line is in an inactive state during a latch period which is from immediately before the latch circuits start a data latch operation until when the transfer gate disconnects the bit lines from the sense nodes after the latch operation, the selection word line being one of the word lines and being connected to selection memory cells from which data is to be read to the sense nodes.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to selectively couple any of the multiple voltages to the selector output. The selector output of the selector circuit is coupled to a non-volatile memory array to provide the NV memory array with a selectable program voltage for programming the NV memory array and a selectable erase voltage for erasing the NV memory array.

Abstract: A single job memory device includes an array of memory cells, row and column decoders and first and second charge pump voltage regulators controlled by respective first and second control circuits that supply the row and column decoders at least during write operations of data in the array of memory cells. A third charge pump voltage generator, controlled by a third control circuit, supplies the row and column decoders during read operations of data from the array of memory cells. The memory device includes a switching circuit that, during the read operations, disconnects two of the control circuits from the respective charge pump voltage generators, transmits control signals generated by the other control circuit to the first and second charge pump voltage generators, and shorts among them the output nodes of the voltage generators on which the supply voltages of the row and column decoders are generated.

Abstract: A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.

Abstract: A nonvolatile memory system includes a drive voltage generator to generate a drive voltage on the basis of a power supply voltage; a plurality of normal memory cells serving as a nonvolatile memory storing data by accumulating charge of a polarity according to the data to be stored in a floating gate at a level according to the drive voltage generated by the drive voltage generator, the data being written in or read from the nonvolatile memory; a minimum voltage detecting memory cell serving as a nonvolatile memory in which charge of a level to cause a read error when the power supply voltage is equal to or lower than a minimum voltage of predetermined operation guarantee is accumulated in a floating gate; and a controller to output a read result of the normal memory cells if no read error occurs in a reading operation in the minimum voltage detecting memory cell.

Abstract: In a D/I conversion section of the semiconductor device for driving a light emission display device, a precharge circuit is provided at the rear of each 1-output D/I conversion section. A precharge signal PC is input into the precharge circuit. The D/I conversion section has two output blocks internally thereof, and a role for storing and outputting current is changed every frame to enable securing a period for driving a pixel longer. Further, at the time of driving, in the precharge circuit, current driving is carried out after a voltage corresponding to output current has been applied to the pixel, and therefore, the pixel can be driven at high speed. Thereby, output current of high accuracy can be supplied to digital image data to be input, and even where an output current value is low, the current load device can be driven at high speed.

Abstract: A data storing fuse element unit includes a plurality of fuse elements, stores data in the respective fuse elements in a bit unit in accordance with presence and absence of cutting of fuse elements, and a latch circuit unit latches the stored data by the bit unit. A logic information storing fuse element unit stores logic information of whether output logic of the data stored in the fuse elements is to be inverted or not. A data selecting unit selects any one of data latched in the latch circuit unit and data with the output logic of the data latched in the latch circuit unit inverted in a logic inverting unit, in accordance with logic information of the logic information storing fuse element unit and outputs the data.

Abstract: The energy consumption of a static memory cell, which may be connected to a first bit line and a second bit line of a bit line pair by means of transistors, is reduced in an energy-saving mode of operation by adjusting the potentials on each of the bit lines of the bit line pair such that a potential difference between the gate terminals of the transistors and the bit lines of the bit line pair is reduced in comparison with a normal mode of operation.

Abstract: A memory system includes a semiconductor memory having a plurality of banks; and a controller accessing the semiconductor memory. The number of the banks is larger than the number of banks simultaneously accessed. When receiving an access command for the bank currently executing the access operation, the semiconductor memory activates a busy signal and keeps the busy signal active until the access operation currently executed is completed. The controller stops outputting a next access command while receiving the activated busy signal. Based on the received busy signal, the controller judges whether or not the next access command should be outputted to the semiconductor memory. Consequently, it is possible to easily execute the random access in a semiconductor memory having a plurality of banks, without giving any load to the system side, which can improve the data transfer rate at the time of the random access.

Abstract: A memory capable of inhibiting a non-selected cell from disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, for applying voltages of opposite directions to the first storage means of a non-selected memory cell by the same number of times or substantially applying no voltages throughout a read operation and a rewrite operation while varying a rewriting method with a case of reading first data by the read operation and with a case of reading second data by the read operation.

Abstract: A system and method are disclosed for reducing latency in asserting a word-line for read/write operations of a memory row in a memory array. One embodiment of the present invention includes a memory array decoder circuit. The memory array decoder comprises a level-shifting NAND-gate operative to receive a plurality of pre-decode inputs having a first voltage range. The level-shifting NAND-gate is further operative to generate a level-shifted NAND output signal that is a NAND output of the plurality of pre-decode inputs and has a second voltage range that is greater than the first voltage range. The memory array decoder circuit also comprises an output inverter operative to invert the level-shifted NAND output signal to generate a decode signal.

Abstract: An insulator for a drum of a concrete truck is provided. Because temperature is a factor in the time in which concrete cures, thermal conditions during transport are of paramount concern. There have been efforts to alleviate this problem by providing insulating blankets that control temperature better. However, until now, a durable system that effectively insulates concrete while in transport has not been available. Furthermore, construction of an insulating system large enough to cover a concrete mixer gives rise to numerous fabrication difficulties. With the introduction of a polyethylene foam interposed between truck tarp material, a convenient system that is easily coupled and decoupled from a truck is available that is both durable and cost effective.

Abstract: The present invention relates to a device for producing a hardenable mass, preferably bone substitute and/or bone reinforcing material or bone cement or similar material. A mixing container (3) has a mixing space (4) in which at least one powder and at least one liquid component (5, 6) are mixed to provide the hardenable mass (2). A piston means (7) is provided in the mixing space (4) of the mixing container (3). At least one means (8) which is rotatable relative to the mixing container (3) cooperates with the piston means (7) for, in a retaining position (P1), retaining said piston means (7) relative to the mixing container (3) and, by rotation to a release position (P2), releasing the piston means (7) such that said piston means can move in a direction (U) towards at least one opening (49) through which said mass (2) can pass out of the mixing space (4).

Abstract: A paint mixing system made up of a generally firm elongated stirrer with a first end that extends along a generally symmetrical straight body length to a second end, and a sleeve. The stirrer is generally configured for insertion within the sleeve, and when put together the sleeve and the stirrer are configured to interact so as to allow for the mixing of paint by moving the device within the can of paint. After the mixing of paint to a desired consistency, the stirrer sleeve can be removed and replaced.

Abstract: A measuring apparatus includes several feeding mechanisms, a conveying mechanism, and receiving barrels as many as the feeding mechanisms; each feeding mechanism includes a storage barrel, a conduit connected to an outlet of the storage barrel, an elastic element in the conduit, and a transmission for rotating the elastic element so as to convey material forwards along the conduit; the conveying mechanism includes a guiding and bearing board for supporting the receiving barrels, a platform, a conveying machine for pushing the receiving barrels forwards, a propping power source for propping the platform upwards, and scales; the board has slots, and the scales are positioned on the platform for weighing materials added into the receiving barrels; each scale has propping rods thereon such that the scales will weigh materials added into the receiving barrels when moved up for the propping rods to pass through the slots and prop the receiving barrels.

Abstract: The present invention is directed to a multi-compartment autoclave using inter-compartment dividers having one or more underflow openings for passing a feed stream between compartments.

Abstract: A mixing apparatus has a chamber, a shaft extending into the chamber, a motor drivingly interconnected to the shaft, a nozzle support affixed to the shaft and extending outwardly therefrom within the chamber, and a nozzle having an interior passageway affixed to the nozzle support such that the nozzle moves in the chamber as the motor drivingly rotates the shaft. The chamber has a multi-phase fluid therein. The nozzle moves through the fluid such that fluid is channeled through the interior passageway at a same rate that the nozzle moves through the fluid. Another nozzle can be affixed to the nozzle support diametrically opposite to the nozzle.

Abstract: A mixing apparatus has a chamber, a shaft extending into the chamber, a motor drivingly interconnected to the shaft, a nozzle support affixed to the shaft and extending outwardly therefrom within the chamber, and a nozzle having an interior passageway affixed to the nozzle support such that the nozzle moves in the chamber as the motor drivingly rotates the shaft. The chamber has a multi-phase fluid therein. A flow restrictor is affixed to an inner wall of said chamber so as to extend inwardly therefor. The flow restrictor is a plurality of flat panels arranged in spaced relation around the interior of the chamber and within a liquid phase of the multi-phase fluid.

Abstract: Described are a system and a method for airport noise monitoring. The system may include (a) a data receiving arrangement receiving, from a data source, information corresponding to an airport; (b) a data comparing arrangement comparing the received information to noise rules; and (c) an alert generating arrangement generating a noise alert based on the comparison of the received information to the noise rules.

Abstract: Even when compression stress is generated because a volume of a thermal insulation layer 2 is expanded due to oxidized by oxygen in the air, occurrence of cracks and fractures of the thermal insulation layer and a heating conductor 3 caused by the cracks are prevented by dispersing the compression stress. A pressure wave generator comprises a substrate 1, the thermal insulation layer 2 of porous material which is formed on a surface of the substrate 1 in thickness direction, and the heating conductor 3 of thin film formed on the thermal insulation layer 2, and generates pressure waves by heat exchange between the heating conductor 3 and a medium.

Abstract: An alarm clock assembly of an embodiment of the present invention is provided that also turns off a non-integrated, connected lamp or other electrical device based on pushing a button on the clock. The alarm clock assembly also has input means for setting a timer to turn off the connected device and can also be programmed to turn on the connected, non-integrated device at a specified time or after a specific time period has elapsed. The alarm clock assembly can also regulate the electrical current in such a manner to dim or flash a connected device, such as a lamp.