Abstract: In accordance with one embodiment of the present invention, a power semiconductor device includes a first drift region of a first conductivity type extending over a semiconductor substrate. The first drift region has a lower impurity concentration than the semiconductor substrate. A second drift region of the first conductivity type extends over the first drift region, and has a higher impurity concentration than the first drift region. A plurality of stripe-shaped body regions of a second conductivity type are formed in an upper portion of the second drift region. A third region of the first conductivity type is formed in an upper portion of each body region so as to form a channel region in each body region between the third region and the second drift region. A gate electrode laterally extends over but is insulated from: (i) the channel region in each body region, (ii) a surface area of the second drift region between adjacent stripes of body regions, and (iii) a surface portion of each source region.

Abstract: A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the first trench, wherein the stressor material includes a dual-use film. A second isolation trench is formed within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench. The presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a <100> or <110> semiconductor-on-insulator substrate.

Abstract: A method for fabricating a semiconductor device including on a single semiconductor substrate, a first MOS transistor having a first gate insulating film of a predetermined thickness, and second and third MOS transistors sharing a second gate insulating film smaller in thickness than the first gate insulating film, the third MOS transistor being lower in threshold voltage than the second MOS transistor, the method includes the steps of: adjusting the threshold voltages of the first and third MOS transistors by first ion-implantation; and adjusting the threshold voltage of the second MOS transistor by second ion-implantation, the second ion-implantation being performed under implantation conditions different from those of the first ion-implantation.

Abstract: A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.

Abstract: A carbon containing masking layer is patterned to include a plurality of container openings therein having minimum feature dimensions of less than or equal to 0.20 micron. The container openings respectively have at least three peripheral corner areas which are each rounded. The container forming layer is plasma etched through the masking layer openings. In one implementation, such plasma etching uses conditions effective to both a) etch the masking layer to modify shape of the masking layer openings by at least reducing degree of roundness of the at least three corners in the masking layer, and b) form container openings in the container forming layer of the modified shapes. Capacitors comprising container shapes are formed using the container openings in the container forming layer. Other implementations and aspects are disclosed.

Abstract: A substrate has an active region divided into storage node contact junction regions, channel regions and a bit line contact junction region. Device isolation layers are formed in the substrate isolating the active region from a neighboring active region Recess patterns are formed each in a trench structure and extending from a storage node contact junction region to a channel region Line type gate patterns, each filling a predetermined portion of the trench of the individual recess pattern, is formed in a direction crossing a major axis of the active region in an upper portion of the individual channel region.

Abstract: The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon.

Abstract: In a capacitor of a semiconductor device, a bottom electrode is formed on a substrate and has an uneven top surface. An interlayer insulation layer is formed on the substrate and has a via hole exposing the top surface of the bottom electrode. A dielectric layer is formed unevenly on the bottom electrode. A top electrode is formed on the dielectric layer while filling the via hole.

Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.

Abstract: NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array. A second gate stack is formed on a second dielectric layer that is formed on the substrate adjacent the first dielectric layer. The second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent an end of the NAND string. The second dielectric layer is thicker than the first dielectric layer.

Abstract: A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing th

Abstract: The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.

Abstract: A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.

Abstract: A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.

Abstract: A semiconductor device may include first, second, and third semiconductor layers. The first and third layers may have a first dopant type, and the second layer may have a second dopant type. A first region within the third semiconductor layer may have the second dopant type. A second region between the first region and the second semiconductor layer may have the first dopant type. A third region above the second region may have the first dopant type. A fourth semiconductor region adjacent to the third region may have a first concentration of the second dopant type. A source contact region may have a second concentration of the second dopant type adjacent to the third semiconductor region and adjacent to the fourth semiconductor region. The second concentration may be higher than the first concentration.

Abstract: An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.

Abstract: Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A semiconductor device composed of III-nitride materials is produced with epitaxial growth that permits vertical and lateral growth geometries to improve device characteristics. The resulting device has a greater breakdown voltage due to the greater integrity of the semiconductor material structure since no ion implantation processes are used. The epitaxially grown layers also exhibit greater thermal conductivity for improved operation with power semiconductor devices. The device may include a laterally grown charge compensated area to form a superjunction device. The resulting device may be bidirectional and have improved breakdown voltage in addition to higher current capacity for a given voltage rating.

Abstract: Methodologies associated with fabricating aligned nanowire lattices are described. One exemplary method embodiment includes providing a twist wafer bonded thin single crystal semiconductor film and a bulk single crystal substrate of the same material. Periodic non-uniform elastic strains present on the surface of the film control the positions where nanocrystals will form on the film. The strains may be removed via annealing and alloying after the formation of nanocrystal arrays.

Abstract: A semiconductor device (2) includes a semiconductor substrate (12) having a surface (13) formed with a first recessed region (20). A first dielectric material (60) is deposited in the first recessed region and formed with a second recessed region (76), and a second dielectric material (100) is grown over the first dielectric material to seal the second recessed region.

Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is placed within a reaction chamber. The substrate comprises a center region and an edge region surrounding the center region. The substrate comprises openings within the center region, and openings within the edge region. While the substrate is within the reaction chamber, a layer of insulative material is formed across the substrate. The layer is thicker over the one of the center region and edge region than over the other of the center region and edge region. The layer is exposed to an etch which removes the insulative material faster from over the one of the center region and edge region than from over the other of the center region and edge region.

Abstract: The present invention provides a manufacturing method for an SOI wafer with a high productivity in which generation of a void is suppressed in manufacturing the SOI wafer. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers each with no line defect on a surface thereof are used. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers are subjected to a high temperature heat treatment in advance.

Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface, implanting atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer, and bonding the free surface of the second layer to a host wafer. The method also includes supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer, conducting a bond strengthening step on the structure after detachment at a temperature of less than about 800° C. to improve the strength of the bond between the second layer and the host wafer, and selectively etching the first layer portion to remove it from the structure and to expose a surface of the second layer.

Abstract: A method for producing an ultra-thin semiconductor chip and an ultra-thin back-illuminated solid-state image pickup device utilizing a semiconductor layer formed on a support substrate via an insulating layer to improve separation performance of a semiconductor layer from a support substrate and thereby improve the productivity and quality. The method uses two porous peeling layers on opposite sides of a substrate to produce an ultra-thin substrate.

Abstract: Provided is a method of manufacturing a silicon on insulator (SOI) substrate, which includes the steps of (a) forming a buried oxidation layer to a predetermined depth of a first wafer and forming an oxidation layer on a surface of the first wafer; (b) bonding a second wafer onto the first wafer; (c) selectively removing the oxidation layer so as to expose a bottom surface of the first wafer; (d) selectively removing the exposed bottom silicon layer of the first wafer using the buried oxidation layer as an etch stop layer; and (e) removing the buried oxidation layer to expose a top surface of the first wafer, and thinning the exposed top surface of the first wafer to a predetermined thickness, so that a process can be relatively simple and can be readily carried out, thereby manufacturing an SOI substrate having a uniform silicon thickness of high quality and an ultra thin characteristic.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: A programmable dopant fiber includes a plurality of quantum structures formed on a fiber-shaped substrate, wherein the substrate includes one or more energy-carrying control paths, which pass energy to quantum structures. Quantum structures may include quantum dot particles on the surface of the fiber or electrodes on top of barrier layers and a transport layer, which form quantum dot devices. The energy passing through the control paths drives charge carriers into the quantum dots, leading to the formation of “artificial atoms” with real-time, tunable properties. These artificial atoms then serve as programmable dopants, which alter the behavior of surrounding materials. The fiber can be used as a programmable dopant inside bulk materials, as a building block for new materials with unique properties, or as a substitute for quantum dots or quantum wires in certain applications.

Abstract: The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

Abstract: A method for manufacturing a semiconductor device having a semiconductor substrate with a contact hole filled by an aluminum-containing thin film. This manufacturing method includes a step of forming a silicon-containing thin film in a region having a predetermined area including the inner surface of the contact hole on the surface of the semiconductor substrate, an step of forming an aluminum-containing thin film on the surface of the semiconductor substrate on which the silicon-containing thin film is formed, and a step of heating the semiconductor substrate on which the aluminum-containing thin film is formed to such a temperature as to cause silicon to diffuse with respect to aluminum.

Abstract: An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.

Abstract: A semiconductor bear chip having a bump subjected to high temperatures is pressed, from the upper side, onto a wiring board including a wiring pattern, a thermosetting resin film covering an electrode area on the wiring pattern and having insulating particles dispersed and included and a thermoplastic resin film covering the thermosetting resin film, while applying a ultrasonic wave, thereby inserting the bumps of the semiconductor bear chip through the thermoplastic resin film and the thermosetting resin film to bond the top end portion of the bump with the electrode area.

Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.

Abstract: A method of manufacturing a wiring substrate of the present invention, includes a step of preparing a substrate containing a semi-cured resin layer or a thermo plastic resin layer, a step of forming a through hole that passes through the substrate, a step of inserting a conductive parts in the through hole, a step of curing the semi-resin layer or the thermo plastic resin layer in a state that the resin layer is made to flow by applying a thermal press to the substrate and filling a clearance between the through hole and the conductive parts with the resin layer, and a step of forming a wiring pattern, which is connected mutually via the conductive parts, on both surface sides of the substrate.

Abstract: A method for forming a contact hole for a dual damascene interconnection in a semiconductor device. A via hole is formed to expose an etch stop film on a lower metal film through an intermetal insulating film. The via hole is filled with a sacrificial film. A bottom antireflective coating film and a mask pattern are formed on the intermetal insulating film and the sacrificial film. An etching process is performed to form a trench to expose a portion of a surface of the intermetal insulating film and a top surface of the sacrificial film. A post etch treatment is performed to remove the sacrificial film, using the mask pattern as an etching mask. The exposed etch stop film is removed to expose a portion of a surface of the lower metal film. A passivation process is performed for the exposed surface of the lower metal film.

Abstract: In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.

Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

Abstract: A method for depositing metal on a semiconductor device having a substrate, an exposed first surface, and an exposed second surface is provided. Metal ions are deposited on the exposed first surface and on the exposed second layer by applying a first voltage between the substrate and an anode in the presence of an electrolytic bath, and metal ions are removed from the exposed first surface by applying a second voltage between the substrate and the anode in the presence of the electrolytic bath. Other aspects and embodiments are provided herein.

Abstract: Disclosed is a method for forming a metal wiring in a semiconductor device in order to improve the operational speed of the semiconductor device. The method includes the steps of depositing an interlayer dielectric film on a silicon substrate, in which the interlayer dielectric film has a contact hole for exposing a predetermined portion of the silicon substrate, depositing a barrier layer on the interlayer dielectric film having the contact hole, depositing a first tungsten layer on the barrier layer by using SiH4 as a reaction gas, depositing a second tungsten layer on the first tungsten layer by using B2H6 as a reaction gas, depositing a third tungsten layer on the second tungsten layer in such a manner that the contact hole is filled with the third tungsten layer, and selectively etching the third tungsten layer, the second tungsten layer, the first tungsten layer, and the barrier layer, thereby forming the metal wiring.

Abstract: A method for depositing a metal compound film on the wafer by using a vapor phase deposition apparatus 100, including: forming a thin film on the wafer in an interior of the vapor phase deposition apparatus 100 by introducing a source gas for the metal compound film containing Hf or Zr; unloading the wafer having the metal compound film formed thereon from the interior of the vapor phase deposition apparatus 100; introducing a reactive gas in the interior of the vapor phase deposition apparatus 100 to immobilize the unreacted organic compound 180 derived from the source gas remained in the interior of the vapor phase deposition apparatus 100; loading another wafer in the interior of the vapor phase deposition apparatus 100; and depositing metal compound film on another wafer by further introducing the source gas in the interior of the vapor phase deposition apparatus 100, in the condition that the unreacted organic compound 180 exists therein as an immobilized form, is presented.

Abstract: A method for forming a pattern is provided that includes: providing a cliché having a plurality of convex patterns; applying an adhesive force reinforcing agent onto each surface of the convex patterns; forming an etching object layer on a substrate and then applying ink onto an upper portion of the etching object layer; attaching the cliché and the substrate to each other such that the convex patterns onto which the adhesive force reinforcing agent is applied can come in contact with the ink applied onto the etching object layer; and forming ink patterns which selectively remain on the etching object layer by separating the substrate and the cliché from each other.

Abstract: Planarizing solutions, planarizing machines and methods for planarizing microelectronic-device substrate assemblies using mechanical and/or chemical-mechanical planarizing processes. In one aspect of the invention, a microelectronic-device substrate assembly is planarized by abrading material from the substrate assembly using a plurality of first abrasive particles and removing material from the substrate assembly using a plurality second abrasive particles. The first abrasive particles have a first planarizing attribute, and the second abrasive particles have a second planarizing attribute. The first and second planarizing attributes are different from one another to preferably selectively remove topographical features from substrate assembly and/or selectively remove different types of material at the substrate surface.

Abstract: A plasma etch process for etching a porous carbon-doped silicon oxide dielectric layer using a photoresist mask is carried out first in an etch reactor by performing a fluoro-carbon based etch process on the workpiece to etch exposed portions of the dielectric layer while depositing protective fluoro-carbon polymer on the photoresist mask. Then, in an ashing reactor, polymer and photoresist are removed by heating the workpiece to over 100 degrees C., exposing a peripheral portion of the backside of said workpiece, and providing products from a plasma of a hydrogen process gas to reduce carbon contained in polymer and photoresist on said workpiece until the polymer has been removed from a backside of said workpiece. The process gas preferably contains both hydrogen gas and water vapor, although the primary constituent is hydrogen gas. The wafer (workpiece) backside may be exposed by extending the wafer lift pins.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: A method for moving resist stripper across the surface of a semiconductor substrate includes applying a wet chemical resist stripper, such as an organic or oxidizing wet chemical resist stripper, to at least a portion of a photomask positioned over the semiconductor substrate. A carrier fluid, such as a gas, is then directed toward the semiconductor substrate so as to move the resist stripper across the substrate. The carrier fluid may be directed toward the substrate as the resist stripper is being applied thereto or following application of the resist stripper. A system for effecting the method is also disclosed.

Abstract: Methods of etching a dielectric layer and a cap layer over a conductor to expose the conductor are disclosed. In one embodiment, the methods include the use of a silicon dioxide (SiO2) etching chemistry including octafluorocyclobutane (C4F8) and a titanium nitride (TiN) etching chemistry including tetrafluoro methane (CF4). The methods prevent etch rate degradation and exhibit reduced electro-static discharge (ESD) defects.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a bit line contact region and a storage node contact region are simultaneously formed, and then a storage node contact hole is formed after a form of bit line to reduce a height of a finally formed storage node contact plug, thereby increasing a storage node open area and reducing a short circuit between the bit lines.

Abstract: A method for removing mottled etch in a semiconductor fabricating process, prevents mottled etch from being generated after etching, by performing ashing using an oxide plasma, prior to performing wet etching using a photoresist pattern. The method for removing the mottled etch includes the steps of forming a gate oxide film on a semiconductor substrate; forming a photoresist pattern on the substrate; performing ashing using an oxygen plasma; and removing the oxide film consequently by wet etching, the oxide film being opened by the pattern.

Abstract: An electronic device having a substrate structure having an undercut region is provided and further included is a method for forming an undercut region of a substrate structure. The method includes forming a patterned protective layer over a first electrode. The method also includes forming the substrate structure over the patterned protective layer. An opening within the substrate structure overlies an exposed portion of the substrate structure. The method further includes removing the exposed portion of the patterned protective layer, thereby exposing a portion of the first electrode and forming an undercut region of the substrate structure. The method still further includes depositing a liquid over the first electrode after removing the exposed portion of the patterned protective layer, and solidifying the liquid to form a solid layer.

Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.