Abstract: A radiation detector comprises pixel electrodes which collect charges, a photoelectric converting layer which is provided on the pixel electrodes and which converts incident radiation into the charges, and which contains at least one or more kinds of heavy metal halide (ABn:A=heavy metal, B=halogen, n=either one of 1, 2, and 3) and at least one or more kinds of halogen (B2) respectively, and an electrode layer which is provided on the photoelectric converting layer opposite to the pixel electrodes.

Abstract: A deflector which deflects a charged particle beam includes a substrate having an opening through which the charged particle beam should pass, and a deflection electrode which is arranged in the opening to deflect the charged particle beam and has a first conductive member and second conductive member which are formed by plating. The second conductive member is formed on a surface of the first conductive member and is essentially made of a material that is more difficult to oxidize than the first conductive member.

Abstract: Disclosed is a diagnostic resonant cavity for determining characteristics of a charged particle beam, such as an electron beam, produced in a charged particle accelerator. The cavity is based on resonant quadrupole-mode and higher order cavities. Enhanced shunt impedance in such cavities is obtained by the incorporation of a set of four or more electrically conductive rods extending inwardly from either one or both of the end walls of the cavity, so as to form capacitive gaps near the outer radius of the beam tube. For typical diagnostic cavity applications, a five-fold increase in shunt impedance can be obtained. In alternative embodiments the cavity may include either four or more opposing pairs of rods which extend coaxially toward one another from the opposite end walls of the cavity and are spaced from one another to form capacitative gaps; or the cavity may include a single set of individual rods that extend from one end wall to a point adjacent the opposing end wall.

Abstract: To achieve high-resolution lithography, the temperature of a sample is controlled with heater wires during electron-beam lithography, the adverse effect of a magnetic field induced by the heater current is suppressed. Namely, heater wires are used to control the temperature of a sample so that the temperature will be maintained constant. In order to minimize the adverse effect of a magnetic field during the passage of currents through the heater wires, two heater wires are layered with the arrangement of the upper and lower sides, currents are fed to flow through the heater wires in mutually opposite directions, and the ratio of the current flowing through the upper heater wire to the one flowing through the lower heater wire is slightly changed from zero.

Abstract: A light source unit supplies the light radiated from the plasma, and includes a stabilizer for reducing a fluctuation of a position of the light radiated from the plasma.

Abstract: A beam space-charge compensation device is applied to an angular energy filter provided in an ion beam processing system that performs processing by irradiating onto a wafer with an ion beam. The beam space-charge compensation device comprises a plasma shower provided in a beam-guiding chamber of the angular energy filter. The plasma shower comprises an arc chamber having a filament for generating thermo-electrons for plasma. The arc chamber comprises an extraction hole for extracting the thermo-electrons. The plasma shower is arranged such that the extraction hole is located on lines of magnetic force, perpendicular to an ion beam advancing direction, of the magnetic field and that a center axis of the filament and a center axis of said extraction hole coincide with the lines of magnetic force, perpendicular to the ion beam advancing direction, of the magnetic field.

Abstract: An ion beam implanter includes an ion beam source for generating an ion beam moving along a beam line and an implantation chamber wherein a workpiece is positioned to intersect the ion beam for ion implantation of an implantation surface of the workpiece by the ion beam. The implanter further includes a workpiece support structure coupled to the implantation chamber and supporting the workpiece within an interior region of the implantation chamber, the workpiece support structure. The workpiece support structure includes a rotation member coupled to the implantation chamber for changing an implantation angle of the workpiece with respect to a portion of the ion beam within the implantation chamber. The workpiece support structure also includes a translation member movably coupled to the rotation member and supporting the workpiece for movement along a path of travel wherein at least some components of the translation member components are disposed within a reduced pressure translation member chamber.

Abstract: A method for correcting angle zero position of an ion implantation equipment. The method includes loading a semiconductor wafer into the ion implantation equipment, implanting ions into the wafer with varying angle, measuring thermal wave and sheet resistance value of the wafer, and correcting the angle zero position with reference to points at which the measured thermal wave or sheet resistance value is minimized.

Abstract: In a pattern definition device for use in a particle-beam processing apparatus a plurality of apertures (21) are arranged within a pattern definition field (pf) wherein the positions of the apertures (21) in the pattern definition field (pf) taken with respect to a direction (X, Y) perpendicular, or parallel, to the scanning direction are offset to each other by not only multiple integers of the effective width (w) of an aperture taken along said direction, but also multiple integers of an integer fraction of said effective width. The pattern definition field (pf) may be segmented into several domains (D) composed of a many staggered lines (pl) of apertures; along the direction perpendicular to the scanning direction, the apertures of a domain are offset to each other by multiple integers of the effective width (w), whereas the offsets of apertures of different domains are integer fractions of that width.

Abstract: A system for handling a radioactive source includes a container containing a radioactive source and a cap mounted on the container to retain the radioactive source inside the container. The cap has a first locking structure and a second locking structure. The system further includes a handling tool having a support shaft, a first locking tip adapted to form a first lock with the first locking structure, and a second locking tip adapted to form a second lock with the second locking structure. The first and second locking tips are slidably coupled to the support shaft.

Abstract: A radiation protection system for shielding medical personnel from a gamma ray source being used to provide brachytherapy to a patient is provided by disposing shielding material between the source of radiation and locations outside the radiation protection system in such a manner as to provide shielding for the primary radiation in directions from which radiation from the source may emerge, while providing the patient an open viewing area with a large field of view for the patient to view the locations outside the radiation protection system. The described system reduces the radiation exposure of staff in the treatment room, thereby permitting physicians and therapists to observe the patient without being exposed to excessive amounts of radiation. The opening in the radiation protection system around the head of the patient provides the ability for the patient to see his surroundings and to eliminate the anxiety resulting from the feeling of being closed in.

Abstract: A measuring apparatus for measuring optical performance of a target optical system to be measured includes an optical unit for splitting light from a light source into measuring light and reference light so that the measuring light can be introduced into the target optical system, a reflection unit for reflecting the measuring light from the target optical system toward the target optical system via a fluid, and a detector for detecting an interference fringe generated between interference between the measuring light that has emitted from the target optical system after being reflected by the reflection unit and the reference light that does not pass the target optical system.

Abstract: A device for examining the optical properties of surfaces having at least one first radiation device emitting radiation at least at one first predetermined spatial angle to a surface to be examined, at least one first detector device for capturing the radiation emitted to and reflected back from the surface, wherein the detector device allows a local resolution of detected radiation and is positioned at least at a second predetermined spatial angle relative to the surface. At least one spatial angle at which the radiation device and/or the detector device are positioned, is variable.

Abstract: The present invention relates to apparatus, systems, and methods for analyzing biological samples. The apparatus, systems, and methods can involve using a vacuum source to pull microfluidic volumes through analytical equipment, such as flow cells and the like. Additionally, the invention involves using optical equipment in conjunction with the analytical equipment to analyze samples and control the operation thereof.

Abstract: A radiation image read-out method and apparatus for a stimulable phosphor sheet, provided with a layer of stimulable phosphor, which has been exposed to radiation to carry information about an image, and the image is thereby stored on the stimulable phosphor sheet. The method includes the steps of: exposing the stimulable phosphor sheet to stimulating rays to emit light in proportion to the amount of energy stored thereon during its exposure to radiation; sensing the emitted light to generate a detection signal; amplifying the detection signal using a first amplifier or a second amplifier, dependent on the magnitude of the detection signal, to generate an amplified detection signal, the first amplifier differing from the second amplifier; and converting the amplified detection signals into a digital signal to form a digital image. In a preferred embodiment, the first and second amplifiers are logarithmic and linear amplifiers.

Abstract: A non-volatile memory cell utilizes a programmable conductor random access memory (PCRAM) structure instead of a polysilicon layer for a floating gate. Instead of storing or removing electrons from a floating gate, the programmable conductor is switched between its low and high resistive states to operate the flash memory cell. The resulting cell can be erased faster and has better endurance than a conventional flash memory cell.

Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3-10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.

Abstract: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One or more vias are formed through the active layer, transparent conducting layer and insulating layer of the first device module. Sidewalls of the vias are coated with an insulating material such that a channel is formed through the insulating material to the backside top electrode of the first device module. The channel is at least partially filled with an electrically conductive material to form a plug that makes electrical contact between the transparent conducting layer and the backside top electrode of the first device module.

Abstract: The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing a first barrier metal layer of a Ti film on the entire upper surface thereof; and vapor-depositing, on the upper part of the Ti film, a second barrier metal layer of a ZrB2 film having different upper and lower Boron concentrations, by RPECVD controlling the presence/absence of H2 plasma, wherein the barrier metal layer includes the Ti film, lower ZrB2 film and upper a ZrB2 film sequentially stacked between tungsten bit lines and ion implantation region of a semiconductor substrate.

Abstract: The present invention is generally directed to electroluminescent Ir(III) compounds, the substituted 2-phenylpyridines, phenylpyrimidines, and phenylquinolines that are used to make the Ir(III) compounds, and devices that are made with the Ir(III) compounds.

Abstract: An electronic device includes first and second electrical contacts electrically coupled to a semiconductor polymer film, which includes mono-substituted diphenylhydrazone.

Abstract: A vertical organic transistor comprises a substrate, a first electrode positioned over the substrate, a first semiconductor layer formed over the first electrode, a second electrode formed on the first semiconductor layer and shaped into a prescribed pattern, a second semiconductor layer formed over the second electrode and the first semiconductor layer, and a third electrode formed over the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are made of different semiconductor materials.

Abstract: Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layers and capacitor dielectric layers in various integrated circuit devices.

Abstract: In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 113a are provided in an n-channel TFT. The LDD regions 107a and 107b overlap the first wiring line 102a and not overlap the second wiring line 113a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.

Abstract: In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads.

Abstract: A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.

Abstract: A NAND memory array has a select line coupled to each of a plurality of NAND strings of memory cells of the memory array. The select line has a select gate at each intersection of one of the plurality of NAND strings and the select line. The select line further includes first and second conductive layers separated by a dielectric layer, and a contact that extends from a third conductive layer, disposed on the second conductive layer, to the first conductive layer. The contact is formed in a hole that passes through the second conductive layer and the dielectric layer and that terminates at the first conductive layer. The contact electrically connects the first and second conductive layers. The hole can have a slot shape so that the contact spans two or more NAND strings of the plurality of NAND strings.

Abstract: A low-cost high-property optical semiconductor element for a long wavelength is provided, using a GaAs substrate. The optical semiconductor element comprises a substrate of GaAs having a first surface and a second surface opposite to each other, a buffer layer of InjGa1-jAs1-kNk (0?j?1, 0.002?k?0.05) formed on the first surface of the substrate, a first conductive type clad layer formed on the buffer layer, an active layer formed on the first conductive type clad layer and comprising a well layer of InzGa1-zAs (0?z?1), the well layer having a smaller bandgap than the first conductive type clad layer, the active layer having a thickness of more than its critical thickness for the substrate based upon equilibrium theories, and a second conductive type clad layer formed on the active layer and having a larger bandgap than the well layer.

Abstract: The wavelength-converting casting composition is based on a transparent epoxy casting resin with a luminous substance admixed. The composition is used in an electroluminescent component having a body that emits ultraviolet, blue or green light. An inorganic luminous substance pigment powder with luminous substance pigments is dispersed in the transparent epoxy casting resin. The luminous substance is a powder of Ce-doped phosphors and the luminous substance pigments have particle sizes ?20 ?m and a mean grain diameter d50?5 ?m.

Abstract: A device includes a light emitting semiconductor device bonded to an optical element. In some embodiments, the optical element may be elongated or shaped to direct a portion of light emitted by the active region in a direction substantially perpendicular to a central axis of the semiconductor light emitting device and the optical element. In some embodiments, the semiconductor light emitting device and optical element are positioned in a reflector or adjacent to a light guide. The optical element may be bonded to the first semiconductor light emitting device by a bond at an interface disposed between the optical element and the semiconductor light emitting device. In some embodiments, the bond is substantially free of organic-based adhesives.

Abstract: A method of manufacturing an optical element including the steps of: forming a through hole in a semiconductor element which has an optical section and an electrode electrically connected to the optical section; and forming a conductive layer extending from a first surface of the semiconductor element on which the optical section is formed, through an inner wall surface of the through hole, to a second surface opposite to the first surface.

Abstract: A light emitting diode (LED) includes a LED chip, which can transfer electrical power to electric-magnetic wave. A set of lead frame is enclosed by electrical isolator material to form a cavity. An optics lens seats on top of the cavity and is bonded to said electrical isolator material. A submount to carry said LED chip is soldered or adhered to the lead frame and forms the electrical contact from said LED chip to lead frame. A high transparency material is utilized to enclosed the LED chip.

Abstract: A submount for a light emitting device package is provided. The submount includes a substrate; a first bonding layer and a second bonding layer which are separately formed on the substrate; a first barrier layer and a second barrier layer which are formed on the first bonding layer and on the second bonding layer, respectively; a first solder and a second solder which are formed on the first barrier layer and on the second barrier layer, respectively; and a first blocking layer and a second blocking layer which are formed around the first barrier layer and the second barrier layer, blocking the melted first solder and the melted second solder from overflowing during a flip chip process.

Abstract: The leads of a light emitting diode are made coaxial. The inner lead protrudes lower than the outer lead. The package is inserted into a spongy display panel for power supply. The display panel has three layers: a lower conducting layer for contacting said inner lead and a top conducting layer for contacting said outer layer, and an insulating layer between the top and the bottom layer. For LED with a bottom electrode and a top electrode, the LED can be mounted on the planar tops of the inner lead and the top electrode wire bonded to the outer lead, or the LED can be mounted on the side surface of the inner lead and the top electrode wire bonded to the outer lead. For LED with two bottom electrode, the LED electrodes can straddle over the planar tops of the inner lead and the outer lead, or the LED electrodes can straddle over the telescopic side surfaces of the two leads.

Abstract: A compound semiconductor light emitting device for preparing a chip which improves the light extraction efficiency, enables mounting of easy positioning with only once wire bonding, and leads to a reduction in the manhour. One face of an insulative substrate (11) is overlaid with a semiconductor layer (4) consisting of a plurality of semiconductor thin films to form an active layer (15). One electrode (33) is formed on the top face of this semiconductor layer (4), and the other electrode (33) on the other face of the insulative substrate (11). For the exposure of a first semiconductor thin film layer (13) connected to the other electrode (33), the semiconductor film over the first semiconductor thin film layer (13) is removed to form an exposure region (10). This exposure region (10) is provided with a through hole (2) penetrating through the insulative substrate (11) and first semiconductor thin film layer (13).

Abstract: A retaining ring for use with electrochemical mechanical processing is described. The retaining ring has a generally annular body formed with a conductive portion and a non-conductive portion. The non-conductive portion contacts the substrate during polishing. The conductive portion is electrically biased during polishing to reduce the edge effect that tends to occur with conventional electrochemical mechanical processing systems.

Abstract: This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity. For the collector-up HBT, window structures around the sidewalls of a collector are used to etch either the emitter layer disposed directly under the external base layer, or an emitter contact layer For the emitter-up HBT, window structures around the sidewalls of an emitter are used to etch either the collector layer disposed directly under the external base layer, or a collector contact layer. In both HBTs, the external base layer is supported by a columnar structure to ensure mechanical strength.

Abstract: The present invention provides a gas sensor having excellent humidity resistance even if used in a high temperature and high humidity atmosphere. According to the present invention, a gas sensor is comprised of: a silicon substrate; a metal-oxide semiconductor portion comprised mainly of SnO2 and formed on the substrate; and a catalytic portion comprised of Pd and dispersed on a surface of the metal-oxide semiconductor portion, wherein the metal-oxide semiconductor portion and the catalytic portion constitute a gas sensing portion. Furthermore, an insulating portion comprised mainly of SiO2 is formed dispersedly on a surface of the gas sensing portion.

Abstract: Integrated circuit varactors and methods for varactor fabrication are provided. Varactors are formed on integrated circuits that contain complementary metal-oxide-semiconductor (CMOS) transistors. The same semiconductor fabrication process steps are used to form both the varactors and CMOS transistors, thereby eliminating potentially cost-prohibitive changes to manufacturing process flows. Varactor performance is enhanced by including a deep n-well structure. The deep n-well reduces sheet resistance in the semiconductor portion of the varactor and improves the varactor's quality factor. The deep n-well is formed from the same deep n-well layer that is used to form the CMOS transistors on the integrated circuit. The varactor has two active electrodes. The electrodes are spaced farther apart than specified by semiconductor fabrication design rules. The number of contact vias used in one of the electrodes is less than the maximum specified by the design rules.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a screening electrode spaced apart from a channel region.

Abstract: An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.

Abstract: A microcrystalline germanium image sensor array. The array includes a number of pixel circuits fabricated in or on a substrate. Each pixel circuit comprises a charge collecting electrode for collecting electrical charges and a readout means for reading out the charges collected by the charge collecting electrode. A photodiode layer of charge generating material located above the pixel circuits convert electromagnetic radiation into electrical charges. This photodiode layer includes microcrystalline germanium and defines at least an n-layer, and i-layer and a p-layer. The sensor array also includes and a surface electrode in the form of a grid or thin transparent layer located above the layer of charge generating material. The sensor is especially useful for imaging in visible and near infrared spectral regions of the electromagnetic spectrum and provides imaging with starlight illumination.

Abstract: A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench and electrically connected to a storage electrode of the capacitor; a select transistor provided on a surface of the semiconductor substrate and having a source region in contact with the trench; a spacer covering a side of the source region; and a surface strap contact arranged upon the spacers, the source region and the storage node.

Abstract: The present invention relates to a semiconductor device that contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region. The present invention also relates to a fabrication process, which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material.

Abstract: This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an integrated circuit includes forming a trench isolation mask over a semiconductor substrate. The trench isolation mask defines an active area region and a trench isolation region. An ion implantion is conducted into semiconductive material of the substrate to form a buried region within active area of the substrate. The buried region has a first edge received proximate an edge of the trench isolation region. Using the trench isolation mask, etching is conducted into semiconductive material of the substrate to form an isolation trench. After the ion implantation and after forming the isolation trench, insulative material is formed within the buried region and insulative material is deposited to within the isolation trench. The insulative material received within the isolation trench joins with the insulative material formed within the buried region.

Abstract: A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed in the substrate on one side of the deep trench capacitor. The trench exposes a portion of the upper electrode of the deep trench capacitor and a portion of the substrate. After that, a semiconductor strip is formed in the trench. A gate dielectric layer is formed over the substrate to cover the exposed semiconductor strip and the substrate. A gate is formed over the gate dielectric layer such that the gate and the semiconductor strip crosses over each other, and the gate-covered portion of the semiconductor strip serves as a channel region.

Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: An integrated circuit having a plurality of active areas separated from each other by a field region and a method for manufacturing the integrated circuit. A first polysilicon finger is formed over the first active area and the field region and a second polysilicon finger is formed over the second active area and the field region. A first dielectric layer is formed over the first active area and the field region and a second dielectric layer is formed over the second active area and the portion of the first dielectric layer over the field region. A first electrical interconnect is formed over and dielectrically isolated from the first polysilicon finger and a second electrical interconnect is formed over and dielectrically isolated from the second active area. The second electrical interconnect is electrically coupled to the second polysilicon finger.

Abstract: The invention includes a method of forming an array of memory cells. A series of capacitor constructions is formed, with the individual capacitor constructions having storage nodes. The capacitor constructions are defined to include a first set of capacitor constructions and a second set of capacitor constructions. A series of electrically conductive transistor gates are formed over the capacitor constructions and in electrical connection with the capacitor constructions. The transistor gates are defined to include a first set that is in electrical connection with the storage nodes of the first set of capacitor constructions, and a second set that is in electrical connection with the storage nodes of the second set of capacitor constructions. A first conductive line is formed over the transistor gates and in electrical connection with the first set of transistor gates, and a second conductive line is formed over the first conductive line and in electrical connection with the second set of transistor gates.

Abstract: A semiconductor device includes a semiconductor substrate including a first upper surface, a first insulating film including an upper portion including a first side wall having a first upper end and a second upper surface having a second upper end, a second insulating film formed on the first upper surface of the substrate, a floating gate electrode including a third upper surface, a second side wall and a lower surface, a third insulating film, and a control gate electrode. A height of the second upper end is lower than a height of the third upper surface and higher than a height of the first upper end relative to the first upper surface. The first upper end is located at a position higher than the lower surface of the floating gate electrode. The entire second side wall is aligned with the first side wall of the first insulating film.