Abstract: A self-tuning resonator for use in a transmitter apparatus for inducing alternating currents in a buried conductor. The resonator is dynamically tuned at frequencies below 500 kHz by exploiting the inherent voltage-variability of net capacitance in multilayer ceramic capacitors. The transmitter apparatus provides improved efficiency and induced output power suitable for use in a man-portable locator system, providing a very high magnetic field output from a physically small battery-powered resonator at frequencies under 500 kHz. The resonator exhibits a very low equivalent series resistance (ESR) and is adaptively returned to a predetermined resonant frequency responsive to any changes in resonance arising from phenomena such as component heating, thereby supporting very high tank circuit currents from battery-powered source to produce very high magnetic flux output.

Abstract: A system for locating a malfunctioning bulb in a decorative light string uses an antenna that produces an output signal corresponding to the strength of the electric field produced by a portion of the light string near the antenna. An amplifier is coupled to the antenna to receive the antenna output signal and produce an amplified output signal representing the strength of the electric field. The amplifier includes a negative feedback circuit to improve the stability of the amplifier. A detector receives the amplifier output signal and activates an alarm device when the amplifier output signal is above or below a predetermined threshold representing a known operational condition of the light string.

Abstract: The invention proposes a method for operating an evaluation circuit for an electrochemical cell wherein the evaluation circuit is switched on for a first time period and is switched off for a second time period. The ratio between the first and the second time periods is selected to be less than 1. The measurement value of the electrochemical cell undergoes a current amplification in the evaluation circuit.

Abstract: A cable tester tests cable to determine a cable status. A mode selector selects one of a first operating mode and a second operating mode. A pretest module senses activity on the cable and selectively enables testing based on the sensed activity when in the first operating mode and enables testing when in the second operating mode. A test module is enabled by the pretest module, transmits a test pulse on the cable, measures a reflection amplitude and calculates a cable length. The cable status includes an open status, a normal status and a short status. The test module determines the cable status based on the measured amplitude and the calculated cable length.

Abstract: A system for detecting a defect or discontinuity in media or at an interface of the media includes a signal generator; a transmission path coupled to the signal generator, wherein the transmission path is arranged along or through the media; a detection circuit for detecting a transmitted and a detected portion of a signal provided by the signal generator; and a circuit for analyzing the reflected portion and identifying a location of a discontinuity or defect in the media. A related method of detecting a defect or discontinuity in media or at an interface between the media includes establishing an electromagnetic energy path along or through the media; coupling electromagnetic energy into the path; detecting a reflected portion of the electromagnetic energy; and analyzing the detected portion so as to determine a position of the defect or discontinuity.

Abstract: A system and method that allows a consumer to monitor the electrical power usage in a residence is disclosed. The electrical use may be monitored at the service level, the circuit level, or at the group level. The electrical usage is communicated to a power monitoring system using a power line communications network (PLC). The monitored electrical usage can be accessed by both the utility supplying the electricity and by the consumer or owner of the residence.

Abstract: The present invention relates to a method and an arrangement of measuring conductive component content of a multiphase fluid flow and uses thereof. The claimed device comprises two coils arranged around the pipe containing the fluid to be measured, where the induced power loss in the mixture is determined, thereby determining the content of the conductive component. Alternatively, a number of coils are arranged on the outside surface of the fluid transporting pipe and the power loss or attenuation of magnetic field is determined.

Abstract: The invention relates to a flexible, resilient capacitive sensor suitable for large-scale manufacturing. The sensor includes a dielectric, an electrically conductive detector and trace layer on the first side of the dielectric layer including a detector and trace, an electrically conductive reference layer on a second side of the dielectric layer, and a capacitance meter electrically connected to the trace and to the conductive reference layer to detect changes in capacitance upon interaction with detector. The sensor is shielded to reduce the effects of outside interference.

Abstract: The present invention provides a sensor and apparatus for measuring flow electric potential for evaluation of a degree of electrodeposition of paint applied to the body or chassis of a vehicle. The sensor includes a base plate part, a dielectric polymer member, a positive (+) electrode terminal and a negative (?) electrode terminal, and an insulation part. The base plate part is mounted on the outer and inner body or chassis of a vehicle, and is electrically connected to ground. The dielectric polymer member is patterned and formed on the base plate part. The positive (+) electrode terminal is connected to the dielectric polymer member and is configured to have a positive (+) polarity. The negative (?) electrode terminal is connected to the base plate part and is configured to have a negative (?) polarity. The insulation part is formed to insulate the positive (+) and negative (?) electrode terminals from each other.

Abstract: A high density integrated test probe and method of fabrication is described. A group of wires are ball bonded to contact locations on the surface of a fan out substrate. The wires are sheared off leaving a stub, the end of which is flattened by an anvil. Before flattening a sheet of material having a group of holes is arranged for alignment with the group of stubs is disposed over the stubs. The sheet of material supports the enlarged tip. The substrate with stubs form a probe which is moved into engagement with contact locations on a work piece such as a drip or packaging substrate.

Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component. The packaging and interconnection includes a contact structure made of conductive material and formed on a contact substrate, a contact trace formed on the contact substrate and connected to the contact structure, a contact pad formed on a bottom surface of the contact substrate and connected to the contact structure through a via hole and the contact trace, a contact target provided at an outer periphery of the contact structure to be electrically connected with the contact pad, and a conductive member for connecting the contact pad and the contact target.

Abstract: A test device includes an element having a surface for contacting a first plane, and a probe having a free end positioned in a second plane. The element of the test having the surface to contact the first plane includes features for contacting a ground plane. The length of the probe in the test device is greater than the length of the element having a surface for contacting the first plane. An electronic package includes a printed circuit board having a primary side, and a secondary side. A component, having a main body, is attached to the primary side of the printed circuit board. A pad is attached to the main body of the component. The printed circuit board has an opening therein positioned near the pad. The probe passes through the opening in the printed circuit board to contact the pad from the secondary side of the printed circuit board.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t?r?35t where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 ?m to 30 ?m and larger than that of the second curved surface.

Abstract: An electrical connecting method has the step of bringing a contact member connected to an electric circuit into contact with a terminal of an electronic part. A desired processing is performed by feeding current to the terminal via the contact member. The contact member is then separated from the terminal. When the contact member is brought into contact with the terminal, energy is applied to the contact member or the terminal in order to locally soften a portion of the terminal contacting the contact member. Thereafter, the desired processing is performed, in the state that the contacting portion of the terminal with the contact member is softened so as to reduce the contact resistance and so as to increase the subsequent separatability of the contact member from the terminal.

Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: The present invention provides an inspection system of ID chips that can supply a signal or power supply voltage to an ID chip without contact, and can increase throughput of an inspection process and an inspection method using the inspection system. The inspection system according to the present invention includes a plurality of inspection electrodes, a plurality of inspection antennas, a position control unit, a unit for applying voltage to each of the inspection antennas, and a unit for measuring potentials of the inspection electrodes. One feature of the inspection system is that a plurality of ID chips and the plurality of inspection electrodes are overlapped with a certain space therebetween, and the plurality of ID chips and the plurality of inspection antennas are overlapped with a certain space therebetween, and the plurality of ID chips are interposed between the plurality of inspection electrodes and the plurality of inspection antennas by the position control unit.

Abstract: A circuit and method for easily detecting skew of a transistor within a semiconductor device are provided. The circuit for detecting the skew of the transistor includes a linear voltage generating unit for outputting a linear voltage by using a first supply voltage, a first attenuation unit for reducing variation width of the linear voltage according to the performance of the transistor, a saturation voltage generating unit for outputting a saturation voltage by using a second supply voltage, and a comparison unit for comparing an output of the first attenuation unit and the saturation voltage.

Abstract: A system and method for replacing a malfunctioning logic device with a substitute logic device. The system provides a replacement assembly that contains a complex programmable logic device, a programming port and a pin configuration. The pin configuration selected matches the pin configuration of the malfunctioning logic device being replaced. The programming port on the replacement assembly is attached to a computer. Using software on the computer, the complex programmable logic device can be programmed with the same logic functions as were present within the malfunctioning logic device. Consequently, a single replacement assembly can be used to replace hundreds of different types of logic devices. This provided a cost efficient manner to produce replacements for obsolete logic devices that are no longer commercially available.

Abstract: Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.

Abstract: Some embodiments provide a reconfigurable IC that includes at least two sections, each with several configurable circuits. Each configurable circuit configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of different sections iterate through different numbers of configuration data sets.

Abstract: A programmable integrated circuit (IC) includes rows and columns of tiles, each tile including logic blocks, segments of interconnect lines, and programmable structures (e.g., routing multiplexers driving the interconnect lines, input multiplexers driving the logic blocks). The interconnect lines can be used, for example, to interconnect two programmable structures included in tiles located in different rows and different columns. Thus, these “diagonal” interconnect lines also have programmable access to other diagonal interconnect lines in the general interconnect structure. In some embodiments, the diagonal interconnect lines include “doubles”, which interconnect programmable structures in tiles diagonally adjacent to one another, and “pents”, which interconnect programmable structures in tiles separated by two intervening rows (or columns) and one intervening column (or row).

Abstract: An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Abstract: A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.

Abstract: Circuitry for distributing clock signals (e.g., reference clock signals) among a plurality of blocks of circuitry. Each block may include reference clock source circuitry and reference clock utilization circuitry. Each block also preferably includes an identical or substantially identical module of clock signal distribution circuitry that can (1) accept a signal from the source circuitry in that block, (2) apply any of several clock signals to the utilization circuitry in that block, and (3) connect to the similar module(s) of one or more adjacent blocks.

Abstract: A circuit includes a first native or depletion n-channel Metal Oxide Semiconductor (MOS) transistor and a second native or depletion n-channel MOS transistor. The first and second native or depletion n-channel MOS transistors are capable of receiving an input signal. The circuit also includes a standard p-channel MOS transistor and a standard n-channel MOS transistor. The standard MOS transistors are coupled to the native or depletion n-channel MOS transistors and are capable of providing an output signal. The output signal is based on the input signal. Gates of the native or depletion n-channel MOS transistors may be thicker than gates of the standard MOS transistors. The native or depletion n-channel MOS transistors may be capable of blocking excessive voltage from the standard MOS transistors. The standard MOS transistors may be capable of selectively blocking the input signal from the output signal.

Abstract: A semiconductor integrated circuit includes an input circuit for taking in signals and an output circuit for outputting signals. The input circuit is so set that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition. The output circuit is so set that the driving force during the second half of signal transition is lower than the driving force during the first half of transition. Such setting that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition reduces reflected waves during input signal transition. Such setting that the driving force during the second half of signal transition is lower than the driving force during the first half of transition suppresses production of reflected waves during the second half of signal transition.

Abstract: The present invention is directed to buffer/voltage mirror arrangement for sensitive node voltage connections.

Abstract: There is provided a power up circuit capable of outputting a power up signal delayed by a predetermined time. The power up circuit includes a voltage divider for dividing an external voltage, a delay controller for generating a control signal to control an output voltage of the voltage divider for a predetermined time by using the external voltage, and a signal generator for generating a power up signal delayed by a predetermined time by using the control signal.

Abstract: A method and a system for configurably generating enabling pulse clocks are disclosed herein. In various embodiments, enabling pulse clocks are configurably generated for a selected one of a first and a second signaling mode, employing a configurable enabling pulse clock generator configurable to so generate the enabling pulse clocks.

Abstract: A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

Abstract: A clock generation circuit and a clock generation method are provided, which are spread spectrum clock generation and accurate phase control of a reference clock signal and an output clock signal. An input divider unit 70 divides an input clock signal CLKR by 50 to output a divided input clock signal CLKS. A DLL circuit 80 operates to obtain delay control signals DCS1, DCS2. A modulation circuit 40 modulates, in response to the delay control signals DCS1, DCS2 and a modulation signal MOD output from a modulation control circuit 50, the divided input clock signal CLKS to output a modulation clock signal CLKN. A phase comparator 11 detects the phase difference between the modulation clock signal CLKN and a divided inner clock signal CLKM. A clock generation unit 20 generates an output clock signal CLKO having frequency corresponding to a phase difference signal from the phase comparator 11.

Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

Abstract: Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic prevents output of the output clock when any of a predetermined one or more of the samples correspond to a particular logic value (i.e., logic “1” or “0”). For example, sample reset logic may prevent an MCD circuit from providing the output clock when a sample taken from the earliest sampling point of the measure delay array corresponds to logic “1.” The MCD circuit may then provide the output clock in response to a subsequent triggering for which a sample taken from the earliest sampling point is logic “0.” Phase error of the output clock is thereby reduced. MCD circuits improve response to process, voltage and temperature (PVT) variations.

Abstract: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.

Abstract: A reset circuit includes a power supply supplying a power supply voltage, and a band-gap reference that generates a voltage reference signal. A resistor start-up circuit is responsive to the voltage reference signal, and further responsive to an increase in the power supply voltage. The resistor start-up circuit generates a first current when the power supply voltage increases to a first predetermined voltage, and further generates a second current when the power supply voltage increases to a second predetermined voltage. When the second current generated by the resistor start-up circuit is supplied to a resistor divider, the resistor diver delivers an output voltage that is a predetermined portion of the power supply voltage. A comparator compares the voltage reference signal with the resistor divider output voltage, and generates a reset signal when the resistor divider output voltage equals the voltage reference signal.

Abstract: A first-phase clock signal is generated in response to a first input clock signal. A second-phase clock signal is generated one clock cycle of the first input clock signal after generating the first-phase clock signal in response to the first input clock signal. A third-phase clock signal is generated one and one half clock cycles of the first input clock signal after generating the second-phase clock signal in response to a second input clock signal. A fourth-phase clock signal is generated one clock cycle of the first input clock signal after generating the third-phase clock signal in response to the second input clock signal.

Abstract: The clock delay circuit according to the present invention includes a delay circuit section, a selection circuit section, and jitter suppression elements. The delay circuit section provides a plurality of delay clock signals that are obtained by delaying a clock signal with a different delay amount. The selection circuit section selects and provides any one of a plurality of delay clock signals that are provided from the delay circuit section. The jitter suppression elements are connected in series between the delay circuit section and the selection circuit section. When jitters occur at the time of switching the delay clock signals at the selection circuit section, the jitter suppression elements serve to prevent the propagation of the jitters through the delay circuit section.

Abstract: Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals.

Abstract: A method of generating a clock signal using a digital frequency synthesizer includes providing a base clock to the digital frequency synthesizer, comparing a phase of an output clock from the digital frequency synthesizer with a phase of a reference signal, and issuing at least one frequency control command to the digital frequency synthesizer to align the phases.

Abstract: An input circuit (200) operating at a predetermined power supply voltage (VPW) can level shift a high voltage input signal (VINHV) from a higher voltage value to the lower power supply voltage (VPW) level. An input circuit (200) can include input transistors (206-0 and 206-1) having a source-follower configuration. A first input transistor (206-0) receives a high voltage input signal (VINHV) and a second input transistor (206-1) receives a reference voltage (VREF), which can both reach levels greater than power supply voltage (VPW). A compare circuit (204) can reduce duty cycle distortion to generate a lower voltage input signal (VINLV). Input circuit (200) can provide level shifting from LVTTL levels to low voltage CMOS levels without the need for multiple power supply voltages.

Abstract: A driver for a switching device has a plurality of driver circuits for driving the switching device and a control circuit. The control circuit selectively operates the driver circuits in response to a plurality of predetermined drive modes. Alternatively, a driver for a switching device has a driver circuit and a control circuit. The driver circuit is connected to a plurality of power sources. Each of the power sources has a different voltage. The control circuit selects one of the power sources for operating the driver circuit in response to a plurality of predetermined drive modes.

Abstract: A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.

Abstract: An integrated circuit apparatus according to one embodiment of the invention has an NMOS transistor and a source voltage controller which controls the source voltage of the NMOS transistor according to operation mode. The source voltage controller changes the source voltage according to temperature. Since this integrated circuit apparatus changes the source voltage of the MOSFET based on temperature, it is controlled to have desired leakage current regardless of temperature change.

Abstract: A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.

Abstract: A voltage supply circuit which suppresses generation of current spikes in the power source current in operation, reduce noise, simplify the circuit configuration, and decrease the cost. Clock signal CLK at a prescribed frequency is supplied to charge pump driver (10); current sources IS1, IS2, . . . IS6 work at timing set with clock signal CLK to output driving currents; and, corresponding to the driving currents, capacitors C1, C2 . . . are alternately charged or discharged; the charge stored in the capacitor of a preceding stage is sequentially sent to the later capacitor stage, and a boosted voltage higher than power source voltage Vcc is obtained at output terminal T2. In the charge pump type booster, since capacitors are driven with current sources, it is possible to reduce spike noise in the boosting operation, and influence on other analog circuits can be suppressed.

Abstract: A pumping circuit of a semiconductor device includes a power supply unit for supplying a power source voltage to a first node, a first transfer pump for transferring a first electric potential of the first node to a second node, a first pumping unit coupled to the first node for pumping the power source voltage applied to the first node, a first pump control unit for controlling a voltage applied to a gate of the first transfer pump, a second transfer pump for transferring a second electric potential of the second node to a high voltage output terminal, a second pumping unit coupled to the second node for selectively pumping the second electric potential of the second node, and a second pump control unit for controlling a voltage applied to a gate of the second transfer pump in response to the power source voltage level. If the power source voltage is higher than a predetermined voltage, the first pumping unit performs a pumping operation, and the second pumping unit performs only an on or off operation.