Abstract: Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.

Abstract: In integrated semiconductor memories whose stored information is represented by the magnitude of the ohmic resistance of layer stacks with a respective layer comprising a solid electrolyte, the problem arises that although the fact that the large threshold values (G1, G2) for the writing voltage and the erasure voltage differ from memory cell to memory cell means that the memory cells can be programmed individually, said memory cells cannot conventionally be erased individually, i.e., selectively in relation to the other memory cells. The reason for this is the large bandwidth of the threshold values (G1) for the erasure voltages, which ranges from a potential (Verasemin) to a potential (Verasemax). The invention proposes a semiconductor memory and a method for operating the latter, in which simultaneous biasing of all the bit lines and word lines and a specific choice of the electrical potentials allow a single memory cell to be erased selectively in relation to the other memory cells.

Abstract: A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least two resistance states. The threshold device is configured to switch from a high resistance state to a low resistance state upon application of a voltage and, when the voltage is removed, to re-assume the high resistance state. Additionally, the threshold device can be configured to switch in response to both negative and positive applied voltages across the first and second electrodes. Memory elements having a memory portion and threshold device between first and second electrodes and methods for forming the memory elements are also provided.

Abstract: An improved high-density digital storage device uses placement of mobile ions within a memory layer to record digital data. In an embodiment of the invention, the mobile ions comprise sodium ions or other alkali metal ions implanted in a silicon oxide memory layer. In a further embodiment of the invention, a scanning nanotip array is used to position the mobile ions via an electric field as well as to read the positions of the mobile ions. In a further embodiment of the invention, a grid-addressable array of transistors is used to provide scanning tips.

Abstract: Methods and circuits to reduce power consumption of DRAM local word-line drivers are disclosed. A first voltage converter provides a voltage VPP1, which is lower than the voltage VPP required to operate a word-line of a DRAM cell array. A voltage detector monitors the voltage level of the local word-line driver. Once the voltage level VPP1 is reached on the local word-linedriver switching means as e.g. tri-state drivers put the final VPP voltage on the word line. This VPP voltage is the output of a second voltage boost converter. Putting the voltage in two stages on the word-line reduces the overall power consumption. The voltage level VPP1 has to be carefully selected to find a compromised solution between current consumption and performance.

Abstract: Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell has a small number of transistors. The DRAM cell can be used to store configuration data on a programmable integrated circuits (IC). Pass gates are used on programmable ICs to drive signals across the chip. Data stored in DRAM cells is provided directly to the pass gates at the full supply voltage to prevent signal degradation.

Abstract: The present invention provides a magnetoresistive memory cell (30), comprising a magnetoresistive memory element (31), a first current line (32) and a second current line (33), the first and the second current line (32, 33) crossing each other at a cross-point region but not being in direct contact. According to the invention, a bridging element(34) connects the first and second current lines (32, 33) in the vicinity of the cross-point region. The bridging element (34) is magnetically couplable to the magnetoresistive memory element (31). An advantage of the MRAM architecture according to the present invention is that it allows lower power consumption than prior art devices and high selectivity during writing. The present invention also provides a method of writing a value in a matrix of magnetoresistive memory cells (30) according to the present invention, and a method of manufacturing such magnetoresistive memory cells (30).

Abstract: A write wiring for writing information in an MTJ device is covered with a magnetic layer. The magnetic layer has a structure in which the growing direction of columnar grains is 30° or less from the normal-line direction of sidewalls, a structure in which grains are deposited of sidewalls, a structure in which grains are deposited like a layer, or a structure in which grains are amorphously deposited.

Abstract: A method of performing a read operation from a first magnetic random access memory (MRAM) cell in a memory cell string that includes the first MRAM cell coupled to a second MRAM cell. The method includes providing a voltage to a first end of the first memory cell string that is closest to the first MRAM cell, providing a ground source to a second end of the first memory cell string that is opposite the first end, and determining whether a voltage change occurred at a node between the first and second MRAM cells in response to applying a write sense current to the first MRAM cell.

Abstract: A magnetic memory device and a sense amplifier circuit capable of obtaining a read signal output with a high S/N ratio and reducing power consumption and a circuit space, and a method of reading from a magnetic memory device are provided. In a sense amplifier, transistors (41A), (41B) which are differential amplifiers are commonly connected to one constant current circuit (50) through switches (46) ( . . . , 46n, 46n+1, . . . ). Corresponding bit decode lines (20) ( . . . , 20n, 20n+1, . . . ) and a read selection signal line (90) are connected to the switches (46) ( . . . , 46n, 46n+1, . . . ). A read/write signal is transferred from the read selection signal line (90), and the switches (46) operate according to a bit decode value and the read/write signal.

Abstract: A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gate input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.

Abstract: A semiconductor device includes a memory cell array and first and second replica bit lines. A plurality of memory cells are arranged in an array form on the memory cell array. The first replica bit line is configured by wirings having the same wiring width and wiring intervals as bit lines configuring the memory cell array and is operated to generate a read timing signal. The second replica bit line is configured by wirings having the same wiring width and wiring intervals as the bit lines configuring the memory cell array and is operated to generate a write timing signal.

Abstract: A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.

Abstract: To increase a cell current ratio of a program state to an erase state of two bit storage nonvolatile memory cells and reduce power consumption, a program state of MONOS-typed memory cells is a state where electrons are injected into two local regions near drain and source junction edges, an erase state is a state where the electrons injected into the two local regions are neutralized or holes are injected, and a read bias is a linear region. A cell current in the program state can be suppressed since charges injected into the source side suppress introduction of electron carriers required for formation of a conductive channel and charges injected into the drain side limit the formation of the conductive channel near the drain side. Accordingly, a read current can be reduced, a cell current ratio can be enhanced, and moreover, a margin of a reading operation can be increased.

Abstract: A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.

Abstract: Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Abstract: Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Abstract: Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity.

Abstract: An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a last sector whose flag is set to the first value and for each sector from a first address to a last address. When verification fails and the number of the same-cell-verifications is less than a predetermined number, the method applies an erase pulse and verifies the memory call at the same memory address again. When verification fails and the number of same-cell-verifications reaches the predetermined number, the remaining sectors whose flag is set to the first value are verified. When each memory cell of a sector to be erased passes verification, the erase flag of the sector is set to a second value. When the flag of each sector to be erased is set to the second value, the erase operation is terminated.

Abstract: In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the two spare memory cells and connecting these spare memory cells to a sense amplifier, the stored data of one bit is read. A spare memory cell section which is often arranged in an array peripheral portion becomes more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell increases.

Abstract: An apparatus for comparing inputted signals by removing an offset voltage during adjusting an output impedance of a semiconductor memory device, includes a voltage comparator for comparing a first input signal applied to its positive input node with a second input signal applied to its negative input node to output a first output signal to its positive output node and its second output signal to a negative output node; a switched capacitive unit for removing an offset voltage occurred in the positive input node, the negative input node, the positive output node and the negative output node of the voltage comparator; and a latch unit for latching the first output signal and the second output signal.

Abstract: A buffer circuit includes a plurality of registers, a write register selector, a read register selector, and an address proximity detector. The write register selector operates in synchronism with a write clock signal and outputs write enable signals in a predetermined sequence for write-enabling the plurality of registers, one at a time. The read register selector operates in synchronism with a read clock signal and outputs read enable signals in the predetermined sequence for read-enabling the plurality of registers to be read, one at a time. The address proximity detector detects an event in which a difference between a register write-enabled by one of the write enable signals and a different register read-enabled by one of the read enable signals at a time in the predetermined sequence is equal to a predetermined value and outputs a reset signal upon detecting such event.

Abstract: Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power down mode of operation.

Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated

Abstract: An output circuit including a first circuit configured to provide a first output signal, a second circuit configured to provide a second output signal, and a third circuit. The third circuit is configured to receive a third output signal that is based on the first output signal and the second output signal. The third circuit is configured to provide enable signals that turn on one of the first circuit and the second circuit and turn off the other of the first circuit and the second circuit based on the third output signal that is updated via the turned on one of the first circuit and the second circuit.

Abstract: A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method is provided comprising reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells; if the set of memory cells indicates that data can be reliably stored in the group of memory cells, storing data in the group of memory cells; and if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells, storing data in a group of memory cells in a redundant memory. In another preferred embodiment, a method for providing memory redundancy is provided.

Abstract: A downgraded memory module has downgraded DRAM chips soldered to its substrate. The downgraded DRAM chips have a defective memory cell in a logical quadrant of the memory. A physical MSB is a row address present on a non-downgraded DRAM of size S but not used on a downgraded DRAM size S/2. The physical MSB and a second address pin are non-multiplexed address pins that do not carry column addresses. The physical MSB and the second address pin logically divided the DRAM into quadrants. Two good quadrants without defects are selected, and jumpers on the memory module drive the physical MSB and the second address pin with signals that select only these two quadrants and disable access to quadrants containing defects. DRAM chips can be marked or sorted into bins for combinations of good quadrants. Downgraded memory modules have all DRAM chips from the same bin that share jumper settings.

Abstract: A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.

Abstract: A read circuit includes a precharge circuit, a discharge circuit, and a sense amplifier. The precharge circuit includes a first transistor which has a gate connected to the bit line, a second transistor which has a gate connected to the bit line, the second transistor having a current path one end of which is connected to one end of a current path in the first transistor, a third transistor which has a current path one end of which is connected to the other end of the current path in the first transistor, the other end of the current path in the third transistor being connected to a power supply, and a fourth transistor which has a gate connected to a junction between the current paths in the first and second transistors and which controls a charge level of the bit line.

Abstract: A method and a circuit are given, to implement and realize power saving Sense Electronics Endowed (SEE) memory using modified memory read cycles, named as Smart Memory Readout (SMR). In an SMR-mode read cycle, the memory is only active a small fraction of a clock cycle thus saving power. In this small fraction where the memory is enabled by SMR-mode read, the memory content is read to a shadow register and held until read by the microcontroller. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.

Abstract: A semiconductor memory device has first and second sense nodes which are provided corresponding to first and second bit lines, and a sense amplifier which is connected to the first and second sense nodes and senses data read out from a memory cell, wherein the sense amplifier includes an initial sense circuit which increases a potential difference between the first and second sense nodes in a first period after beginning sense operation, and a latch circuit which increases and holds the potential difference between the first and second sense nodes in a second period after the first period, wherein the initial sense circuit includes first and second transistors of first conductive type, third and fourth transistors of first conductive type, and fifth and sixth transistors of first conductive type, wherein the latch circuit includes seventh and eighth transistors of first conductive type, and ninth and tenth transistors of second conductive type.

Abstract: Reset dummy cells which change the load capacitance of a dummy read line DRD according to stored information are provided. Memory information are set to the reset dummy cells according to environmental factors, such as the temperature condition, voltage condition, etc. The timing of reading data from memory cells is controlled according to a change in voltage of the dummy read line DRD which is caused due to the discharge of the precharged dummy read line DRD.

Abstract: The preferred embodiments described below provide a method and memory device for improving the precision of a temperature-sensor circuit. In one preferred embodiment, first and second temperature-dependent reference voltages are generated and compared, and an operating condition of the memory array is controlled based on the result of the comparison. Instead of using a temperature-dependent reference voltage, a temperature-dependent reference current can be used. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract: A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory cells based on a timer period, which sets the timer period in accordance with a disturb amount in an active mode upon shift from the active mode to the standby mode.

Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Abstract: A semiconductor system and method for repairing failures of a packaged integrated circuit system are provided. The method includes detecting a failure associated with a packaged integrated circuit system after the packaged integrated circuit system is packaged, and repairing the failure by activating a redundancy circuit in the packaged integrated circuit system and deactivating a defective circuit associated with the failure. The process for repairing the failure includes applying a repair voltage to a polysilicon fuse to change a conductivity state of the polysilicon fuse from a first state to a second state. In another embodiment, the polysilicon fuse is replaced by a metal fuse, an anti-fuse, or a non-volatile random access memory.

Abstract: An antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse including a capacitor. The capacitor may include a gate over a gate oxide and an n-well under the gate oxide. The n-well may have two n+ regions used as contact points for the n-well. Upon programming, an electrically conductive path (e.g., a short) is permanently burned through the gate oxide. The antifuse cell occupies a relatively small area while providing a relatively tight read current distribution.

Abstract: Memory cells including an SRAM and an OTP memory unit that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. The concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

Abstract: An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and compare a sense current at the sense node relative to the reference current. The sensing circuit generates an output signal having a first logic level in response to the sense current being greater than the reference current and generates the output signal having a second logic level in response to the sense current being less than the reference current. The logic level of the output signal indicative of whether the antifuse is programmed or un-programmed.

Abstract: Methods and apparatuses for adjusting trim settings for internally generated voltages of an integrated circuit device are provided. In one embodiment the apparatus receives a target digital value for an internally generated voltage, and compares the target digital value to a current digital value for the internally generated voltage. If the comparison indicates that a difference between the target digital value and the current digital value is greater than an allowable threshold, a trim setting used to trim the internally generated voltage is adjusted based on the difference. The trim setting may be adjusted until the difference between the target digital value and the current digital value is less than or equal to the allowable threshold.

Abstract: Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.

Abstract: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

Abstract: In one embodiment, a memory circuit comprises one or more first memory cells, each of the one or more first memory cells configured to store at least one bit; one or more second memory cells, each of the one or more second memory cells configured to store at least one bit; and one or more read port circuits physically located between the first memory cells and the second memory cells. Each of the read port circuits is coupled to receive the at least one bit from each of the first memory cells and each of the second memory cells, and each of the read port circuits is configured to output the at least one bit from a selected memory cell of the first memory cells and the second memory cells responsive to a plurality of wordline signals coupled to the read port circuit.

Abstract: Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, adjustable current sink, and a voltage converter, all operably coupled to a current sum node. The first current source generates a first current having a temperature coefficient substantially equal to a temperature coefficient of at least one bit cell. The adjustable current source generates a second current that is substantially independent of a temperature change. The adjustable current sink sinks a third current that is substantially independent of a temperature change. The voltage converter is configured for generating a word-line signal having a word-line voltage proportional to a reference current, wherein the reference current comprises the first current, plus the second current, and minus the third current.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation filtering circuits is described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.

Abstract: The present invention is directed to overcoming analog transmission difficulties by digitizing transducer signals at or near the transducer of an acoustic pulse gun and then transmitting the transducer signals in a digital form so that the signals can be recovered with greater fidelity by a remote computer or recorder. System, apparatus and method aspects of the invention are provided. Advantages of the present invention include better transmission of the acoustic signal from the pulse gun assembly to the computer or recorder, reduced noise and electronic interference, and better data capture.

Abstract: A navigation processor is interfaced to an acoustic processor and to DGPS surface positioning equipment on a vessel. The navigation processor receives (a) position data from the DGPS surface positioning equipment, (b) data from a gyrocompass on an underwater system, (c) depth data of the underwater system, (d) velocity data of the underwater system based on data from a Doppler log unit on board the underwater system, and (e) range and bearing data of the underwater system from the acoustic processor, in order to calculate coordinates of the underwater system.

Abstract: An elastic assembly joined to at least one side face of one of the members to be assembled is engaged by elastic deformation with a ratchet fastening element fixedly connected to the other member to be assembled. These elastic assemblies are constituted by an elongated element. The assembly side face to which it is joined has an elongated receptacle for the reception thereof, this forming in the assembly side face a opening through which a side portion of its wall projects to lie within the trajectory of the ratchet fastening element so as to allow coupling of this ratchet fastening element, at least one of the faces of the latter being configured to hold the elongated element under elastic strain and being orientated to resolve the force exerted upon it into a component which tends to hold the assembled members in place.

Abstract: A timekeeping device enables easily knowing how much playing time has passed and can automatically keep track of time added to compensate for stoppage time. The timekeeping device 1 has a input unit 2, a display unit 3, an alarm unit 5, and a control unit 4. The control unit 4 has a timekeeping unit 41 including a first timer 41A and a second timer 41B, a input control unit 42, a timekeeping control unit 43, a display control unit 44, a alarm control unit 45, and memory 46. The alarm unit 5 outputs a first alarm when the second timer 41B is keeping time and the time kept by the first timer 41A reaches a preset time setting. When the second timer is not keeping time and the time kept by the first timer reaches the preset time, the alarm unit 5 outputs the second alarm.