Abstract: A delay lock loop having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop.

Abstract: Disclosed is waveform width adjusting circuit that comprises: a delay circuit having a prescribed delay time is provided in a signal propagation path and a delay adjusting circuit which applies an adjustment in such a manner that when a waveform width extending from either a positive-going transition or a negative-going transition of the signal waveform at an input terminal to the next negative-going transition or positive-going transition is greater than the delay time of the delay circuit, a signal having a reduced waveform width is output, and such that when the waveform width of the signal at the input terminal is less than or equal to the delay time, the waveform width is not reduced and the signal that is output has the waveform width of the original signal. Thus, the waveform width of a signal for which the waveform width is less than a limit is not reduced.

Abstract: The disclosed methodology and apparatus measure and correct the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds, thus providing a measured duty cycle.

Abstract: In some embodiments, a receiver latch circuit, includes a dynamic latch having at least one input terminal to receive an input data signal and at least one latch terminal. The dynamic latch is adapted to generate an amplified output data signal based at least in part on the input data signal. The dynamic latch includes at least one capacitor, coupled between the at least one input terminal and the at least one latch terminal, to reduce intersymbol interference in the input data signal.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: A clock distribution circuit for distributing an input clock according to an embodiment of the present invention includes: a first clock buffer receiving the clock; a first clock mask series-connected to the first clock buffer and controlling clock input to the first clock buffer; a second clock buffer series-connected to the first clock buffer and receiving a clock output from the first clock mask; and a second clock mask series-connected to the first clock buffer and the second clock buffer to control clock input to the second clock buffer.

Abstract: The invention provides a universal rate-based transducer for advancing diagnostic and predictive analyses of low frequency physical phenomena, such as associated with heat and mass transfer, solid and fluid mechanics, pressure and seismic analysis. In many applications, such as in the fire metrology, aerospace, security and defense sectors, rate information is crucial for reaching fast and reliable diagnosis and prediction. In one preferred embodiment, the invention comprises a universal voltage rate sensor interface that accurately recovers the instantaneous heating/cooling rate, dT/dt. Upon appropriate calibration, this sensor interface allows real-time extraction of rates associated with many physical quantities of interest (e.g., temperature, heat flux, concentration, strain, stress, pressure, intensity, etc.).

Abstract: A signal switching circuit includes an input terminal to which a signal is input, an output terminal from which a signal is output, a first electronic circuit and a second electronic circuit which are alternately connected between the input terminal and the output terminal, and switching elements for alternately connecting the first electronic circuit and the second electronic circuit between the input terminal and the output terminal through a selection. A signal alternative path for connecting between the input terminal and the output terminal at all times is provided. Even when the switching elements are in an open state, the signal that is input to the input terminal is output to the output terminal via the signal alternative path.

Abstract: A driver for a switching device has a plurality of driver circuits for driving the switching device and a control circuit. The control circuit selectively operates the driver circuits in response to a plurality of predetermined drive modes. Alternatively, a driver for a switching device has a driver circuit and a control circuit. The driver circuit is connected to a plurality of power sources. Each of the power sources has a different voltage. The control circuit selects one of the power sources for operating the driver circuit in response to a plurality of predetermined drive modes.

Abstract: A switching circuit uses multiple common-drain JFETs to serve as the low-side switches of the switching circuit, and each of the low-side JFET is coupled between a high-side switch and a power node. Since a JFET can endure high voltage at both drain side and source side, and has good heat dissipation capability at drain side, the drain of the low-side JFET is coupled to the power node to enhance the heat dissipation capability and accordingly, all the low-side JFETs are allowed to be packaged in a same package to reduce the PCB layout area.

Abstract: An exemplary power switching circuit (20) includes a control signal input terminal (210) which is configured for receiving a control signal; an output terminal (220) configured to be connected to a load circuit with capacitance; a direct current (DC) power supply (230); a first switching transistor (240) including a control electrode connected to the control signal input terminal, a first current conducting electrode, and a grounded second current conducting electrode; a second switching transistor (250) including a control electrode connected to the first current conducting electrode of the first switching transistor, a first current conducting electrode connected to the DC power supply, and a second current conducting electrode connected to the output terminal; and a third switching transistor (260) including a control electrode connected to the control signal input terminal, a first current conducting electrode connected to the output terminal, and a grounded second current conducting electrode.

Abstract: A method of temperature compensating an off chip driver (OCD) circuit having a plurality of transistor fingers comprising rendering active a normally inactive transistor finger in the circuit when a predetermined temperature condition occurs. A temperature compensated off chip driver (OCD) circuit utilizing such method.

Abstract: It is an object of the present invention to reliably avoid problems with a load connected when stopping the operation of a charge pump circuit. The charge pump circuit is provided with a first switching element (S1) connected to a power supply, a second switching element (S2) connected to a load (102)and a capacitor element (Cp) connected between the first switching element (S1) and the second switching element (S2), and moves charge in a direction opposite to the direction in which charge moves during normal operation by inverting the phase of any one of clock signals applied to the first switching element (S1), second switching element (S2) and capacitor element (Cp) during normal operation.

Abstract: A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.

Abstract: A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.

Abstract: An active load including a current source, a first resistive element, and a switch. The current source is configured to provide a bias current and the first resistive element is configured to receive the bias current and provide a bias voltage. The switch has an input and an output and is configured to receive a drive voltage at the input, receive the bias voltage between the input and the output, provide an output voltage at the output that is sufficiently different than the drive voltage to maintain headroom, and provide an inductive impedance that enhances circuit bandwidth.

Abstract: Transistor devices are provided configured to operate at frequencies above a typical first cutoff frequency. In one aspect, a method is provided for configuring a transistor device to operate above a first cutoff frequency. The method comprises selecting a desired operating frequency range and a desired output power for a transistor associated with the transistor device, analyzing the effects of phase velocity mismatch on the overall gain of a plurality of different sized transistors, and evaluating the primary and secondary gain regions of the plurality of different sized transistors. The method further comprises selecting a transistor sized to provide the desired output power at or close to the desired operating frequency range based on the analysis of the phase velocity mismatch and the evaluation of the primary and secondary gain regions.

Abstract: An audio power amplifier IC which is capable of suppressing degradation in sound quality resulting from the frequency of a reference clock, and an audio system provided with the audio power amplifier IC are provided. The audio power amplifier IC includes a clock generation circuit (10) generating an internal clock, a clock terminal (CLK) for outputting the internal clock or receiving an external clock, a clock selection circuit (11) selecting the internal clock or the external clock as a reference clock (BCLK), a first audio signal input terminal (IN1) for receiving a first audio signal (Lin), and a first digital power amplifier circuit (51) performing pulse modulation on the first audio signal (Lin) based on the reference clock (BCLK) to output a pulse synchronized with the reference clock (BCLK).

Abstract: An amplifier circuit of a BTL system is disclosed, which comprises a first operational amplifier which outputs an output signal having a same phase as an input signal input to a signal input terminal, a second operational amplifier which outputs an output signal having an opposite phase to the input signal, a voltage divider which generates a midpoint voltage of the input signal, a first resistor connected between an output terminal and a negative phase input terminal of the first operational amplifier, second and third resistors connected in series between the negative phase input terminals of the first and second operational amplifiers, a fourth resistor connected between an output terminal and the negative phase input terminal of the second operational amplifier, and an impedance converter connected between a midpoint voltage node of the voltage divider and a series-connection node of the second and third resistors.

Abstract: An adaptive bias method and circuits for amplifiers that provide a substantial current boost based at least partly upon a sensed input power of an amplifier circuit. Methods and circuits of the invention provide an additional bias current based upon the sensed input power. Circuits of the invention may be simple, area-efficient, low-power, stable and digitally-programmable. In addition, methods and circuits of the invention may be used with a number of amplifier circuit configurations, including amplifiers having either inductor and/or resistive degeneration.

Abstract: An operational amplifier includes: a differential amplifier circuit configured to receive an inverting input voltage (VIN?) and a non-inverting input voltage (VIN+); and an auxiliary circuit for improving a slew rate of an output voltage of the differential amplifier circuit, wherein when a voltage difference between the inverting input voltage (VIN?) and the non-inverting input voltage (VIN+) is less than a predetermined small voltage difference, an output terminal of the auxiliary circuit is disconnected from an output terminal of the differential amplifier circuit, and when the voltage difference exceeds the predetermined small voltage difference so that a voltage waveform is shifted to at least one direction, the voltage shift is accelerated by receiving/transferring a current from/to the output terminal of the differential amplifier circuit toward a shifting direction of an output voltage of the differential amplifier circuit.

Abstract: An operational amplifier including a first current mirror, a second current mirror, and a differential pair of transistors. The differential pair of transistors are configured to receive two inputs to direct current through the first current mirror and the second current mirror. The first current mirror provides a first current to a first high impedance node and the second current mirror provides a second current to a second high impedance node.

Abstract: In a constant amplitude wave-combining type amplifier for splitting a single input signal into two parts by a distributor 1, amplifying the split signal parts by first and second amplifiers 3a, 3b and then combining output signals amplified thereby, the amplifiers 3a, 3b comprise at least two amplifier elements accommodated in a single package. Also, the amplifier elements constituting the first and second amplifiers 3a, 3b are packaged in a close relationship to each other. Moreover, the amplifier elements constituting the first and second amplifiers 3a, 3b may be either field effect transistors or bipolar transistors.

Abstract: A first power source 11 for supplying a bias voltage to a gate electrode G of a field effect transistor 13, which amplifies high-frequency signals, and a second power source 15 for supplying a bias voltage to a drain electrode D of the field effect transistor 13 are provided. The protective resistance 12 is connected between the gate electrode G of the field effect transistor 13 and the first power source 11, and the bias voltage controller 14 is connected between the drain electrode D of the field effect transistor 13 and the second power source 11. Further, a voltage detector 16 is connected between both ends of the protective resistance 12 to detect a voltage drop generated between both ends of the protective resistance 12, when a rectified current flows to the gate electrode G from the drain electrode D of the field effect transistor 13.

Abstract: Provided herein is a power amplifier having a multiple stage power amplifier section and an output matching network section. The multiple stage power amplifier section can include multiple power amplifier stages with interstage matching circuits located therebetween. The output matching network can be configured to match the multiple stage power amplifier section at multiple different frequencies or frequency bands. The power amplifier device is capable of selective operation within one of multiple different frequencies or frequency bands.

Abstract: A multiple op amp IC with a single low noise op amp configuration comprises at least two op amp circuits fabricated on a common substrate. The IC can be configured such that the multiple op amps are connected in parallel to form a single op amp having output drive and input-referred noise characteristics which are superior to those of the constituent op amps. The IC can be fabricated with either first or second metallization patterns, with the first pattern providing multiple op amps with separate inputs and outputs, and the second pattern interconnecting the amplifiers to form a single op amp. The second pattern also preferably interconnects at least one set of corresponding high impedance nodes to prevent a difference voltage which might otherwise arise between the nodes due to component mismatches between the multiple op amps.

Abstract: An oscillation controlling apparatus configured to control an oscillation frequency of an oscillation circuit to be a target frequency comprises a frequency acquiring unit configured to acquire a plurality of oscillation frequencies of the oscillation circuit for a plurality of values of control signals by outputting the plurality of control signals increasing or decreasing the oscillation frequency of the oscillation circuit as values thereof are increased or decreased; a frequency characteristic calculating unit configured to calculate data indicating a relationship between the plurality of oscillation frequencies and the plurality of values of the control signals with a least-square method, based on the plurality of values of the control signals output by the frequency acquiring unit and the plurality of oscillation frequencies acquired by the frequency acquiring unit; and a control signal output unit configured to output the control signal setting the oscillation frequency to the target frequency, based o

Abstract: A frequency modulator is provided for generating an output signal with a frequency that is a function of a modulation signal, wherein the modulation signal can assume N?2 different discrete modulation values, and a predetermined frequency value of the output signal is associated with each modulation value, containing: a) a closed phase locked loop with a loop filter for providing a first control voltage, with a voltage controlled oscillator for generating the output signal, and with a switchable frequency divider for deriving a frequency-divided signal, and b) a modulation unit that is designed to provide, at a first output, values of a divisor that are a function of the modulation signal, and at a second output, a second control voltage that is a function of the modulation signal, c) wherein the oscillator has a first control input connected to the loop filter and has a second control input connected to the second output of the modulation unit, and is designed to generate the output signal as a function of t

Abstract: A surface mount crystal oscillator comprises: a crystal blank; an IC chip in which at least an oscillator circuit using the crystal blank is integrated; a mounting substrate having one main surface on which the crystal blank is disposed, and the other main surface used to mounting the crystal oscillator on a wiring board; and a cover bonded to the mounting substrate for hermetically sealing the crystal blank within a space between the mounting substrate and the cover. The mounting substrate has the one main surface extending outward from a region in which the cover is disposed such that a portion of the one main surface exposes. Test terminals which are electrically connected to the crystal blank are disposed on the exposed region of the one main surface.

Abstract: A system for comparing, measuring, or providing a reference signal based on a oscillator having variable loop gain is described. Only when the oscillator loop gain is at least the value of one does the oscillator produce an AC output signal. The oscillator's ability to oscillate is controlled by the one or more sensor/transducer input signal levels. In some cases, negative feedback of the AC output signal is also used to control the loop gain of the oscillator circuit keeping the loop gain at or close to the value of one. The system's output signal indicates whether the oscillator is oscillating or not, or the AC signal level required to just maintain oscillation.

Abstract: To modulate the frequency of a signal to be transmitted, the biasing voltage applied to a terminal of a transistor is dynamically modulated. To achieve this, the pulse width or a pulse amplitude of a control signal is modulated. Alternatively, a multi-bit control signal may be used to perform the modulation. The frequency of the transmitted signal is optionally modulated by varying the temperature of a oscillator. To vary this temperature, the current flowing through one or more resistive elements positioned in proximity of the oscillator is varied in response to the pulse width or amplitude of a second control signal. The temperature may also be changed by varying a multi-bit control signal. As the level of this current flow varies, the amount of heat emitted by the resistors vary, thereby changing the temperature of the oscillator which has a non-zero temperature coefficient.

Abstract: The various designs of capacitive or inductive coupling/decoupling fitted on cables in a medium voltage network are known, the inductive coupling circuits constantly inducing current in the sheath of the electric cable. The invention aims at obtaining ranges of capacitive coupling/decoupling for an inductive coupling circuit. Therefore, an inductive coupling unit comprising a ring enclosing the sheathed electric cable and a coil, coupled to said ring by induction and connected to a transmission and reception device, is designed such that, upon transmission the current of the message signal is directly induced in the conductor and, upon receptions only the conductor current is evaluated. In a first embodiment, a by-pass, located downstream of the inductive coupling unit and upstream of the defined surface, is connected to the sheath and to ground or to the compensation potential.

Abstract: In a filter circuit (1), a common mode choke (2) and a normal mode choke (3) have extremely high and low impedances, respectively, for common mode signals received through two input terminals (1a and 1b). The chokes have the opposite impedance characteristics for differential signals. In particular, the difference in impedance is large. Furthermore, the normal mode choke (3) is installed as a previous stage of the common mode choke (2). Accordingly, common mode noises which enter the two input terminals (1a and 1b) penetrate the normal mode choke (3), but neither penetrate the common mode choke (2) nor are reflected from the common mode choke (2). In particular, common mode currents flow through the normal mode choke (3) but do not flow through the common mode choke (2).

Abstract: A directional bridge circuit is formed on a single substrate. The substrate has an access hole and is housed in a conductive package. A pedestal extends from the conductive package and enables a physical connection between the directional bridge circuit and the pedestal through the access hole.

Abstract: A manifold combiner for a plurality of radio frequency electromagnetic signals includes a first RF bandpass filter element with input and output ports and a first junction element, wherein the first junction element includes a first port connected to the first filter output port, a second port connected to a shorted stub element, and a third port functioning as an output. The signal path toward the stub appears as an open to the first filter. The combiner further includes at least one additional filter element and junction element, with the second port of the additional junction element fed from the output of the previous junction element. Interconnecting sections couple the respective elements. Dimensions of interconnecting sections are selected such that each filter element output sees a single path out of the manifold, through the output of the last junction element, with all other possible paths appearing as open circuits.

Abstract: A filter includes piezoelectric thin-film resonators having a substrate, a lower electrode supported by the substrate, a piezoelectric film provided on the lower electrode, and an upper electrode provided on the piezoelectric film. At least one of the piezoelectric thin-film resonators has a portion in which the upper electrode overlaps the lower electrode across the piezoelectric film. The above portion has a shape different from shapes of corresponding portions of other piezoelectric thin-film resonators, so that a spurious component in the above at least one of the piezoelectric thin-film resonators occur at a frequency different from frequencies of spurious components that occur in the other piezoelectric thin-film resonators.

Abstract: A CATV filter assembled inside a housing has the housing marked by a laser system with indicia relating to specific characteristics of the filter. The housing is thus not mechanically deformed during the step of marking, resulting in unchanged RF characteristics of the filter as a result of the marking.

Abstract: The present invention realizes a noise suppression circuit capable of suppressing noise in a wide frequency range even if impedance fluctuates on the input side or the output side. A noise suppression circuit has first and second inductors (L1, L2) inserted in series in a first conductive line (3), and a series circuit (15) configured to have a third inductor (L3) and a first capacitor (C1) connected in series. The third inductor (L3) side is connected between the first and second inductors (L1, L2). The noise suppression circuit further includes a second capacitor (C2) whose one end is connected to the first conductive line (3) on the first inductor (L1) side and whose other end is connected between the third inductor and the first capacitor in the series circuit (15).

Abstract: A connecting system can couple two waveguides to one another, wherein each of the waveguides comprises a flange or a protruding rim. When the waveguides are connected together, the flanges can face one another in an adjoining arrangement. The connecting system can comprise two members, each having a groove, recess, or slot that receives a circumferential area of the adjoining flanges. The two members can be disposed on opposite lateral sides of the waveguides with each groove embracing a peripheral area of the adjoining flanges. A fastener or another apparatus can bring the two members towards one another, thereby causing the flanges to move deeper into the grooves. That is, the two members can clamp around opposing sides of the flanges. In response to the flanges moving deeper into the grooves, the sidewalls of the grooves can compress the flanges together to attach the waveguides to one another.

Abstract: A PIN diode network includes a parallel inductor. In the off state of the PIN diode, the inductor forms a resonant tank circuit in parallel with the PIN diode. The inductor is selected based on the stray capacitance of the PIN diode so that the self resonant frequency (SRF) of the tank circuit is at or near the desired operating frequency. At the operating frequency, the impedance of the tank circuit is essentially infinite. At the operating frequency, isolation is improved for the PIN diode network as compared to a PIN diode alone. The PIN diode network allows a lower specification PIN diode to operate with higher isolation. The PIN diode network allows a lower specification PIN diode to operate at a higher frequency than would otherwise be possible due to intrinsic stray capacitance of the PIN diode.

Abstract: A manual opening device is for an electrical switching apparatus, such as a synchronous circuit breaker, including a housing having an opening, a plurality of pole mechanisms each comprising separable contacts, and at least one operating mechanism including a number of actuators adapted to open and close the separable contacts. The operating mechanism is supported by the housing and includes a corresponding pole shaft. The manual opening device comprises an operating handle, a cam assembly, and a drive assembly. A first end of the operating handle protrudes through the opening of the housing and the second end is coupled to the cam assembly. The drive assembly couples the cam assembly to the corresponding pole shaft of the operating mechanism and cooperates with the corresponding pole shaft and actuators to simultaneously open the separable contacts when the operating handle is moved from a first position to a second position.

Abstract: A magnetic element includes a drum core provided with a flange portion having a flange surface at each end portion of a winding shaft, a coil wound on the winding shaft, a terminal to connect each end portion of the coil, and a shield core provided with an engagement portion having such a shape that partially fits in along an outer circumference of the flange portion.

Abstract: A flux-channeled high current inductor includes an inductor body having a first end and an opposite second end and a conductor extending through the inductor body. The conductor includes a plurality of separate channels through a cross-sectional area of the inductor body thereby directing magnetic flux inducted by a current flowing through the conductor into two or more cross-sectional areas and reducing flux density of a given single area. The inductor body may be formed of a first ferromagnetic plate and a second ferromagnetic plate. The inductor may be formed from a single component magnetic core and have one or more slits to define inductance. The inductor may be formed of a magnetic powder. A method is provided for manufacturing flux-channeled high current inductors.

Abstract: A fusible disconnect device having auxiliary connections to line-side and load-side terminals and color coding features to indicate an amperage rating of a fuse.

Abstract: The invention describes a bimetallic thermal switch comprising an electrically insulating carrier (2), a contact spring (4) made from a bimetallic material, which is carried by the electrically insulating carrier (2) and has two ends, one being fixed in position, and which is so formed, at least over a certain portion (4a), that it will abruptly change its curvature when its switching temperature is exceeded; two electric supply lines (8, 9) held on the insulating carrier (2) and leading to two contact pieces (6, 7) disposed separately one from the other and from the contact spring (4); and a contact bridge (5) mounted on the contact spring (4) opposite the two contact pieces (6, 7).

Abstract: A temperature probe assembly is provided. The temperature probe assembly may comprise a housing formed of a first thermally conductive material and having an inner diameter defined by an inner bore, an insert formed of a second thermally conductive material disposed in the inner bore and having an outer diameter that is substantially equal to the inner diameter of the housing at a first temperature and a temperature sensor mounted within the insert. The second thermally conductive material has a thermal coefficient of expansion that is greater than the first thermally conductive material, such that the insert is insertable into the inner bore at the first temperature and is tightly locked in the inner bore at a second temperature that is greater than the first temperature.

Abstract: A voltage divider for high precision voltage measurement has one or more pair of potentiometers. The wipers of each pair of potentiometers are ganged so that the sum of their resistances relative to a first end of the respective potentiometer is a constant. An output potentiometer or a pair of resistors provide an output for measuring the output voltage. The resolution of the voltage divider is the product of the resolution of each potentiometer pair and the output potentiometer.

Abstract: Methods for adjusting a picture of an object captured by a camera in a mobile radio communication terminal include defining a first camera angle relative to the object and capturing an image of the object by means of the camera from a second camera angle relative to the object. The second camera angle is offset from the first camera angle. The methods further include storing image data relating to the captured image, and generating an angularly adjusted image of the object in response to the image data and an angular relation between the first camera angle and the second camera angle. Corresponding mobile radio communication terminals are also disclosed. The terminals include an image processing system configured to process an image of an object captured by a camera from a second camera angle by generating an angularly adjusted image of the object in response to image data for the image, and in response to an angular relation between the second camera angle and a first camera angle.

Abstract: A system has an electronic key that transmits a coded signal and at least one tool or other device that can receive that signal. The coded signal is compared to a coded signal stored in the tool or other device. If the coded signal authenticates the stored signal, the tool is enabled or disabled for a specified amount of time. An on/off switch then enables the user of the tool to turn the tool or other device on and off during the specified amount of time. After the specified amount of time, the tool is disabled so that the tool or other device can no longer be used. Disabling the tool may be delayed if the tool or other device is in use. The tool or other device may also contain a unique identification code that can be read by an interrogating device to identify the tool or other device.

Abstract: Methods, systems, and apparatuses for identifying items carried by a mobile structure are described. At a first location of the mobile structure, a first radio frequency identification (RFID) read signal is directed to a load carried by the mobile structure to identify an initial set of RFID tags. At a subsequent location of the mobile structure, a subsequent read signal is directed to the load carried by the mobile structure to identify a subsequent set of RFID tags. The initial set of RFID tags and the subsequent set of RFID tags are compared to determine a set of RFID tags associated with the load.