Abstract: Method an apparatus for converting the output of a thermoelectric generator to voltages compatible with implantable medical devices is provided. One apparatus includes an implantable thermoelectric generator. The apparatus includes an input terminal for receiving an input voltage generated by a thermoelectric energy converter and a charging inductor connected in series with the input terminal. The apparatus also includes a switching Field Effect Transistor (FET) connected to the inductor, and a capacitor connected to the FET and the input terminal via a diode. The FET is switched with a frequency and duty cycle such that a voltage level at an output terminal is compatible with an implantable medical device. According to various embodiments, the FET is switched using a closed loop feedback system that controls the frequency and duty cycle based on an observed voltage level at the output terminal. Other aspects and embodiments are provided herein.

Abstract: A feedback circuit (3) generates an error amplification signal VEAO for stabilizing an output voltage Vo at the reference voltage. The reference voltage is set beforehand in the feedback circuit (3). The peak value of drain current ID passing through a switching element (1) is controlled by the error amplification signal VEAO and the output voltage Vo is stabilized. Meanwhile, when a load (132) increases, a reference voltage variable circuit (13) increases the internal reference voltage of the feedback circuit (3) based on the error amplification signal VEAO, so that fluctuations in output voltage due to load fluctuations are reduced.

Abstract: A design and method for controlling the initial inductor current in a DC/DC switching regulator. The Ton or Toff time, depending upon implementation, is gradually increased such that power applied to a load is initially constrained until the system reaches a stable state, at which time normal power is connected to the load. In an embodiment, the on or off time is limited by a circuit which controls a pair of complementary transistors. The states of the transistors are controlled by the use of a startup-phase voltage and a reference voltage, which are then compared in an error amplifier. The result of the comparison is compared to a sawtooth signal in a comparator, the output of which controls the state of complementary transistors.

Abstract: A DC to DC converter includes a comparator, a driver, and a pair of switches. The comparator compares the output voltage with a reference voltage signal and generates a PWM signal. The driver drives the switches so as to force the output voltage to follow the reference signal. In a multiphase architecture, two or more such converter circuits are incorporated to minimize the output voltage ripple and further reduce the recovery time. In a two-phase architecture, two reference signals are phase-shifted by 180 degrees. In an N-phase architecture, the reference signals are phase-shifted by 360/N degrees.

Abstract: A powering arrangement for a device (30, 22) that normally operates on three phase power has the capability of operating based upon single phase power. One disclosed technique includes estimating a direct component based upon a measured voltage across the leads coupled with the single phase power supply. The quadrature component is estimated based upon a numerical derivative of the direct component. The direct component is also provided to a current regulator in a feed forward control manner, which minimizes error.

Abstract: The storage apparatus includes a plurality of storage devices for storing information, a control unit controlling the storage device, a switching unit switching a connection between the storage device and the control unit, and a network different from the connection by the switching unit and connecting the storage device and the control unit. Reading of information from the storage device and writing of information into the storage device is performed by the control unit through the switching unit, and when a fault occurs in the storage device, a fault recovery command is sent from the control unit through the network to the corresponding storage device or the switching unit.

Abstract: A device includes an array of memory cells, which are arranged vertically to a main substrate surface. The array is provided with lower bitlines, wordlines and upper bitlines. The lower and upper bitlines are contact-connected to lower source/drain regions and corresponding upper source/drain regions, respectively, in such a manner that a unique addressing of individual memory cells is possible.

Abstract: Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array. In one embodiment, a switching element is used to electrically isolate the elements in the array from the external load.

Abstract: The invention regards an IC-circuit construction where the circuit is partitioned into power consuming sub-circuits (1,6) and where ground voltage level (VHH) in the power supply of a first sub-circuit (1) is used as the supply voltage level in a second sub-circuit (6). According to the invention a voltage control circuit (4) comprises a first buffer capacitor (10) coupled in parallel over the supply voltage level (VBB) and ground voltage level (VHH) of the first sub-circuit (1) and a second buffer capacitor (11) coupled in parallel over the supply voltage level (VHH) and the ground voltage level (GND) of the second sub-circuit (6), whereby means for maintaining a uniform voltage drop over the first (10) and the second (11) buffer capacitor comprises at least one bucket capacitor (20,21,22) which is alternately coupled in parallel over the first (10) and the second (11) buffer capacitor through a switching system controlled by a toggling signal.

Abstract: A semiconductor memory device has first and second AF programming circuits having low and high AF programming threshold power supply voltages, respectively. In a process where a large majority of programming is carried out in the semiconductor memory device alone, the second AF programming circuit is used. In a module process where semiconductor devices having low withstand voltages are mounted in a module, the first AF programming circuit is used.

Abstract: A semiconductor memory includes a memory cell as a resistance change element and a switching element which are connected in series and a read word line connected to a control terminal of the switching element. In addition, the semiconductor memory includes a circuit which executes an auto-close operation for causing which makes a read word line RWL to be subjected to non-activation automatically after a fixed period from start of a read operation.

Abstract: A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memory cells for reading/modifying their status. At least one memory cell in said plurality is used as detector memory cell, and control means operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.

Abstract: A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled to the pull-up MOS device and the pull-down MOS device. The first drive current and the third drive current preferably have an ? ratio of between about 0.5 and about 1. The second drive current and the third drive current preferably have a ? ratio of between about 1.45 and 5.

Abstract: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.

Abstract: A method for accessing data on a magnetic memory is provided, wherein the data is accessed in a toggle mode. A first current line and a second current line are used for providing operation currents. The data accessing method includes a data changing operation for changing a data stored in a magnetic memory cell. During a first stage, a current in a first direction is supplied to the first current line, and a current in the first direction is simultaneously supplied to the second current line. During a stage before stopping supplying magnetic field, a current in the first direction is supplied to the first current line, and a current in the first direction is simultaneously supplied to the second current line to offset at least a portion of the biased magnetic field.

Abstract: An array of non-volatiel memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.

Abstract: Solid-state memories are disclosed that are comprised of cross-point memory arrays. The cross-point memory arrays include a first plurality of electrically conductive lines and a second plurality of electrically conductive lines that cross over the first plurality of electrically conductive lines. The memory arrays also include a plurality of memory cells located between the first and second conductive lines. The memory cells are formed from a metallic material, such as FeRh, having the characteristic of a first order phase transition due to a change in temperature. The first order phase transition causes a corresponding change in resistivity of the metallic material.

Abstract: An apparatus and methods for a non-volatile magnetic random access memory (MRAM) device that includes a word line, a bit line, and a magnetic thin film memory element located at an intersection of the word and bit lines. The magnetic thin film memory element includes an alloy of a rare earth element and a transition metal element. The word line is operable to heat the magnetic thin film memory element when a heating current is applied. Heating of the magnetic thin film memory element to a predetermined temperature reduces its coercivity, which allows switching of the magnetic state upon application of a magnetic field. The magnetic state of the thin film element can be determined in accordance with principles of the Hall effect.

Abstract: One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.

Abstract: A program element has a magnetic layer electrically connected between first and second nodes. At least a portion of the magnetic layer forms a link portion designed to be blown with external-laser irradiation. The magnetic layer is provided in the same layer as and with the same structure as a tunneling magneto-resistance element in an MTJ memory cell. An electrical contact between the magnetic layer and respective one of the first and second nodes has the same structure as the electrical contact between the tunneling magneto-resistance element and an interconnection provided in the same metal interconnection layer as respective one of the first and second nodes in the MTJ memory cell.

Abstract: A non-volatile memory device includes a plurality of word lines, a plurality of sense lines, and a plurality of non-volatile memory cells. Each memory cell includes a floating gate transistor having a control gate, a floating gate separated dielectrically from the control gate, a drain connection and a source connection. The control gate is connected to one of the word lines and the source connection is connected to one of the sense lines, the drain connection being electrically isolated from the other memory cells. A method for reading the memory device and a method for operating the memory device are also provided.

Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.

Abstract: In a method of programming a nonvolatile memory device comprising a plurality of n-valued nonvolatile memory cells arranged in a matrix, wherein n is a natural number greater than or equal to two (2), the method comprises; programming i-valued data to three or more memory cells contiguously arranged along a first direction of the matrix before programming (i+1)-valued data to any of the three or more memory cells, wherein i is less than n, and wherein the three or more memory cells are programmed during three or more respectively distinct program periods, and after programming the i-valued data to the three or more memory cells, programming (i+1)-valued data to a particular memory cell among the three or more memory cells.

Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.

Abstract: In a SIM card having a flash memory chip, a memory controller chip, and contact/contactless card interfaces, the memory controller chip has a function of executing user authentication of a host equipment, executes processing of data transmitted through the contactless IC card interface (executing reading or writing of data to the flash memory chip) using power supplied from the host equipment to the contact IC card interface, and executes initialization of the flash memory chip between activation of the host equipment and completion of user authentication instructed by the host equipment.

Abstract: A method for repairing cells of a flash memory array includes using a fuse memory array circuit. The fuse memory cells are initially programmed. The locations of defective memory cells of the main array are determined. These locations are stored in the fuse memory cells by erasing predetermined locations in the fuse memory cell array so that the locations are programmed.

Abstract: Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.

Abstract: 2 or more sets of initial setup data specifying different operation conditions are stored in a memory cell array comprising electrically-rewritable non-volatile memory cells arranged therein. A control circuit reads a set of initial setup data out of the 2 or more sets of initial setup data via an sense amplifier circuit based on the area information. The initial setup data is transferred to an initial setup data latch and stored therein.

Abstract: A memory device, a method for sensing a current output and a sensing circuit are disclosed. In one embodiment, a first voltage is supplied at least to a drain and a source terminal of a neighboring memory cell before sensing, and the first voltage is applied to a source terminal of a selected memory cell, while sensing the current though the selected memory cell.

Abstract: The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles.

Abstract: Nonvolatile memory cells and array are provided. The memory cell comprises a body, a source, a drain, and a charge storage region. The body comprises an n-type conductivity and is formed in a well of the n-type conductivity. The source and the drain have p-type conductivity and are formed in the well with a channel of the body defined therebetween. The charge storage region is disposed over and insulated from the channel by a channel insulator. Each cell further comprises a bias setting having a source voltage applied to the source, a well voltage applied to the well, and a drain voltage applied to the drain. A bias configuration for an erase operation of the memory cell is further provided, wherein the source voltage is sufficiently more negative with respect to the well voltage and is sufficiently more positive with respect to the drain voltage to inject hot holes onto the charge storage region. The cells can be arranged in row and column to form memory arrays and memory device.

Abstract: A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

Abstract: Disclosed are a recording device and an HDD built-in recording device each of which can curtail a use area of nonvolatile memory to be used even with the nonvolatile memory having a limit in the number of times of rewriting. In this HDD built-in recording device, a microcomputer 14 judges whether a program recorded in an HDD to be written into EEPROM 15 using a rewriting program and a history table recorded in the EEPROM 15. In doing this, the rewriting program increases the number of accesses in response to the increase in the number of times of rewriting into the EEPROM 15, and thereby restricts the number of programs to be written into the EEPROM 15 from the HDD 17.

Abstract: An Internet based system and method for mediation of financial loans, purchasing goods and providing services between consumers and providers which employs a mediator therebetween. The system employs a public communication network such as the Internet, to interconnect at least one mediator between at least one creditor, and a client. Over a public networking system, the system provides verification of client identity through the mediator, communication of loan terms from the creditor through the mediator to a client, and accounting of each party's ongoing financial interests via software resident on a bank or other financial institution's computer. The system thereby provides clients seeking financial surfaces or goods access to providers thereof over a public network through a mediator and a subsequent accounting for all three parties' mutual interests employing software adapted to the task running on a mutually accessible computer or server.

Abstract: The present invention relates to data transfer to an external storage device disposed on or connected to an electronic device and can accelerate the data transfer. The present invention relates to an electronic device (portable terminal device) connected or disposed with an external storage device, includes a transmission channel connected to an external device (personal computer) that is a data source to transmit data, and simplifies a data transmission path intervening between the transmission path and the external storage device to accelerate the data transfer and accelerate the writing of data into the external storage device.

Abstract: A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a buffer circuit and an early write termination circuit. The buffer circuit is configured to sample input data responsive to a data strobe signal applied to the SDRAM during a write operation and direct the input data to one or more memory cells of the SDRAM for storing the input data. The early write termination circuit is configured to terminate the write operation at less than a programmed burst length by disabling access to one or more of the memory cells after storage of the sampled input data responsive to detecting deactivation of the data strobe signal.

Abstract: A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.

Abstract: An integrated semiconductor memory with a test function comprises a bit line pair having a first end and a second end. A voltage generation circuit having a first connection and a second connection is coupled to the first end of the bit line pair. A plurality of memory cells are connected to a bit line of the bit line pair between the first end and second end of the bit line pair. A controllable switch is connected between the second end of the bit line pair.

Abstract: Circuit arrangements and methods are provided for regulating and maintaining voltage on bitlines of a semiconductor memory device. According to one embodiment, first and second regulation devices are connected to a charging circuit. At the beginning of a charging period, voltage on the bitlines is regulated with the second regulation device as the bitlines are initially charged to a voltage. After initially charging the bitlines to the voltage, voltage on the bitlines is regulated with the first regulation device that also limits current to the bitlines when there is a leakage anomaly associated with the bitlines. According to another embodiment, a charging circuit that is connected to sense nodes of a sense amplifier while the sense nodes are connected to the bitlines is activated so that the charging circuit assists in charging the bitlines at the beginning of a charging period.

Abstract: The present invention provides a semiconductor device and a control method thereof, the semiconductor device including: a bit line connected to a memory cell; a voltage control circuit controlling a voltage supplied from a voltage source to the bit line; a differential amplifier circuit providing the control voltage to the voltage control circuit in response to a voltage at a node coupled to the bit line and a reference voltage; and a current source providing a current to the differential amplifier circuit. The current source provides more current to the differential amplifier circuit in the first period including a period for precharging than in the second period after precharging.

Abstract: In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides.

Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

Abstract: A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.

Abstract: The present invention relates to a semiconductor memory device to execute a refresh operation in such a manner that an entry and an exit of a self refresh mode is carried out. The present invention uses only external clock signals without a clock enable signal or an auto refresh command and therefore it is possible to implement a simple circuit for the self refresh. A semiconductor memory device includes a self refresh enable signal generator for outputting an activated self refresh enable signal when positive and negative external clock signals are in phase and a de-activated self refresh enable signal when the positive and negative external clock signals are out of phase and a self refresh block for performing a self refresh operation in response to the activated self refresh enable signal.

Abstract: A refresh period generating circuit which generates a refresh period in refreshing a DRAM cell, comprising: an oscillation circuit which oscillates at a frequency with temperature dependence on ambient temperature; a dividing circuit which divides an oscillation output of the oscillation circuit; a temperature detector which detects the ambient temperature; and a selector which switches and selects among division outputs with respective frequencies from the dividing circuit based on an output of the temperature detector, and outputs a signal as a reference of the refresh period. The temperature dependence in the oscillation circuit includes a positive temperature coefficient in a predetermined temperature range, and does not include a positive temperature coefficient out of the predetermined temperature range. The selector switches the division outputs out of the predetermined temperature range.

Abstract: A plurality of memory cells are arranged in a memory cell array. The plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines. A plurality of source lines are disposed along the plurality of bit lines. The plurality of source lines are connected respectively to sources of the plurality of memory cells at a time of data read.

Abstract: A memory capable of suppressing increase of the chip area thereof while increasing a read voltage is obtained. This memory comprises a memory cell array including a plurality of subarrays, a sub bit line arranged on each subarray and provided to be connectable to a main bit line, a storage portion connected between the word line and the sub bit line and a first transistor having a gate connected to the sub bit line and a first source/drain region connected to the main bit line for controlling the potential of the main bit line on the basis of the potential of the sub bit line in a read operation.

Abstract: A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.

Abstract: Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line from the latch output, and the enable line in the added port is the logical NOR of all of the original enable lines. By adding this extra latch port in the higher-level model, it becomes possible to introduce assertion logic to ensure that one and only one latch port for a given latch is ever active during the same simulation cycle. The model can then be tested earlier in the design methodology prior to the availability of the post-synthesis netlist. The model can also be used in both simulation and formal or semi-formal verification.

Abstract: A semiconductor device that prevents a build-up of electrostatic charge in a dummy pad is provided. The semiconductor device may contain an internal circuit formed on a semiconductor substrate and the dummy pad which is not electrically connected to the internal circuit. The semiconductor device may further include a seal ring that surrounds the internal circuit and the dummy pad, where the seal ring is electrically connected to the semiconductor substrate and includes a pattern in a first metal layer, a contact between the pattern in the first metal layer and the semiconductor substrate, patterns in upper metal layers stacked above the pattern in the first metal layer, and multiple electrical contacts between the patterns in the first metal layer and the upper metal layers, in which the dummy pad is electrically connected to the seal ring.