Abstract: A thin film transistor (TFT) photosensitive to illumination with light, which may enhance the transistor's characteristics and the controlling parameters of the transistor state. The transistor comprises an insulating substrate; a source electrode; a drain electrode; a semiconductor layer of a first semiconductor material, which forms a channel of the transistor; a gate electrode; and an insulating layer between the gate electrode and the semiconductor layer. A second semiconductor material is disposed between and in electrical connection with the semiconductor layer and at least one of the source electrode and the drain electrode. The second semiconductor material is photoconductive.

Abstract: A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.

Abstract: A semiconductor evaluation device evaluates an amount of mask misalignment in an optical exposure step during the fabrication of a semiconductor device. The semiconductor evaluation device has a first semiconductor region selectively formed in a semiconductor substrate, a first gate electrode having a cross-shaped plan configuration, formed on the first semiconductor region with a first gate insulating film interposed therebetween, and an intersecting portion at which a first gate portion disposed in an X-axis direction and a second gate portion disposed in a Y-axis direction intersect each other, and a first impurity diffusion layer formed in the area of the first semiconductor region which is other than the portion thereof underlying the first gate electrode and partitioned by the first gate electrode into four diffusion regions.

Abstract: A readout pixel of an input display is provided. The readout pixel includes the fundamental elements as the normal pixel, and further includes a photo sensing element with a second switching element and a third switching element for generating a photo signal. The second switching element includes a second gate electrode connecting to a gate line, a second drain electrode, and a second source electrode connecting to a readout line. The third switching element includes a third gate electrode and a third drain electrode both connecting to a reference voltage, and a third source electrode connecting to the second drain electrode.

Abstract: A multi-channel thin film transistor structure including a first conducting layer, an insulating layer, a semiconductor layer and a second conducting layer is provided. The first conducting layer formed on a substrate includes a gate electrode. The insulating layer covers the first conducting layer. The semiconductor layer formed on the insulating layer includes a plurality of semiconductor islands located above the gate electrode. The second conducting layer formed on the insulating layer and on the semiconductor layer includes a source electrode and a drain electrode. Each one of the semiconductor islands is coupled electrically with the source electrode at one end and coupled electrically with the drain electrode at the other end.

Abstract: A device includes a substrate; a bank provided on the substrate; and a metal wiring in a wiring forming region of the substrate that is sectioned by the bank with a liquid phase method. The metal wiring includes a first film formed along a bottom of the wiring forming region and a side face of the bank facing the wiring forming region. The metal wiring also includes a second film disposed on the first film.

Abstract: A stagger type TFT substrate and a fabrication method therefor in which the number of exposure processes is reduced. A resist pattern is formed in an area on the TFT substrate where a drain bus-line (DB) is to be formed and an area on the TFT substrate where a TFT is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the DB and a channel area for the TFT. In addition, a resist pattern is formed in an area where a gate bus-line (GB) is to be formed and an area where a pixel electrode is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the GB and the pixel electrode. The DB and the channel are formed by one half tone mask and the GB and the pixel electrode are formed by another half tone mask. As a result, the number of exposure processes necessary for fabricating a stagger type TFT substrate can be reduced.

Abstract: A display device includes a first substrate; a first electrode and a second electrode placed on the first substrate; a second substrate separately placed from and facing with the first substrate; a third electrode placed on the second substrate; a first layer placed between the first and second substrates, being on the first substrate, and including a luminescent material which becomes luminous in response to electrochemical oxidation or reduction; a second layer placed between the first and second substrates, being on the second substrate, and including a coloring material which discolors in response to electrochemical oxidation or reduction; and a third layer placed between the first and second layers, transmitting none of or few oxidizing species or reducing species in the luminescent material, and having ion conductivity and electron conductivity.

Abstract: Exemplary embodiments provide a scalable process for the growth of large scale and uniform III-N nanoneedle arrays with precise control of the position, cross sectional shape and/or dimensions for each nanoneedle. In an exemplary process, a plurality of nanoneedle array can be formed by growing one or more semiconductor material in a plurality of patterned rows of apertures with a predetermined geometry. The plurality of patterned rows of apertures can be formed though a thick selective nanoscale growth mask, which can later be removed to expose the plurality of nanoneedle arrays. The plurality of nanoneedle arrays can be connected top and bottom by a continuous coalesced epitaxial film, which can be used in a planar semiconductor process or be further configured as a photonic crystal to improve the output coupling of nanoscale optoelectronic devices such as LEDs and/or lasers.

Abstract: Extremely smooth (6 nm roughness) and continuous ultrananocrystalline diamond (UNCD) thin films were achieved by microwave plasma chemical vapor deposition using a thin 10 nm tungsten (W) interlayer between the silicon (Si) substrate and the diamond film. The W interlayer significantly increased the initial UNCD nucleation density to >1012 sites/cm2, thereby lowering the surface roughness and eliminating interfacial voids. A method is also disclosed to make various articles.

Abstract: The present application discloses a light source comprising an LED die having an emitting surface and an optical element including a base, an apex smaller than the base, and a converging side extending between the base and the apex, wherein the base is optically coupled to and is no greater in size than the emitting surface, and wherein the optical element directs light emitted by the LED die to produce a side emitting pattern.

Abstract: An LED extractor has an input surface adapted to optically couple to an emitting surface of an LED die, and is composed of a glass (including a glass-ceramic) material whose refractive index is at least 2, or at least 2.2.

Abstract: There is provided a highly reliable semiconductor light emitting device even in using for street lamps or traffic signals, which can be used in place of electric lamps or fluorescent lamps by protecting from surges such as static electricity or the like. A plurality of light emitting units (1) are formed, by forming a semiconductor lamination portion by laminating semiconductor layers on a substrate so as to form a light emitting layer, by electrically separating the semiconductor lamination portion into a plurality, and by providing a pair of electrodes (19) and (20). The light emitting units (1) are respectively connected in series and/or in parallel with wiring films (3). An inductor (8) absorbing surges is connected, in series, to the plurality of light emitting units (1) connected in series between electrode pads (4a) and (4b) connected to an external power source. For an example, the inductor (8) is formed by arranging the plurality of light emitting units (1) in a whirl shape.

Abstract: A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer.

Abstract: In one aspect, the present application discloses a light source comprising an LED die having an emitting surface and an optical element having a base, two converging sides, and two diverging sides, wherein the base is optically coupled to the emitting surface. In another aspect, the present application discloses a light source comprising an LED die having an emitting surface and a high index optical element optically coupled to the LED die and shaped to direct light emitted by the LED die to produce a side emitting pattern having two lobes.

Abstract: The present application discloses a light source comprising an LED die having an emitting surface, a first optical element including a base, an apex, and a converging side joining the base and the apex, wherein the base is optically coupled to the emitting surface and a second optical element encapsulating the LED die and the first optical element. In one aspect, the base is no greater in size than the emitting surface. In a second aspect, the apex resides over the emitting surface. In a third aspect, the second optical element provides an increase in power extracted from the LED die as compared to the power extracted by first optical element alone. In a fourth aspect, the first optical element has a first index of refraction and the second optical element has a second index of refraction lower than the first index of refraction.

Abstract: In one embodiment, a single light emitting diode lamp package includes at least two light emitting devices that can be switched independently of one another and thus may be useful in vehicular lighting applications, for example low and high beam headlights. In another embodiment, a LED device includes a first LED die and at least one additional LED die disposed at different positions within a common reflector cup. Multiple LED sub-assemblies may be mounted to a common lead frame along non-coincident principal axes. Methods for varying intensity or color from multi-LED lamps are further provided.

Abstract: A cover for use together with a transmitter of an encoded light or EMR beam for intercepting and re-directing the beam away from the transmitter toward a receiver, an optical device or another solid state device whereby data encoded on the encoded light or EMR beam can be transmitted out of the transmitter to a receiver and the data encoded thereon can be used or retransmitted.

Abstract: A lighting device having a light emitting diode (LED). The device includes a metal substrate having a surface. A dielectric coating layer is superimposed on the surface of the metal substrate. A light emitting diode (LED) is supported on the dielectric coating layer. The metal substrate serves as a heat sink for the heat emitted by LED during operation.

Abstract: An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-type modulation doped quantum well interfaces that are spaced apart from one another. Incident radiation within a predetermined wavelength resonates within the cavity of a given pixel element for absorption therein that causes charge accumulation. The accumulated charge is related to the intensity of the incident radiation. The heterojunction-thyristor-based pixel element is suitable for many imaging applications, including CCD-based imaging arrays and active-pixel imaging arrays.

Abstract: A donor substrate for a flat panel display includes a base film, a light-to-heat conversion layer on the base film, a first buffer layer on the light-to-heat conversion layer, the first buffer layer including an emission host material, a transfer layer on the first buffer layer, and a second buffer layer on the transfer layer, the second buffer layer including an emission host material identical to the emission host material of the first buffer layer.

Abstract: A semiconductor device having SRAM cell units each comprising a pair of driving transistors, a pair of load transistors and a pair of access transistors, in which each of the transistors has a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulting film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; a longitudinal direction of each semiconductor layer extends along a first direction; and between the adjacent SRAM cell units in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer in the other transistor which center line extends along the first direction.

Abstract: The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the gate widths to gate lengths for current driving while reducing resistance and power dissipation.

Abstract: An electro-optical device includes: a pair of substrates facing one another across an electro-optical substance layer; and a layered structure formed on one of the substrates, including scanning lines formed in a first direction, data lines formed in a second direction intersecting the first direction, pixel electrodes formed corresponding to the intersections, transistors for controlling switching of the pixel electrodes, storage capacitors electrically connected to the pixel electrodes, and a fixed electrode layer for supplying fixed potential to one electrode of the storage capacitors, the scanning lines, data lines, transistors, and storage capacitors being arrayed within a light shielding region around the pixel electrodes; wherein the pixel electrodes, and a semiconductor layer where the transistors are formed, are electrically connected via an relay electrode layer at the same layer as the fixed electrode layer; and wherein the fixed electrode layer is discontinuous between adjacent data lines in the f

Abstract: A charge transfer transistor includes: a first diffusion region and a second diffusion region; a gate for controlling a charge transfer from the first diffusion region to the second diffusion region by a control signal; and a potential well incorporated under the gate, wherein the first diffusion region is a pinned photodiode. A pixel of an image sensor includes: a photodiode for generating and collecting a photo generated charge; a floating diffusion region for serving as a photo generated charge sensing node; a transfer gate for controlling a charge transfer from the photodiode to the floating diffusion region by a control signal; and a potential well incorporated under the transfer gate.

Abstract: MOS-type solid-state image pickup device includes a photoelectric conversion unit having a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region, a third semiconductor region of the first conductivity type disposed at a light incident side of the second semiconductor region, and a transfer MOS transistor having the second semiconductor region, a fourth semiconductor region of the second conductivity type, and a gate electrode disposed on an insulating film on the first semiconductor region between the photoelectric conversion unit and the fourth semiconductor region to transfer a charge carrier from the second semiconductor region to the fourth semiconductor region. The photoelectric conversion unit and the transfer MOS transistor are disposed on a substrate.

Abstract: An image sensor applying a power voltage to a backside of a semiconductor substrate includes a first type semiconductor substrate, a first type semiconductor layer formed on the first type semiconductor substrate, a second type semiconductor layer formed on the first type semiconductor layer, and a power voltage receiver formed on a backside of the first type semiconductor substrate opposite the first type semiconductor layer with respect to the first type semiconductor substrate, wherein the power voltage receiver receives a power voltage from outside and applies the power voltage to the first type semiconductor substrate.

Abstract: An image sensor device includes a semiconductor substrate having a light-sensing region, and a first and second electrode embedded within the substrate. The first and second electrode forms an array of slits, the array of slits is configured to allow a wavelength of light to pass through to the light-sensing region. A method for making an image sensor device includes providing a semiconductor substrate, forming a plurality of pixels on the semiconductor substrate, and forming a plurality of slits embedded within each of the plurality of pixels. The plurality of slits is configured to allow a wavelength of light to pass through to each of the plurality of pixels.

Abstract: An image sensor includes a photosensitive region that accumulates charge corresponding to received incident light; a transfer gate for transferring all or a portion of the charge from the photosensitive region; a voltage supply having an increasing voltage over time that is applied to the transfer gate; a floating diffusion for receiving the all or a portion of the charge from the photosensitive region and converting the charge to a voltage; an amplifier for receiving and amplifying a signal from the floating diffusion; a pulse detector for detecting a voltage pulse from the amplifier; and a counter for counting clock cycles between initiation of the increasing voltage until a signal is received from the detector which indicates initiation of charge transfer from the photosensitive region to the floating diffusion.

Abstract: A white light photodiode has a film layer and an ultraviolet (UV) photodiode. The film layer is made of an oxide rich in silicon; and is formed through a chemical vapor deposition. A white light can be generated by exciting the film layer with a UV light from the UV photodiode.

Abstract: A reset transistor includes a floating diffusion region for detecting a charge, a junction region for draining the charge, a gate for controlling a transfer of the charge from the floating diffusion region to the junction region upon receipt of a reset signal, and a potential well incorporated underneath the gate.

Abstract: The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.

Abstract: An alignment mark for a semiconductor device is provided. The alignment mark defines a plane pattern and includes a conductive layer embedded in a recessed section provided in an insulation layer, and an oxidation barrier layer provided on the conductive layer, wherein an area occupancy ratio of the recessed section in the plane pattern is 5% or greater.

Abstract: A liquid crystal display device may comprise a semiconductor layer on a substrate and including a channel portion and ohmic contact portions at both sides of the channel portion, wherein an edge portion of the semiconductor layer has a side surface of a substantially tapered shape; a gate insulating layer covering the semiconductor layer; a gate electrode on the gate insulating layer and substantially corresponding to the channel portion; source and drain electrodes contacting the semiconductor layer; and a pixel electrode contacting the drain electrode.

Abstract: A memory structure, a memory device and a manufacturing method thereof are provided. First, a substrate is provided and a dielectric layer is formed over the substrate. Then, a pattern is formed in the dielectric layer. An amorphous silicon layer is formed in the pattern and over the dielectric layer. The amorphous silicon layer is patterned to form an electrode over the pattern. Then, a spacer is formed on the sidewall of the electrode. A selective hemispherical grains (HSGS) layer is formed over the surface of the electrode and the surface of the spacer.

Abstract: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell.

Abstract: An ID tag capable of communicating data wirelessly, the size of which is reduced, and where the size of an IC chip is reduced, a limited area of the chip is effectively used, current consumption is reduced, and communication distance is prevented from decreasing. The ID tag of the invention includes an IC chip having an integrated circuit, a resonance capacitor portion and a storage capacitor portion, and an antenna formed over the IC chip so as to overlap at least partially with an insulating film interposed therebetween. The antenna, the insulating film and wirings or semiconductor films forming the integrated circuit are stacked, and one or both of capacitors in the resonance capacitor portion and the storage capacitor portion are formed by this stacked structure.

Abstract: The semiconductor memory device has a substrate with a main surface, on which parallel trenches are arranged. A memory layer is disposed at the sidewalls of the trenches, and gate electrodes are disposed in the trenches. Buried bitlines are formed as doped regions between neighboring trenches. The buried bitlines abut the sidewalls of the trenches and comprise upper surfaces, which are arranged at a specified distance from the bottom of the trenches. Source/drain regions are formed by sections of the buried bitlines.

Abstract: A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.

Abstract: A capacitance of a capacitor including a metal electrode is increased by using a dielectric film having a high dielectric constant. A band gap is reduced as the dielectric constant of a material is increased. In a dielectric having the dielectric constant of 50 or more such as strontium titanate, the high dielectric constant is ensured due to the crystallization but the side effect of the increased leakage current occurs. Since the replacement of the material requires the significant change of the manufacturing apparatus or the manufacturing process, the manufacturing cost is increased. Hafnium oxide is not replaced with the other materials, but the dielectric constant of hafnium oxide is improved to increase the capacitance. An element having a large ion radius such as yttrium is added in a small amount to increase the dielectric constant of hafnium while an amorphous state is maintained. The capacitor process where the amorphous state is maintained is applied to produce the DRAM at low cost.

Abstract: This disclosure concerns a semiconductor device comprising a convex-shaped semiconductor layer formed on a semiconductor substrate; an insulation film formed on the semiconductor substrate, the insulation film having a film thickness to the extent that a lower part of the semiconductor layer is buried; a gate electrode formed on a set of both opposed side faces via a gate insulation film; and a source region and a drain region formed on a side face side on which the gate electrode is not formed in the semiconductor layer, wherein the semiconductor layer is formed so as to dispose surfaces of a peripheral part excepting a central part on an outer side than surfaces of the central part covered by at least the gate electrode.

Abstract: The memory device includes a source region and a drain region in a substrate and spaced apart from each other; a memory cell formed on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; a control gate formed on the memory cell. The memory cell includes a first tunneling oxide layer formed on the substrate; a second tunneling oxide layer formed on the first tunneling oxide layer; and a control oxide layer formed on the second tunneling oxide layer. The control oxide layer includes the nanocrystals. The second tunneling oxide layer, having an aminosilane group the increases electrostatic attraction, may be hydrophilic, enabling the formation of a monolayer of the nanocrystals.

Abstract: A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers which allows a tunnel window of a storage device to be fabricated in close proximity to an associated select gate and with a reduced gate width compared to typical devices. The tunnel window is recessed within an upper surface of a substrate. The tunnel window recess is made possible by selective etching of the substrate and oxides covering the substrate. A substantial reduction in the size of a tunnel window means device scaling is possible far beyond what is attainable with standard photolithography. Standby current is reduced significantly by fabricating a select device with complementary material types for the gate compared with the adjacent source/drain regions.

Abstract: Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates.

Abstract: Structures and methods to form a bistable resistive random access memory for reducing the amount of heat dissipation from electrodes by confining a heating region in the memory cell device are described. The heating region is confined in a kernel comprising a programmable resistive memory material that is in contact with an upper programmable resistive memory member and a lower programmable resistive memory member. The lower programmable resistive member has sides that align with sides of a bottom electrode comprising a tungsten plug. The lower programmable resistive member and the bottom electrode function a first conductor so that the amount of heat dissipation from the first conductor is reduced. The upper programmable resistive memory material and a top electrode function as a second conductor so that the amount of heat dissipation from the second conductor is reduced.

Abstract: The invention concerns a field-effect transistor with a drain, a source, a channel in electrical contact with the source and the drain, and at least one gate, so as to apply an electric field to the channel when each gate is polarised, where the channel has a multi-layer structure with at least three layers, and with at least one of the layers of the multi-layer structure having electrical properties that are substantially different from those of another layer of the multi-layer structure, and wherein a single gate or two gates are arranged substantially perpendicular to a reference plane of the channel defined by an interface plane between two layers of the multi-layer structure.

Abstract: A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.

Abstract: A deep source/drain region and a source/drain extension region may be formed in a semiconductor substrate adjacent to a gate electrode. A first silicide layer may be formed on the source/drain extension region. A gate spacer may be formed on a sidewall of the gate electrode to cover the first silicide layer. A second silicide layer may be formed on the deep source/drain region outside the gate spacer.

Abstract: An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate electrode. The first insulating film and the second insulating film are formed in separate steps, and the first insulating film is thicker than the second insulating film. With this structure, when an insulating film is provided between the floating gate electrode and a silicon substrate to have a thickness more increased at its end portion than at its middle portion, the thickness can be increased more freely and a degree of the increase can be controlled more readily.

Abstract: By decreasing the threshold voltage shift due to the potential change of the cells adjacent in a word line direction, the reliability of a flash memory can be enhanced. Memory cells of a flash memory are formed in p-type wells of a semiconductor substrate and include gate insulator films, floating gates, high-K insulator films, and control gates (word lines). The floating gates and control gates (word lines) are isolated by high-K insulator films. The plurality of memory cells arrayed in row a direction are isolated by isolation trenches extending in a column direction. In the isolation trenches, a silicon oxide film is embedded. In the silicon oxide film, an air gap is provided. A lower end of the air gap extends near to the bottom of the isolation trench, and its upper end extends further above the upper surface of the high-K insulator film covering the floating gate.