Abstract: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 ?m, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

Abstract: A NAND non-volatile two-bit memory cell comprises a cell stack and two select stacks disposed on an active area of a substrate. Each select stack is respectively disposed on a side of the cell stack with a sidewall between the cell stack and a respective select stack. The cell stack has four components: a first dielectric layer disposed over the substrate; a charge accumulation layer capable of holding charge in a portion thereof to store information and disposed over the first dielectric layer; a second dielectric layer disposed over the charge accumulation layer; and a control gate disposed over the second dielectric layer. The select stack has two components: a third dielectric layer disposed over the substrate and a select gate, capable of inverting an underneath channel region to function as a source or a drain of the memory cell, disposed over the third dielectric layer.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: A PMOS transistor of a semiconductor device exhibiting improved characteristics, a semiconductor device incorporating the same, and a method for manufacturing the semiconductor device. The PMOS transistor incorporates a first gate insulation film formed in a predetermined region on a semiconductor substrate and comprising a hafnium-based oxide, a second gate insulation film formed on the first gate insulation film for shielding reaction between hafnium and silicon, and a gate conductive film formed on the second gate insulation film and comprising polysilicon.

Abstract: A body-tied MOSFET device and method of fabrication are presented. In the method of fabrication, oxygen diffuses and reacts down a first axis of a pFET or nFET. This results in a partial oxidation of a buried-oxide/silicon island interface. The partial oxidation produces a thickness variation in the silicon island that creates a stress along the first axis. The stress along the first axis modifies a device characteristic of the FET. Oxidation along a second, perpendicular, axis may also be inhibited. The partial oxidation may be incorporated in SOI and STI based process flows. In addition, a dual-gate oxidation process may further enhance device characteristics.

Abstract: The present invention provides a method for manufacturing massively and efficiently a minute device which can receive or send data in contact, preferably, out of contact by forming an integrated circuit which is formed by a thin film over a large glass substrate and by peeling the integrated circuit from the substrate. Especially, an integrated circuit which is formed by a thin film is extremely thin, and so there is a threat that the integrated circuit is flied when transporting, and so handling thereof is difficult. In accordance with the present invention, a separating layer (also referred to as a peeling layer) is damaged at a plurality of times by at least two different kinds of methods (a damage due to laser light irradiation, a damage due to etching, or a damage due to a physical means), subsequently, the layer to be peeled can be efficiently peeled from a substrate. Further, handling of individual devices becomes easy by arching the peeled device.

Abstract: An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

Abstract: A terminating resistance element of an LSI chip has an N? type impurity diffusion region formed at the surface of a P type well at the surface of a semiconductor substrate, an N+ type impurity diffusion layer formed at the surface of the N? type impurity diffusion region, and a pair of electrodes formed at respective ends at the surface of the N+ type impurity diffusion layer. The N? type impurity diffusion region has an impurity concentration lower than the impurity concentration of the N+ type impurity diffusion layer. Therefore, the capacitance of the PN junction becomes smaller as compared to the conventional case where the N type impurity diffusion layer is provided directly at the surface of a P type semiconductor substrate. Therefore, reflection and attenuation of an input signal are suppressed.

Abstract: A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of body tie that is shared between at least two FETs. A second trench may also be formed within the first trench. The second trench stops in the SOI substrate. The second trench defines the location and shape of a body-tie. Once the location and shape of the body-tie are defined, an oxide is deposited above the body-tie. The deposited oxide prevents certain implants from entering the body tie. By preventing these implants, a source and a drain implant may be self-aligned to the source and drain areas without requiring the use of the photoresist mask to shield the body tie regions from the source and drain implant.

Abstract: Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same.

Abstract: A semiconductor device comprising a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprising a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width of the second gate structure.

Abstract: A semiconductor device is provided with a first MISFET including a first gate insulating film including a HfAlO film formed over a semiconductor substrate and a first gate electrode, including a nickel silicide film, formed over the first gate insulating film. An aluminum concentration of the HfAlO film on a side of the HfAlO film facing the first gate electrode is higher than an aluminum concentration of the HfAlO film on a side of the HfAlO film facing the semiconductor substrate.

Abstract: A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.

Abstract: A topography (40) is provided which includes a device having a transistor formed from a stack of semiconductor layers (42/46). The different semiconductor layers are spaced apart by a gate (60) and by support structures (48) comprising a material having different etch characteristics than the materials of the spaced apart semiconductor layers. The device includes a first transistor channel (76) within the upper semiconductor layer and, in some cases, further includes a second transistor channel within the lower semiconductor layer. The resulting hybrid transistor structure may be fabricated as one of a pair of CMOS transistors, the other of which may include the same configuration or a different configuration. A method for fabricating the hybrid transistor structure includes forming a gate structure surrounding a suspended portion (52) of an upper patterned semiconductor layer (53) and extending down to a surface of a lower semiconductor layer (42).

Abstract: A stacked contact structure includes a first contact plug of a first conductive material filling a first contact hole in a first dielectric layer, and a second contact plug of a second conductive material filling a second contact hole in a second dielectric layer. The second conductive material is different from the first conductive material, and the second conductive material has an electrical resistance lower than that of the first conductive material.

Abstract: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.

Abstract: A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.

Abstract: An integrated circuit structure is formed on a substrate. The integrated circuit structure includes a logic area and a memory cell area. The memory cell area includes a charge storage area and a non-charge storage area. A dielectric layer is formed on the substrate in the charge storage area. A thyristor is formed on the dielectric layer. A transistor is formed on the substrate in the non-charge storage area.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first implantation process in the first orientation of the workpiece. The semiconductor device is implanted with the dopant species using a second implantation process in the at least one second orientation of the workpiece, wherein the second implantation process is different than the first implantation process.

Abstract: A sensor device includes a substrate having first and second regions of first and second conductivity types, respectively. A junction having a band-gap is formed between the first and second regions. A plasmon source generates plasmons having fields. At least a portion of the plasmon source is formed near the junction, and the fields reduce the band-gap to enable a current to flow through the device.

Abstract: The present invention is directed towards radiation detectors and methods of detecting incident radiation. In particular the present invention is directed towards photodiodes with controlled current leakage detector structures and a method of manufacturing photodiodes with controlled current leakage detector structures. The photodiodes of the present invention are advantageous in that they have special structures to substantially reduce detection of stray light. Additionally, the present invention gives special emphasis to the design, fabrication, and use of photodiodes with controlled leakage current.

Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

Abstract: An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.

Abstract: A bipolar transistor having the enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film for masking thereby to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront, and the increase of resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have the enhanced characteristics.

Abstract: A method of growing bulk single crystals of an AlN on a single crystal seed is provided, wherein an AlN source material is placed within a crucible chamber in spacial relationship to a seed fused to the cap of the crucible. The crucible is heated in a manner sufficient to establish a temperature gradient between the source material and the seed with the seed at a higher temperature than the source material such that the outer layer of the seed is evaporated, thereby cleaning the seed of contaminants and removing any damage to the seed incurred during seed preparation. Thereafter, the temperature gradient between the source material and the seed is inverted so that the source material is sublimed and deposited on the seed, thereby growing a bulk single crystal of AlN.

Abstract: Embodiments of the invention relate to a process for producing a III-N bulk crystal, wherein III denotes at least one element selected from group III of the periodic system, selected from Al, Ga and In, wherein the III-N bulk crystal is grown by vapor phase epitaxy on a substrate, and wherein the growth rate is measured in real-time. By actively measuring and controlling the growth rate in situ, i.e. during the epitaxial growth, the actual growth rate can be maintained essentially constant. In this manner, III-N bulk crystals and individualized III-N single crystal substrates separated therefrom, which respectively have excellent crystal quality both in the growth direction and in the growth plane perpendicular thereto, can be obtained.

Abstract: An illuminator (1) is manufactured by embossing an aluminium preform to provide a structured substrate base (21) with cavities (25) for LEDs and recesses (26) for tracks. The substrate is anodised to provide an aluminium oxide insulating layer (30) over the structured surface. A metal layer (35) is then applied over the insulating layer (30), and this is etched to leave metal pads in the cavities and tracks in the recesses (26). LEDs (50) are placed in the cavities and they are wire-bonded to the exposed metal tracks. This manufacturing method allows versatility in choice of configuration of 5 illuminator by simple embossing a desired substrate shape. Also, the anodisation provides an excellent and durable insulating layer, which has the major benefit of being conformal with the structured surface.

Abstract: A semiconductor device is provided that includes a semiconductor substrate, an n-channel MOSFET formed on the substrate and a p-channel MOSFET formed on the substrate. A first layer is formed to cover the n-channel MOSFET, wherein the first layer has a first flexure-induced stress. A second layer is formed to cover the p-channel MOSFET, wherein the second layer has a second flexure-induced stress.

Abstract: To provide a shield substrate, semiconductor package and semiconductor device which can give improved resistance to thermal stress. The shield substrate according to this invention is provided with a conductive film on which slits each having a shape through which electromagnetic wave noise does not leak are formed. These slits are rectangular slits formed in an array on the conductive film. In accordance with this configuration, the length of the straight line on the conductive film is interrupted by the slits, and thermal stress generated on the conductive film is interrupted by the slits. Thus, the thermal stress on the conductive film will not be excessively concentrated at one point, thereby preventing crack or flake-off from occurring on the conductive film.

Abstract: A method of manufacturing a coaxial trace (100) within a surrounding material (190) includes: providing a first substrate (191, 410) and a second substrate (192, 1010) composed of the surrounding material; forming a first portion (101, 601) of the coaxial trace in the first substrate; forming a second portion (102, 1001) of the coaxial trace in the second substrate; aligning the first portion of the coaxial trace with the second portion of the coaxial trace; and bonding the first portion of the coaxial trace to the second portion of the coaxial trace.

Abstract: Shield structures are provided. A first and second shield lines are formed over a substrate and coupled with a first voltage. A conductive line is formed between the first and the second shield lines, and coupled with a second voltage. The first shield layer is formed over the substrate and coupled to the first and the second shield lines via at least one first conductive structure.

Abstract: An integrated circuit includes a first and a second die positioned on a lead frame of a package. The lead frame includes a plurality of bond fingers. The integrated circuit includes a first bond pad on the first die that is electrically interconnected to a corresponding second bond pad on the second die through first and second bond fingers of the lead frame. The package may be a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame.

Abstract: A structure of a lead-frame matrix of photoelectron devices is provided. The lead-frame matrix is used to fabricate a first lead-frame array and a second lead-frame array. In the structure of the lead-frame matrix of the photoelectron devices, pins of the first lead-frame array and pins of the second lead-frame array are alternatively inserted.

Abstract: A method of manufacturing photo couplers is provided. At first, a receiver lead-frame array is cut from a lead-frame matrix having a transmitter lead-frame array and the receiver lead-frame array. Then, the receiver lead-frame array is overturned and placed on the lead-frame matrix to allow light-receiver elements on the receiver lead-frame array to face light-emitting elements on the transmitter lead-frame array of the lead-frame matrix. Finally, the receiver lead-frame array and the lead-frame matrix are connected.

Abstract: A high voltage semiconductor module has a leadframe with spaced pads which is connected to a heat sink plate by a curable insulation layer on the top of the plate. Semiconductor die may be soldered to the leadframe pads before or after assembly to the plate. The insulation layer may be a curable epoxy or a B stage IMS plate.

Abstract: A flip chip type LED lighting device manufacturing method includes the step of providing a strip, the step of providing a submount, the step of forming a metal bonding layer on the strip or submount, the step of bonding the submount to the strip, and the step of cutting the structure thus obtained into individual flip chip type LED lighting devices.

Abstract: A package structure includes: a substrate having a chip-bearing area arranged thereon; an window type assistant element arranged on the substrate and surrounding the edge of the chip-bearing area; a plurality of chips arranged within the chip-bearing area; and a package encapsulation covering chips within the chip-bearing area. It can resist the deformation and reduce the damage from the warpage and simultaneously enhance the yield and stability of the package structure.

Abstract: A process yield of a semiconductor device is enhanced. To that end, there is provided a semiconductor device comprising a substrate having a component mount face with semiconductor chips mounted thereon, the substrate being provided with a plurality of connection leads, and a cap made of resin, placed over the component mount face of the substrate so as to cover the same, the a cap having a first body part, and a second body part larger in thickness than the first body part. Because product information in the form of inscriptions is engraved on the top surface side of the second body part of the cap, the product information can be displayed without the use of an ink mark, it is possible to prevent occurrence of marking defects due to ink bleed, and so forth, thereby enhancing the process yield of a memory card (the semiconductor device).

Abstract: A chip structure comprising a substrate, a conductive layer, a plurality of bumps and a trap layer is provided. The substrate has a plurality of pads and the conductive layer is disposed on the pads. The bumps are disposed on the conductive layer above the pads and the trap layer is disposed between two adjacent bumps. In addition, a process of fabricating the chip structure is provided.

Abstract: A multiple chip package module comprises a first substrate, a first chip, an inverted first semiconductor unit, a first encapsulant, and a second semiconductor unit. The first chip is disposed on the first substrate. The inverted first semiconductor unit is stacked over the first chip. The first encapsulant covers the first chip and the first semiconductor unit, and the first encapsulant has an opening to expose a part of the first semiconductor unit. The second semiconductor unit comprises a plurality of first bumps on a bottom side of the second semiconductor unit, the second semiconductor unit mounted on the first semiconductor unit in the opening, and is electrically connected to the first semiconductor unit through the first bumps.

Abstract: There is provided a stacked IC module including first and second leaded packages in stacked disposition, each of the first and second leaded packages having plural leads emergent along at least one side of each of the respective leaded packages, and a flexible circuit disposed in part between the first and second leaded packages, wherein the flexible is folded back on itself to create an arcuate connective field that is compressed to have conformity with the plural leads of the first and second leaded packages.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other.

Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.

Abstract: A semiconductor package is disclosed including test pads formed of solder bumps affixed to the semiconductor package during fabrication. When the package is encapsulated, due to the pressure exerted on the package during the encapsulation process, portions of the solder bumps get flattened out to be generally flush with and exposed on a surface of the semiconductor package. These exposed portions of the solder bumps form the test pads by which the finished package may be tested.

Abstract: A semiconductor chip includes a line structure arranged along a peripheral region of the semiconductor chip region in order to inspect a crack, a first pad and second pad arranged on different end portions of the line structure, a second pad arranged on another end portion of the line structure, an inspection device activated during a crack test mode to electrically connect the first pad, the line structure and the second pad. The inspection device may include a first switching circuit connected between the first pad and the line structure, the first switching circuit being deactivated during a normal operation mode and being activated a crack test mode; and a second switching circuit connected between the second pad and the line structure, the second switching circuit being deactivated during the normal operation mode and being activated during the crack test mode.

Abstract: A method and system are described for obtaining a first code role indicator, an association between the first code role indicator and a first code module, and a second code role indicator and circuitry for deciding whether to install a second code module in a first node, responsive to a result of a comparison between the first code role indicator and the second code role indicator.

Abstract: In the vicinity of soldering through holes of lands for soldering a lead terminal in a multilayer printed board, electrically isolated lands are provided to form a thermal through hole. In the soldering, by the radiation and supply of heat of a lead-free solder filled in the thermal through hole, it is possible to suppress the radiation of heat of the soldering through hole. Thus, it is possible to achieve a sufficient solder rise and to obtain an excellent soldering property.