Abstract: The invention relates to a circuit arrangement for production of a reset signal after a supply voltage (Vdd) has fallen and risen again, which circuit arrangement has two cross-coupled inverters (INV1, INV2) and an initialization circuit (S) which is connected to the input of one of the inverters (INV2), in which case the outputs of the inverters (INV1, INV2) are capacitively connected asymmetrically, andlor in which case the inverters (INV1, INV2) have different transfer voltages.

Abstract: A control circuit for command signals of a clock generator includes a power supply end, an output end, a control end, a diode, a first resistor and a second resistor. The first resistor, the diode, and the second resistor are connected in series between the power supply end and the ground. The diode has an anode connected to the first resistor and a cathode connected to the second resistor. The control end is connected to a node between the diode and the second resistor; the output end is connected to a node between the diode and the first resistor. The output end outputs the command signals to the clock generator.

Abstract: A system and method for power-on reset and under-voltage lockout schemes. The system includes a first transistor, which includes a first gate, a first terminal, and a second terminal, the second terminal being biased to a predetermined voltage. The system includes a second transistor, which include a second gate, a third terminal, and a fourth terminal, the third terminal being configured to receive an input voltage. The system includes a first resistor that is associated with a first resistance. The first resistor includes a fifth terminal and a sixth terminal, the fifth terminal being configured to receive the input voltage. The system includes a second resistor that is associated with a second resistance. The second resistor includes a seventh terminal and an eighth terminal, the seventh terminal being coupled to the sixth terminal. The system includes a first Zener diode that is associated with a first Zener voltage.

Abstract: A circuit for timing adjustment includes a PLL circuit configured to generate a phase-adjusted clock signal in response to phase comparison between an input clock signal and a delayed clock signal, a feedback path configured to delay the phase-adjusted clock signal for provision as the delayed clock signal to the PLL circuit, a first timing correction circuit configured to add a predetermined delay time to the feedback path, an output data circuit configured to supply output data at first timing responsive to the phase-adjusted clock signal, a second timing correction circuit configured to delay the first timing by the predetermined delay time to generate second timing different from the first timing, and an input data circuit configured to latch input data at the second timing.

Abstract: The DLL circuit detects a frequency of an external clock signal and adjusts a coarse delay during a DLL circuit operation, thereby quickly terminating a feedback operation of the DLL circuit and having a reduced circuit area of a delay line. Therefore, the DLL circuit can be used for next generation high-integration and high-frequency memory devices such as DDR2 SDRAMs.

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract: A delay locked loop (DLL) includes a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal. A phase detector receives as input the input clock signal and the delayed clock signal and outputs a signal proportional to the phase difference between the input clock signal and the delayed clock signal to provide a control voltage for adjusting the delay to the specified amount. A pulse swallower removes a pulse from the input clock signal or from the delayed clock signal to reverse the direction of the control signal.

Abstract: A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T thereof into N parts, and includes first variable delay sections and second variable delay sections, each of which is formed of an arbitrary number of unit delay buffers connected in series with one another. A phase comparison section makes a compare between the phase of the input clock signal and the phase of an output signal which is the input signal having been delayed while passing through all the first and second variable delay sections, and outputs a result of the comparison. A delay control section calculates a total number of unit delay buffers S required based on the phase comparison result, sets a quotient Q of S divided by N to be the number of unit delay buffers for each of the first variable delay sections, and allocates a remainder R of S divided by N to the second variable delay sections, respectively.

Abstract: Embodiments may include a duty cycle controller to adjust the duty cycle of the clock signal based upon a delay signal and an input clock signal. A duty cycle detector may determine signals with frequencies based upon the duty cycle of the output signal and a correction module may compare the frequencies of the detector signals to generate the delay signal. In some embodiments, once the duty cycle of the output clock signal reaches the desired duty cycle such as fifty percent, the correction module may be turned off.

Abstract: A steering current generator for a phase interpolator has a multiplicity of fine phase adjustment current sources, each of which is switchable to direct its current to one or other of two summing nodes. The current of each of those two summing nodes is supplemented by respective fixed always-on current sources. The steering current generator has four current outputs and a switching matrix is provided to switch the current from the summing nodes to first and second selected ones of those outputs. The switching matrix is also connected to switch bleed currents to the other two of the current outputs.

Abstract: Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.

Abstract: A level shifter circuit includes first and second reference potential supply lines; first and second output potential supply circuits each connected between the first and second reference potential supply lines; first and second input lines; first and second output lines; and a stress test circuit which functions to, during normal operation, when the first input signal and the second input signal are input to the first input line and the second input line, output the first output signal and the second output signal having respectively different potentials for the first output line and the second output line, and during the stress test, when the first input signal and the second input signal are input to the first input line and the second input line, output signals having identical potentials from the first output line and the second output line.

Abstract: An increasing number of phases in multiphase converters causes an increase in requirements with respect to the control IC. According to the present invention, instead of deriving a new PWM signal for every single phase of the DC-DC converter, the single phases are clustered into groups (22, 24, 26). Within each group, the converters are operated on the basis of one PWM signal (PW M1, PW M2 . . . PW MN). Advantageously, this may allow to reduce the requirements with respect to the control IC and thus may allow the application of cheaper and smaller control ICs.

Abstract: A charge pump comprises a single voltage multiplier stage (1) which converts an input voltage (VDD) into an output voltage (Vo) under control of a clock signal (Q, Qn; CLKO). An oscillator (2) receives the input voltage (VDD) to generate the clock signal (Q, Qn; CLKO) having a repetition period (Tr1, Tr2) which is substantially proportional to a squared input voltage (VDD2).

Abstract: A substrate voltage generating circuit for use in a semiconductor memory device is provided. The semiconductor memory device includes a charge pump for generating a substrate bias voltage in response to a clock signal; a first inverter type detector for detecting whether the substrate bias voltage reaches a target voltage; a second differential amplifier type detector for detecting whether the substrate bias voltage reaches the target voltage; and a driver for generating the clock signal in response to an output of one of the first and second detectors.

Abstract: Internal voltage generators are provided, as well as methods of overdriving an internal voltage generation circuit. Embodiments of the internal voltage generator comprise a first driver for receiving an external voltage to supply an internal voltage to the internal circuit in response to an input voltage; a comparator for comparing a reference voltage with a fed-back internal voltage to generate the input voltage of the first driver; a variable pulse generating circuit responsive to an input pulse; and a second driver for dropping the input voltage of the first driver to a ground voltage in response to the variable pulse produced by the variable pulse generating circuit. The internal voltage generator can generate the internal voltage of a relatively constant level without regard to increase of the external voltage or frequency of an operating signal.

Abstract: Implementing maintenance of a higher speed with fewest possible additional circuits while suppressing deterioration in characteristics of a clock buffer caused by an offset voltage. In a clock buffer circuit comprising a differential amplifier including a pair of load resistances, a pair of differential stage transistors, a constant current source transistor for supplying an operating current to the differential stage transistors, and a bias circuit for supplying to the constant current source transistor a bias voltage according to the resistance value of the load resistances, the bias circuit generates the bias voltage so controlled that the voltage gain of the clock buffer circuit becomes a predetermined value with respect to a variation of the resistance value of the load resistances.

Abstract: An FSK demodulator which outputs an enable signal in response to the detection of a data change point in a detected signal of an amplitude associated with the received frequency of an input FSK signal, outputs an average signal of the detected signal for each predetermined time period, acquires the average signal in response to the enable signal to output as an offset signal an average value of M average signals, and subtracts the offset signal from the detected signal to output the resulting signal.

Abstract: An amplification system capable of reducing DC offset in a baseband signal, which has first and second differential output terminals, first and second low pass filters, and first and second amplifiers. The first low pass filter filters a first input signal to thus generate a first filtered signal. The first amplifier amplifies the first input signal and the first filtered signal to thus generate a first amplified signal. The second low pass filter filters a second input signal to thus generate a second filtered signal. The second amplifier amplifies the second input signal and the second filtered signal to thus generate a second amplified signal. The system couples the first and second amplified signals at the first and the second differential output terminals to thus reduce the DC offset of a differential voltage signal output by the first and second differential output terminals.

Abstract: A method and an apparatus for outputting an audio signal are provided. The apparatus includes a power source; a compensator for compensating an input signal by adding the input signal to an offset value reciprocally proportional to a source voltage; a pulse width modulator for modulating an audio signal transmitted from the compensator; and an output stage for outputting the modulated audio signal. Accordingly, audio quality can be improved directly for a listener by compensating the input signal damaged by periodical voltage drops.

Abstract: An amplifier circuit amplifies a signal inputted from an input terminal. A first feedback circuit is placed across an emitter of a bipolar transistor and an input of the amplifier circuit. A second feedback circuit is placed across the input and an output of the amplifier circuit for feeding the output of the amplifier circuit back to the input of the amplifier circuit. A phase change amount in the feedback circuit is determined by the values of an inductor and a capacitor. The values of these elements are selected so that a phase of a signal in which fundamental waves included in two feedback signals are combined and a phase of a signal in which second harmonics included in the two feedback signals are combined are shifted by approximately 180 degrees from a phase of a fundamental wave of an input signal.

Abstract: A multiband amplifier for a test and measurement instrument includes a splitter to split an input signal into split signals, amplifiers, and means for combining and digitizing the amplified signals into a digitized signal. Each amplifier is configured to amplify an associated split signal over an amplifier passband. The amplifier passband of at least one amplifier is different from the amplifier passband of another amplifier.

Abstract: Systems and methods are disclosed for providing automatic gain control of a multi-stage system. A method can include defining at least one parameter that is adapted to at least one of maximize hardware capacity of each of a plurality of gain stages and mitigate part-to-part variations of the multi-stage system. An order is selected for training the plurality of stages based on relative noise dominance for the plurality of stage. For a given stage of the plurality of stages, which is selected according to the selected order, output signals of the multi-stage system are measured over a plurality of gain settings for the given stage. A gain setting of the given stage of the multi-stage system also is configured based on the measured output signals relative to the at least one parameter defined for the given stage. The plurality of gain stages can include an analog equalizer as well programmable gain amplifiers connected in series.

Abstract: An automatic level control circuit comprises a level detection circuit which detects attack detection to sense a detection level greater than a predetermined level and recovery detection to sense a detection level smaller than the predetermined level, and a gain control circuit which outputs a gain adjustment control signal to regulate a gain of an variable gain amplifier such that an output signal from the variable gain amplifier is set to a predetermined signal level. The gain control circuit generates multiple candidate signals to change the gain at different response speeds, and selectively outputs, as a gain adjustment control signal, one of the candidate signals capable of providing the smallest value as the gain. Therefore, even when the gain is rapidly reduced by the attack action against a short-duration large signal, the gain can be returned to its original state at an appropriate speed.

Abstract: A Class D amplifier comprises a ramp generator that generates a first reference signal and a second reference signal. A signal generator generates a first signal as the first reference signal exceeds an input signal to the Class D amplifier and generates the first signal as the second reference signal exceeds the input signal. The signal generator generates a second signal as the first reference signal falls below the input signal and generates the second signal as the second reference signal falls below the input signal.

Abstract: An amplifier (10) includes a first stage (4) including differentially coupled first (Q1) and second (Q2) input transistors and a controlled active load circuit (6). A second stage (8) includes differentially coupled third (Q5) and fourth (Q6) input transistors and a load circuit (Q7,8). A first output (2A) of the first stage (4) is coupled to a first input of the second stage (8), a second output (2B) of the first stage (4) being coupled to a second input of the second stage (8). A common mode feedback amplifier (12) has an input coupled to receive a common mode signal (3) from the second stage (8) for producing an amplified common mode signal (9) on a control input of the controlled active load circuit (6) to provide fast settling of an output (Vout) of the second stage without substantially increasing amplifier noise.

Abstract: A push-pull amplifier includes a pair of transistors, wherein each of the transistors has a control terminal, a first terminal, and a second terminal. A current that flows between the first terminal and the second terminal is controlled in accordance with signals applied to the control terminal, such that when an amount of current flowing between the first terminal and the second terminal of one of the transistors is within a predetermined range, a high-frequency component of the signals input to the control terminal of one of the transistors is amplified, and when this current is outside the predetermined range, the high frequency component is not amplified.

Abstract: An automatic level control circuit comprises a gain controllable amplifier, a comparing and outputting circuit which compares a level of an output signal from the gain controllable amplifier with a reference level and outputs a result of comparison as a comparison result signal; an output signal restricting circuit which restricts the comparison result signal obtained in a period between one zero crossing point and another zero crossing point of the input signal such that a portion of the comparison result signal obtained within a predetermined output time is output, and an attack detecting and outputting circuit which restricts an output signal from the comparing and outputting circuit to the portion of the comparison output signal obtained within the predetermined time when the comparison result signal is output over the predetermined output time and outputs the restricted comparison result signal as an attack detection output signal.

Abstract: An input impedance matching circuit for a low noise amplifier includes a source pad, a gate pad, an input transistor, a source degeneration inductor and a matching capacitor. The gate pad receives an input signal and the input transistor amplifies the input signal transmitted from the gate pad. The source degeneration inductor electrically coupled to an external ground voltage is adapted for input impedance matching of the low noise amplifier. The source pad is coupled to a source electrode of the input transistor and the matching capacitor is formed between the gate pad and the source pad extending the source pad to be disposed under the gate pad. Accordingly, impedance matching of the low noise amplifier may be facilitated and the gain and noise figure of the low noise amplifier may be improved.

Abstract: An amplifying circuit with a variable supply voltage and a method thereof are disclosed. The amplifying circuit employs a voltage converter to adjust the supply voltage, thereby upgrading the energy efficiency of the circuit. The circuit also includes a control device, which can generate a control signal for controlling the voltage converter according to an output signal or input signal of the circuit.

Abstract: The present invention provides an amplifying circuit capable of accomplishing high-impedance input/output, and providing a high gain and low power consumption. The amplifier amplifies a signal received through an input terminal, and outputs the signal through an output terminal. A control circuit comprised of the inductors, and the switches turns input/output impedances of the amplifier into a high impedance.

Abstract: A digital phase locked loop apparatus includes an input signal time detecting device that detects a phase of an input signal with prescribed time resolution obtained by dividing a cycle of an operation clock generated by a clock generator at a prescribed time. An output clock generating device outputs output clock time data per the one cycle in accordance with frequency control data. The output clock time data has a value corresponding to a phase of a virtual output clock generated by dividing the operation clock in accordance with the time resolution. A phase difference detecting device detects a difference between phases of the input signal and the virtual output clock, and outputs a phase difference signal in accordance with the detection result. The frequency control device changes the frequency control data in accordance with the phase difference signal.

Abstract: A phase shifter is fed an input signal having a frequency f. A coupler is included fed by the input signal. The coupler has a pair of output terminals for providing a pair of signals having the frequency f and having a relative phase shift difference of m?/2 radians, where m is an integer. A switch is included having a pair of inputs, each one of the pair of inputs being coupled to a corresponding one of the pair of output terminals of the coupler. The switch has an output, one of the pair of inputs of the switch being coupled to the output of the switch selectively in accordance with a first control signal fed to the switch.

Abstract: A frequency synthesizer is provided with a PLL, including a divider by N circuit and a phase generation circuit which is connected to the output of the VCO of the PLL. The phase generation circuit generates a predetermined number of phases synchronized on the frequency of the VCO and at intervals from each other equal to a time difference representative of a phase error measured by a phase comparator of the PLL. A signal generation circuit provides an intermediate signal starting from the phases, the period of which is dependent on the time difference and a first adjustment parameter. The intermediate signal is applied to the divider by N circuit. A correction circuit determines the phase error accumulated during N?1 periods of the intermediate signal and makes a correction of the intermediate signal every N periods of the intermediate signal as a function of the accumulated phase error such that the loop becomes stable.

Abstract: The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.

Abstract: Disclosed herein is a method and apparatus used to create an idealized voltage controlled oscillator (VCO) which allows very high modulation rates without the expected phase noise (jitter) which nominally comes from wide bandwidth VCOs. In this fashion, high quality VCOs that typically offer pure signals at the cost of small tuning bandwidths can be enhanced to create idealized VCOs that offer both high quality (low jitter) and high tuning bandwidths. A high-frequency phase modulator and control voltage processing is used in conjunction with a natural VCO to create a method and apparatus in accordance with the invention. The control voltage processing includes separation of frequency components of the controlling voltage and electrical integration of high-frequency control voltage components directed to the phase modulator to create the overall voltage-to-frequency transfer function for the ideal VCO.

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector circuit configured to detect an error of an output clock signal in relation to a reference clock signal and to generate a charge pump control signal therefrom and a charge pump circuit configured to charge and discharge an output node thereof responsive to the charge pump control signal. The PLL further includes a current-mode loop filter circuit coupled to the output node of the charge pump circuit and configured to generate a filtered current from the current at the output node of the charge pump circuit, and a current-controlled oscillator configured to generate the output clock signal responsive to the filtered current. The current-mode loop filter circuit may be self-biased. For example, the current-mode loop filter circuit and the charge pump may be biased responsive to a common bias control signal generated by the current-mode loop filter circuit.

Abstract: An automatic quadrature phase compensation system comprises an on-chip analog phase sense circuit capable of detecting small differences in quadrature phase error and providing a corresponding DC voltage, a voltage-controlled or programmable phase delay circuit to implement quadrature phase error correction, and a feedback system or compensation engine used to process the sensed error voltage and apply a corresponding correction signal to the adjustable phase delay.

Abstract: A timer circuit that has a normal mode and a test mode is disclosed. The test mode includes a power-up phase and a power-down phase. The timer circuit includes an oscillator and a first timer circuit portion coupled to the oscillator. The first timer circuit portion includes an input and an output. An output signal that confirms either the satisfactory or unsatisfactory operation of the first timer circuit portion is taken from the output associated with the first timer circuit portion in the power-up phase. The timer circuit further includes a second timer circuit portion coupled to the first timer circuit portion and the oscillator. The second timer circuit portion also includes an input and an output. An output signal that confirms either the satisfactory or unsatisfactory operation of the second timer circuit portion is taken from the output associated with the second timer circuit portion in the power-down phase.

Abstract: An amplifier circuit for an oscillator in a defined oscillating frequency range includes a plurality of transconductors, wherein at least one transconductor has a positive transconductance, and wherein at least one other transconductor has a negative transconductance, wherein the transconductors together provide a positive amplification, and a passive impedance element coupled to at least one fed back transconductor, wherein the transconductance of the transconductor and the impedance element are dimensioned so that, in the oscillating frequency range, a given phase difference is present between a signal at the input and a signal at the output.

Abstract: Improved voltage controlled oscillator (VCO) circuits are disclosed. A symmetrical voltage controlled oscillator (VCO) system according to the embodiments of the present invention comprises a frequency tuning circuit containing one or more varactors for receiving a predetermined tuning signal and a frequency tuning bias signal for altering capacitances of the varactors, a modulation circuit coupled in parallel with the frequency tuning circuit containing one or more varactors for modulating one or more outputs, and a core circuit coupled in a parallel with the tuning circuit and the modulation circuit for providing an oscillation mechanism, wherein the core circuit has an inductance module coupled in a parallel fashion with the frequency tuning circuit and the modulation circuit, wherein circuit elements of the VCO system are symmetrically arranged for increasing oscillation efficiency thereof and the varactors are tuned to deliver the output at an output frequency.

Abstract: A noise tolerant voltage controlled oscillator is described. The voltage controlled oscillator include a varactor element as part of an LC tank circuit. The varactor element is biased by a bias signal and a bias-dependent control signal. The bias-dependent control signal tunes the LC tank circuit. Because the control signal is bias-dependent, noise and other deleterious influences do not cause the varactor element to deviate in capacitance. Instead, the bias-dependent control signal is a tuning signal that is centered around the bias signal, which allows the varactor element to provide a constant capacitance in the event of a varying bias signal.

Abstract: For use in a multi-band wireless communication system, a local oscillator includes a voltage-controlled oscillator that generates an oscillating signal in response to a control signal. A local oscillating signal generator includes buffers and frequency dividers for generating from the oscillating signal a plurality of frequency signals having different frequencies. A switching circuit selects one of the frequency signals, and a phase locked loop generates the control signal from the selected frequency signal.

Abstract: A switch arrangement comprises a plurality of MEMS switches arranged on a substrate about a central point, each MEMS switch being disposed on a common imaginary circle centered on the central point. Additionally, and each MEMS switch is preferably spaced equidistantly along the circumference of the imaginary circle. Connections are provided for connecting a RF port of each one of the MEMS switches with the central point.

Abstract: A coupling device in FIG. 3 consisting of upper and lower connecting plates 100 and 101 with external flanges parallel to transmission line (103) for coupling RF energy for forward power detection. The coupling device (100) incorporates a helix structure with rotation centered near or about transmission line 103 and incorporates embedded secondary structures which are parallel to transmission line and fixed a predetermined distance from the transmission line (103). Theses plurality of parallel flanges are used to increase the coupling coefficient and directivity of the helix coupler (107) and maintain geometries that optimize magnetic field coupling. One or more vias (102) are used to connect individual upper connecting plate (100) and individual lower connecting plate (101) to form the overall helix structure. The addition of the parallel flanges to upper and lower connecting plates allow for a greater coupling efficiency per unit length of transmission line 103.

Abstract: The duplexer includes a transmit filter connected between an antenna terminal and a transmit terminal, and a splitter circuit and a receive filter connected in series between the antenna terminal and the receive terminal. The splitter circuit includes at least one phaseline connected between the antenna terminal and the receive filter and at least one resonator connected in parallel with the phaseline. According to the present invention, the length of the phaseline can be made shorter, so the entire duplexer can be made more compact in size. In addition, an inductors are preferably connected between each ends of the phaseline and the resonator. In this case, the inductance of a wire or via formed within the package can be used.

Abstract: In a surface acoustic wave device according to the present invention, a transmitting filter element TX and a receiving filter element RX are formed on one main surface of a piezoelectric substrate 300, and are mounted by face down on an upper surface of a circuit board 200. A ground electrode 322 in the receiving filter element RX is connected to three linear via conductors 221? formed on the circuit board 200, and a ground electrode 312 in the transmitting filter element TX is connected to a crank-shaped via conductor 211? formed on the circuit board 200.

Abstract: A waveguide filter with a signal input port at a first end and a signal output port at a second end includes a dielectric core of moldable material where the outer surface of its periphery has a metal layer with nonmetallized openings positioned at opposite ends of the filter to accommodate the input and output ports. The filter's periphery is configured to provide a cascade connection of a plurality of metal-bounded ridge-waveguide sections with interspersed metal-bounded evanescent-mode coupling regions. The filter can be joined through a manifold to realize a frequency-multiplexer, with the manifold containing a cascade connection of electrically short waveguide segments and quasi-lumped waveguide circuit components, such as irises. The filter and multiplexer are amenable to the application of cost-effective injection molding techniques to manufacture the dielectric core.

Abstract: A panel antenna having a variable phase shifter module with at least one main-PCB having an input trace coupled to a wiper junction. An arcuate trace on the main-PCB extending between a first output trace and a second output trace, the arcuate trace having an arc center proximate the wiper junction. A wiper-PCB having a linking trace thereon; the wiper-PCB rotatably coupled to the main-PCB proximate the wiper junction with the linking trace facing the first main-PCB. Because the linking trace faces the main-PCB, the wiper-PCB may be formed from inexpensive and structurally resilient substrate material. The linking trace coupling the wiper junction with the arcuate trace. Multiple arcuate traces may be linked to further output traces to add additional outputs, each having variable phase shift between them, depending upon the position of the wiper-PCB. Multiple main-PCBs may be stacked upon each other and the wiper-PCBs of each controlled by a common linkage.

Abstract: High-speed interconnect systems for connecting two or more electrical elements are provided. Interconnect system has the means, which could reduce the microwave loss induced due to the dielectrics. Reducing the effective loss tangent of the dielectrics reduces the microwave loss. With optimize design of the interconnects, the speed of the electrical signal can be made to closer to the speed of the light. The interconnect systems consists of the electrical signal line, inhomogeneous dielectric systems and the ground line, wherein inhomogeneous dielectric system consisting of the opened-trenches into the dielectric substrate or comb-shaped dielectrics to reduce the microwave loss. Alternatively dielectric structure can have the structure based on the fully electronic or electromagnetic crystal or quasi crystal with the line defect. Alternatively, dielectric structure can be made to comb-shaped structure with teethes having thickness and space making the air pocket to reduce the microwave loss.