Abstract: An integral electronic revenue meter system diagnostics package including a microprocessor, storage memory, preselect series of system diagnostic tests, and recording any results which exceed predefined programmable thresholds, and display means for displaying error and/or diagnostic messages identifying selected diagnostic data and/or errors discovered in the meter tests during a predefined period is included as part of an electricity revenue meter of the type used for collecting metering data for a utility which uses such data for billing purposes. The system automatically senses the type of electrical service in which the revenue meter is installed when the revenue meter is installed in a socket at the customer's premises.

Abstract: An electrical test lead includes an insulated electrical cable having a proximal end and a distal end, an electrical connector disposed at the proximal end of the cable and connected to a test instrument, and an electrically conductive magnetic probe disposed at the distal end. The probe is adapted to magnetically attach to a test point in an electrical system and to provide an electrical connection from the test point through the probe, the cable and the connector to the test instrument. Together, the test lead and the test instrument may be used as an electrical test kit. The test lead may further include an additional electrical test lead component magnetically attached, and electrically connected, to the electrically conductive magnetic probe and extending therefrom. An additional electrically conductive magnetic probe or a non-magnetic electrical connector may be disposed at the distal end of the additional electrical test lead component.

Abstract: There is described an inductive position sensor in which a signal generator applies a excitation signal to an excitation winding formed on a first member, the excitation winding being electromagnetically coupled to at least two resonant circuits formed on a second member which are spaced from each other along a measurement path. The excitation windings are shaped so that the electromagnetic coupling between the exciting winding and each of the resonators varies along the measurement path. In this way, by applying an excitation signal to the excitation winding, respective different signals are induced in the resonators which depend upon the relative position of the first and second members.

Abstract: In a stator structure for a rotation detector according to the present invention, a stator body is formed by rotating a plurality of annular stator pieces by a predetermined angle for each stator piece and laminating them, and a resin-molded frame body having a mounting ear is disposed on an outer periphery of the stator body, such that the stator body can be mounted in other equipment or the like by using the mounting ear.

Abstract: A system for directly measuring a magnetostriction value of a magnetoresistive element includes a fixture for receiving a substrate carrying one or more magnetoresistive elements. A magnet assembly applies a first magnetic field parallel to the substrate, and a magnetic alternating field perpendicular to the substrate and parallel to magnetoresistive layers of the elements. A stress-inducing mechanism applies a mechanical stress to the substrate, the stress being oriented parallel to the substrate. A measuring subsystem measures a signal from at least one of the magnetoresistive elements.

Abstract: A three-dimensional magnetic bearing sensor 10a includes a first sensor 101, a second sensor 102, and a third sensor 103 each constituted by a magneto-impedance sensor element 10 comprising a magnetic sensitive member 2 having a characteristic changed responsive to an external magnetic field, an insulator 4 formed to allow penetration of the magnetic sensitive member 2 therethrough, and an electromagnetic coil 3 made up of foil-like conductive patterns 31, 32 arranged in adjacent relation on an outer surface of the insulator 4. The first sensor 101, the second sensor 102, and the third sensor 103 are disposed such that directions in which the magnetic sensitive members 2 in respective sensors have maximum magnetic field detection sensitivities are substantially orthogonal to each other.

Abstract: A flexible fluxgate including: at least two ferromagnetic or ferrimagnetic, flexible cores; at least two sets of a plurality of windings of an electrically conductive material, at least one set of windings being wound around each of the cores; and an electrically conductive, flexible shield enclosing the cores and the windings. The fluxgate may have a considerable length, e.g. several hundreds of meters, and can be arranged in an open loop. The fluxgate may be used in an access control system. Various fluxgate magnetometers are disclosed as well.

Abstract: A method and apparatus for obtaining a parameter of interest relating to a region proximate a nuclear magnetic resonance (NMR) logging tool suitable for subterranean well logging is disclosed. The nuclei of the region are subjected to a pulsed NMR technique and are productive of NMR logging data, the nuclei of the region characteristically having a longitudinal relaxation time T1 distribution and an apparent transverse relaxation time T2app distribution. In response to the NMR logging data, an R distribution is defined as R=T1/T2app, the T2app and R distributions are processed as separate bins, along with the NMR logging data, according to a two-dimensional inversion model, and a signal intensity map of R versus T2app is provided that is representative of the parameter of interest relating to the region. In response to a high-intensity signal on the map being within a first range of T2app values and a first range of R values, the presence of a light hydrocarbon within the region is identified.

Abstract: In a magnetic resonance imaging method an echo train is generated of successive magnetic resonance signals from an object to be examined. The magnetic resonance signals are received with a degree of undersampling and by means of a receiver antennae system having a spatial sensitivity profile and the degree of undersampling is set on the basis of an amount of phase evolution due to a magnetic susceptibility distribution of the object to be examined.

Abstract: Homodyne image reconstruction is combined with an iterative decomposition of water and fat from MR signals obtained from a partial k-space signal acquisition in order to maximize the resolution of calculated water and fat images. The method includes asymmetrical acquisition of under-sampled MRI data, obtaining low resolution images, and then estimating a magnetic field map and phase maps of water and fat image signals from the low resolution images. The acquired data is again filtered and Fourier transformed to obtain an estimate of combined fat and water signals using the estimated magnetic field map and phase maps. Water and fat images are then estimated from which phases of the water and fat images are determined. The real parts of the water and fat images are then used in calculating water and fat images using a homodyne process.

Abstract: A radiofrequency (RF) resonator for magnetic resonance analysis, the RF resonator comprising: (a) at least two conductive elements, each having a first curvature along a direction perpendicular to a longitudinal axis, the at least two conductive elements being spaced along the longitudinal axis, so that when an RF current flows within the at least two conductive elements in a direction of the longitudinal axis, a substantially homogeneous RF magnetic field, directed perpendicular to the longitudinal axis, is produced in a volume defined between the at least two conductive elements.

Abstract: A method of pre-scan data acquisition includes the application of a pre-scan pulse sequence to acquire MR signals from a region-of-interest to be imaged with an imaging pulse sequence. The pre-scan pulse sequence applies a pre-scan readout gradient pulse and a pre-scan readout gradient rewinder pulse. MR signals are acquired from a region of interest during application of the pre-scan readout gradient pulse and after application of the pre-scan readout gradient rewinder pulse.

Abstract: Body (22) for measuring the resistivity of a formation (9) surrounding a well (10) equipped with a lining (11), comprising: a body (23) of a probe (22), a set of three primary voltage measurement electrodes (ea, eb, ec), an upper electrode (ea) and a lower electrode (ec) and a central electrode (eb), two electrodes (In1, In2), an upper current injection electrode (In1) and a lower current injection electrode (In2) arranged on each side of the set of primary electrodes, characterized in that it also comprises, two secondary voltage measurement electrodes (24, 26) arranged on each side of the set of primary electrodes (ea, eb, ec), and between the two current injection electrodes (In1, In2), the spacing between a secondary electrode (24, 26) and the closest primary end electrode (ea, ec) being more than 1.5 times the spacing between the primary electrodes (ea, eb, ec).

Abstract: A relay controller for connecting a power source includes at least one relay having at least two contacts. The relay controller includes a processing device operable to selectively switch the relay contacts, and a feedback circuit adapted to identify an actual state of the relay contacts. The processing device is configured to recognize a fault contact condition of a disparity between an expected state of the relay contacts and the actual state of the relay contacts. The processing device is also configured to responsively communicate information relating to the relay fault condition.

Abstract: A method to locate a fault from one end of a section of a power line utilizing measurements of current, voltage and angles between the phases at a first end of said section. Symmetrical components of currents are calculated for the current and voltage measurement at the first end. A value of impedance is calculated for an extra link between the terminals with the impedance for the positive sequence. A compensation is determined for the shunt capacitance. The zero-sequence current is determined from the healthy line of a section of parallel power lines. A distance to a fault is calculated for the parallel line section. The distance to the fault from the first end is calculated. The fault is located utilizing the calculate distances.

Abstract: Change in power supply voltage supplied to a device under test is controlled.

Abstract: Methods and apparatus for reducing the thermal noise integrated on a storage element are disclosed. One embodiment of the invention is directed to a sampling circuit comprising a sampling capacitor to store a charge, the sampling capacitor being exposed to an ambient temperature. The sampling circuit further comprises circuitry to sample the charge onto the capacitor, wherein thermal noise is also sampled onto the capacitor, and wherein the circuitry is constructed such that the power of the thermal noise sampled onto the capacitor is less than the product of the ambient temperature and Boltzmann's constant divided by a capacitance of the sampling capacitor. Another embodiment of the invention is directed to a method of controlling thermal noise sampled onto a capacitor. The method comprises an act of independently controlling the spectral density of the thermal noise and/or the bandwidth of the thermal noise.

Abstract: A damage detection system includes a processor and a transmitter communicatively connected to the processor. The transmitter sends a signal to the processor and the processor is programmed to assign a spatial coordinate to the transmitter. The processor is further programmed to identify a transmitter location as damaged when the transmitter fails to send the signal. The damage detection system may analyze the damaged area and report potentially affected sub-systems to users of a machine or vehicle equipped with the damage detection system.

Abstract: An eccentric offset Kelvin probe with a beveled contact tip radially offset from the longitudinal axis of the probe which provides a reduced tip spacing between adjacent pairs of probes.

Abstract: A probe apparatus and a probe system are provided. The probe apparatus uses a larger printed circuit board to dispose a plurality of testers. The layout of each of the testers on the circuit board is modified accordingly, such that more number of the testers can be disposed on the circuit board and the pin count of the probe apparatus is increased. In addition, the probe apparatus can be installed in the test tool. Accordingly, the testing efficiency of the present test tool can be substantially promoted and the cost of the overall testing can be effectively reduced.

Abstract: A probing apparatus includes a mechanism apparatus. The mechanism apparatus includes a base body, a vibration absorber, a shifting mechanism, and a stage connected via the base body to a ground terminal. A probe, positioned over the stage, is connected to a measurement terminal of a measuring apparatus via a signal cable. The signal cable has a connecting terminal connected to the measurement terminal of the measuring apparatus. A shielding cover, positioned over a measured device on a glass substrate held on the stage, has an area not smaller than an area of the measured device and not greater than four times the area of the measured device. The shielding cover is grounded.

Abstract: A holding side contact arm (317) for holding an IC to be tested is positioned on the optical axis (OP) of an alignment CCD camera (326) of an alignment device (320), the IC to be tested is inserted to a first opening (321a) formed on an alignment movable portion (321), and a contact member (317d) of the holding side contact arm (317) is brought to contact the alignment movable portion (321). Then, an alignment amount for correcting a position of the IC to be tested is calculated by taking an image by the camera (326) and performing image processing. A lock-and-free means (318) provided to a first contact arm (315a1) is made to be in a non-restricted state, a movable portion driving device (322) is driven based on the alignment amount, and the holding side contact arm (317) contacting the alignment movable portion (321) is moved with respect to a root side contact arm (316), so that alignment of a position of the IC to be tested is performed.

Abstract: The disclosure is a device for applying a test voltage from the external of a memory device in a burn-in test mode. An internal voltage generator for a burn-in test is comprised of pad means receiving an external voltage, switching means turned on in the burn-in test mode, and an internal voltage generating means. An external voltage applied to the pad means during the burn-in test mode is transferred to the internal voltage generating means by way of the switching means.

Abstract: A network analyzing apparatus that analyzes the network properties of a device under test by applying reference signals to a device under test by frequency sweeping or power sweeping comprises input device for inputting the sweep range and sweep interval of these reference signals as well as the center coordinates and radius of a test circle for testing this device under test; a measurement apparatus for measuring the network properties of this device under test and obtaining measurements for n number of measurement points determined from this sweep range and sweep interval; and a testing apparatus, with this testing apparatus finding the difference between this measurement and center coordinates and, referring to this difference and this radius, determining that this measurement that has been read passes the test if the magnitude of this referred difference is no greater than this referred radius, or is less than this referred radius.

Abstract: The trench leakage current of a deep trench isolation structure is measured. The deep trench isolation structure, which is filled with polysilicon, contacts both a first region of a first conductivity type and a second region of a second conductivity type, and is proximate to a third region of the first conductivity type formed in the second region. Test voltages are applied to the structures and the leakage current is measured.

Abstract: A gate capacitance of a MOS transistor is determined by (a) measuring the gate capacitance and dissipation factor; (b) obtaining a channel resistance and a tunneling resistance; (c) setting an initial capacitance and an error dissipation factor; (d) calculating a direct dissipation factor using the channel resistance, the tunneling resistance, and the initial capacitance; (e) calculating a calculated dissipation factor using the error dissipation factor, the direct dissipation factor, and the measured dissipation factor; (f) calculating a calculated capacitance using the channel resistance, the tunneling resistance, the initial capacitance, the error dissipation factor, and the measured dissipation factor; and (g) detecting the initial capacitance as an accurate gate capacitance of the transistor if it is determined that the calculated capacitance is equal to the measured capacitance and the calculated dissipation factor is equal to the measured dissipation factor, and otherwise repeating steps (c) through (g

Abstract: A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area.

Abstract: A test apparatus for testing switching speed of a circuit, which includes a pre-stage logic element outputting a first or second level voltage and a post-stage logic element to which the output signal of the pre-stage logic element is input, is provided, wherein the post-stage logic element includes the post-stage FET, a gate terminal of which the output signal is input to, for outputting a different level of voltage according to the case that the output signal voltage is higher or lower than a predetermined threshold voltage, and the test apparatus includes a threshold voltage setting unit for setting a threshold voltage of a post-stage field effect transistor (FET) to be different from that in a normal operation by setting a substrate voltage of the post-stage FET to have a value different from that in the normal operation of the circuit; a delay time measuring unit for measuring a delay time of the circuit to which the threshold voltage different from that in the normal operation is set; and an error detec

Abstract: A TFT array inspection device inspects a TFT array substrate having thin film transistors arranged in a matrix pattern. The TFT array inspection device includes a probe frame to be electrically connected to the TFT array substrate. The probe frame includes probe pins contacting array inspection electrodes to be connected to a driving electrode terminal provided in a TFT array on the TFT array substrate through wires. The probe pins are positioned at common locations relative to a layout of the TFT array substrate. Since the probe pins are located at common positions, it is possible to use a single common probe frame for the TFT array substrate with a different layout without providing or changing a prove frame corresponding to a different layout of the TFT array substrate.

Abstract: The system for display test includes a driving circuit having integrated circuit (IC) pads on the substrate and the IC pads are electrically connected to the signal lines, respectively. And the first switches are between the first test pads and the IC pads, wherein the number of the first test pads is less than the number of the IC pads.

Abstract: Pixel units are disposed in a display region of a substrate, and scan lines and data lines are used to control the pixel units. Inner short ring includes a first segment, a second segment and a connecting segment connecting both segments. The gates and sources of the first and second active device connect with the first and second segments respectively, and the drains connect with the connecting segment. The gates and sources of part of the third active devices connect with the first segment, and the drains connect with the odd scan lines. The gates and sources of other third active devices connect with the second segment, and the drains connect with the even scan lines. The gates of the fourth active devices connect with connecting lines, and the sources connect with data testing lines, and the drains connect with the odd and even data lines respectively.

Abstract: A loading device for conducting a loading test of an objective power source to be tested comprises a rectifier connected to the objective power source to be tested and a resistor connected to the rectifier, the resistor including a retention tank for collecting electrolyte aqueous solution and an electrode member soaked in the electrolyte aqueous solution, a positive electrode of direct current from the rectifier being connected to the retention tank, and a negative electrode of the direct current being connected to the electrode member, and a hydrogen collecting member forming a first space shielded from air being disposed upward in a periphery of the electrode member.

Abstract: A system for detecting a fault in a power supply having at least one power supply unit and a redundant power supply unit. The system includes a printed circuit board and a common voltage bus disposed on the printed circuit board. A plurality of diodes is disposed on the printed circuit board having first electrodes connected to the common voltage supply bus. The diodes have second electrodes connected to a corresponding one of the at least one power supply unit and the redundant power supply unit. The diodes are connected to the common bus in a logic OR configuration. A controller, disposed on the printed circuit board, is fed by a voltage at the second electrode of a corresponding one of the diodes and a reference voltage for determining whether the voltage at the second electrode of the corresponding one of the diodes is producing a predetermined voltage relative to the reference voltage.

Abstract: A method and apparatus to reduce the probability of programmable logic device (PLD) failure due to single event upset (SEU) of configuration memory. A first portion of configuration memory cells are initially programmed with configuration data, leaving a second portion of configuration memory cells that are un-programmed. The programmed and un-programmed configuration memory cells are grouped into voting groups, where each un-programmed configuration memory cell of each voting group is programmed with the identical configuration data as contained within the originally programmed configuration memory cell of each voting group. The logic values of each configuration memory cell of each voting group are monitored by voting circuits, which enforce a triple modular redundancy (TMR) validation policy. The logical validation results are then applied to control points to mitigate PLD configuration memory errors caused by anomalous events such as neutron induced SEUs.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.

Abstract: An array of logic gates is configured to implement a predefined strategy for an emergency response system in a hardware-only runtime environment. The array of logic gates receives a plurality of input signals from a set of sensors and actuators located within an industrial processing system. Based upon the received plurality of input signals, the array of logic gates determines an emergency response using the predefined strategy. The array of logic gates implements the emergency response to control the industrial processing system based upon the predefined strategy. The array of logic gates can be reconfigured based upon a change in the predefined strategy.

Abstract: A layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit design of especial utility with respect to integrated circuit devices. The logic gate design disclosed herein utilizes fewer transistors than traditional static designs and, therefore, requires a smaller amount of integrated circuit layout area while nevertheless affording higher speed operating performance than that exhibited in existing conventional circuits.

Abstract: A transmitter circuit including: a current driver which current-drives differential signal lines; and a voltage driver which is electrically disconnected from at least one of the differential signal lines in a normal transfer mode, and is electrically connected to the at least one of the differential signal lines and voltage-drives the at least one of the differential signal lines in a power-down mode. The voltage driver outputs a power-down voltage for setting a receiver circuit to the power-down mode or a wakeup voltage for canceling the power-down mode of the receiver circuit, to the at least one of the differential signal lines. The current driver transmits a power-down command to the receiver circuit by current-driving the differential signal lines in the normal transfer mode.

Abstract: A small computer system interface (SCSI) driver circuit having a programmable slew rate comprises N cascaded delay cells each including a data bit input, a delayed data bit output that communicates with the data bit input of an adjacent one of the N cascaded delay cells, and a delay time input that receives a programmable delay time value for setting a variable delay between receiving data at the data bit input and generating the delayed data bit output. N predrivers receive an output enable signal and a corresponding one of the N delayed data bit outputs and generate a predriver output signal based on the output enable and the corresponding one of the N delayed data bit outputs. N drivers have inputs that receive predriver output signals from corresponding ones of the N predrivers. An output port communicates with outputs of the N drivers.

Abstract: A circuit comprises an output terminal, an output driver for providing an output signal at the output terminal, a switching device for producing one or more connections of the output terminal to a respective fixed or variable potential, and a control device for controlling the switching device, the control device being designed to produce the connection or the connections in the event of a transition in the output signal from a first logic level to a second logic level and to disconnect it at the latest when the output signal attains the second level.

Abstract: An integrated circuit programmable multiplexer that reduces sub-threshold leakage current in deep sub-micron technology. The multiplexer uses a plurality of transistor stages, wherein each transistor of a subsequent stage is connected to at least two transistors of a prior stage, such that each transistor is in series with at least one other transistor. Transistors that are not part of the signal path through the multiplexer are deactivated, wherein a series of two or more deactivated transistors have significantly less sub-threshold leakage current than a single deactivated transistor. Configuration memory cells that store and communicate control signals to the multiplexer transistors are also connected to a low-voltage power supply when the multiplexer is not in use to reduce leakage current through the memory cells.

Abstract: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

Abstract: A method and apparatus for determining the size of a keeper transistor in a dynamic circuit is provided. A first portion of a dynamic circuit, comprising the keeper transistor, is analyzed to determine keeper current data that describes what size the keeper transistor would need to be to supply a specified amount of keeper current. A second portion of the dynamic circuit is analyzed, separate from the first portion, to determine an estimated amount of leakage current that passes through the PDN when the PDN is not actively discharging the dynamic node may be determined. The size for the keeper transistor that enables the keeper transistor, when activated, to produce an amount of keeper current that is substantially equal to the estimated amount of leakage current may be determined based on the analysis performed on the first and second portion.

Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Abstract: A digital clock switching circuit and method is disclosed and is operable to deadlock-free switch a digital clock source for an integrated circuit. The circuit includes a first finite state machine associated with a first clock source and a second finite state machine associated with a second clock source. The finite state machines are connected to each other and monitor the current state of the other finite state machine. Each finite state machine receives an input select signal to control which clock source should be active and passed to a clock output. Each finite state machine includes a counter, wherein the counter associated with the active clock source is initialized to a first predetermined value when the input select signal indicates a switching off of the active clock source. The finite state machine associated with the active clock source enters a CHECK state and varies a count at each clock cycle.

Abstract: A latch type sense amplifier includes a latch unit, an amplifying unit and a circuit module for charging or discharging the latch unit. The latch unit is configured by two sets of serially coupled PMOS and NMOS transistors, whose gates and drains are cross-coupled. The amplifying unit is coupled between the latch unit and a complementary power supply for controlling the latch unit in response to a bit line signal and a complementary bit line signal. The circuit module is designed to charge or discharge the data storage node and the complementary data storage node of the latch unit in response to the bit line signal and the complementary bit line signal, without using a current path across the NMOS transistors therein, such that the data storage node and the complementary data storage node are charged or discharged in a manner insensitive to a mismatch between the two NMOS transistors.

Abstract: A power supply monitoring circuit that monitors and delivers the highest voltage power supply to an IC system includes a voltage comparator that receives two different power supply voltages, and outputs a first signal to the gate of a first switching transistor connected between a first power supply and an system power supply output node. The comparator output is also input to an inverter, the output of which comprises a second signal connected to the gate of a second switching transistor connected between a second power supply and the system power supply output node. When the first supply voltage exceeds the second supply voltage, the first transistor is switched on to connect the first supply to the system output node, and the second transistor is switched off; and vice versa. The comparator includes designed-in hysteresis to prevent simultaneous switching of the two transistors.

Abstract: A comparator circuit with reduced current consumption, and other circuits utilizing the same, are provided. The comparator circuit may achieve reduced current consumption by preventing current flow via a switching transistors responsive to the voltage level of the input signal.

Abstract: Embodiments of the present invention include circuits and methods for dividing high frequency signals. In one embodiment the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential outputs, wherein the differential circuit has a first bias current. The divider circuit further includes a cross-coupled circuit having outputs coupled to the differential circuit outputs and a second frequency control input, wherein the cross-coupled circuit has a second bias current. Embodiments of the present invention may include circuits for controlling the relationship between bias currents and circuit parameters that vary with process or temperature or both.

Abstract: A frequency divider circuit is disclosed with at least one push-pull divider with adjustable division ratio and a connected converter device. The circuit converts a clock signal delivered by a push-pull divider into a single-ended signal. A first and a second single-ended divider are connected to the output of the converter device, and a feedback path is provided, which is connected to the output of the push-pull divider and to the outputs of the first and of the at least one second single-ended divider, and which includes an evaluation circuit. This circuit has first and second inputs which are connected to the first and second single-ended dividers in such a way that a future state of the clock signal delivered by the single-ended divider in question can be supplied to the inputs of the evaluation circuit. The evaluation circuit evaluates states of the clock signals delivered by the first and second single-ended dividers, i.e.