Abstract: A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state.

Abstract: A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the sense transistor. Addressing the second vertical MOS transistor provides a means for changing a potential of the floating body of the sense transistor. The vertical gain cell can be used in a memory array with a read data/bit line and a read data word line coupled to the sense transistor, and with a write data/bit line and a write data word line coupled to the second transistor of the vertical gain cell.

Abstract: A electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.

Abstract: A 1T1R resistive memory array comprised of chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such chains of memory cells are non-volatile and provide for each of the memory cells to be randomly accessed.

Abstract: An inexpensive, re-configurable storage circuit for programmable logic devices and application specific integrated circuits is disclosed. The storage circuit comprises: at least one output; and at least two inputs; and at least a one input and a two input response sequence, wherein the inputs change the output in a well defined response sequence; and a configuration circuit comprising one or more memory elements, wherein the memory bits are programmed to select one of said response sequences.

Abstract: A magnetic resistance memory includes an identity determining unit that compares, bit by bit, first data stored in an address specified by a write request with second data to be written to the address, and that determines whether bit-by-bit values of the first data and the second data are identical; and a writing control unit that halts, when a bit of the second data is identical with a corresponding bit of the first data, writing of the bit of the second data.

Abstract: A magnetoresistive memory element including a trapped magnetic region and a free magnetic region separated by a barrier layer. The free magnetic region comprises a stacking of at least two antiferromagnetically-coupled ferromagnetic layers, a layer magnetic moment vector being associated with each layer, the resulting magnetic moment vector, equal to the sum of the layer magnetic moment vectors, having an amplitude smaller than at least 40% of the amplitude of the layer magnetic moment vector of maximum amplitude. The anisotropy field and/or the demagnetizing field tensor is not identical for the at least two ferromagnetic layers, whereby the angular deviations of the layer magnetic moment vectors are different at the time of the application of an external magnetic field, which enables at least two methods for directly writing into the memory element, as well as its initialization.

Abstract: A magnetoresistance effect device includes a magnetized free layer formed of a ferromagnetic material, a magnetized fixing layer formed of a ferromagnetic material and having a crystal grain boundary, a nonmagnetic layer provided between the magnetized free layer and the magnetized fixing layer, and an antiferromagnetic layer provided on one surface of the magnetized fixing layer, which is opposed to a surface of the nonmagnetic layer. The magnetized fixing layer has an element which is segregated into the crystal grain boundary to prevent a material of the antiferromagnetic layer from diffusing.

Abstract: The present invention discloses a nano tube cell, and a semiconductor device having the nano tube cell and a double bit line sensing structure. The cell array circuit includes a plurality of top sub cell arrays, a plurality of bottom sub cell arrays, a main bit line sense amp and a word line driving unit. Especially, the top and bottom sub cell arrays have a double bit line sensing structure for inducing a sensing voltage of a main bit line by controlling a volume of a current supplied from a power voltage to the main bit line according to a sensing voltage of a sub bit line receiving a cell data. Each of the sub cell arrays includes a capacitor, and a PNPN nano tube cell having a PNPN diode switch selectively turned on/off according to a voltage difference between one side terminal of the capacitor and the sub bit line, to decrease a cell size and improve operational characteristics of the circuit.

Abstract: A programmable logic device (PLD) includes a non-volatile configuration memory. The non-volatile configuration memory is adapted to configure programmable resources (such as programmable logic and programmable interconnect) within the PLD. The non-volatile configuration memory may constitute a variety of memory types, for example, flash memory, erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), anti-fuse, and the like.

Abstract: The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line.

Abstract: The present invention provides a nonvolatile memory card in which a program is added, modified, changed, or the like by selecting arbitrary firmware on a flash memory from a plurality of pieces of firmware on flash memories. In a memory card, in addition to a program stored in a built-in ROM, firmware on flash memories as programs for adding, changing, modifying, or the like of a function such as a patch program are stored. Firmware on a flash memory which is desired to be made valid is set in a parameter sector or the like and is loaded into an external RAM, and the CPU of a control logic executes a process.

Abstract: A page buffer is provided for an electrically programmable memory that includes multiple memory cells forming multiple memory pages. The page buffer includes a register for at least temporarily storing data read from or to be written to the memory cells of a selected memory page. The register includes multiple latches and multiple buffer elements. Each of the latches is coupled to at least one signal line for transferring the data bit that is stored in the latch. Each of the buffer elements decouples an output of a corresponding one of the latches from the signal line, with the buffer element driving the signal line according to the data bit stored in the corresponding latch. Also provided is a method of transferring data from a register to signal lines in an electrically programmable memory.

Abstract: The drain programming window in virtual ground memory arrays may be enlarged by reducing the number of voltage drops in the cell access path. This reduction may be accomplished by reducing the number of transistors in the access path or by otherwise reducing the resistance in the access path.

Abstract: There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge injection speed does not depend on a threshold voltage. FIGS. 1A and 1B are views of a circuit structure for controlling the writing. In FIGS. 1A and 1B, an output of an operational amplifier 103 is connected to a control gate of a memory transistor 101, a constant current source 102 is connected to a drain electrode, and a source electrode is grounded. The constant current source 102 and a voltage Vpgm are respectively connected to two input terminals of the operational amplifier 103.

Abstract: In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.

Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract: A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation device electrically isolates the bit line from the sense amplifier, and, after the charge is transferred to the bit line, for causing the isolation device to electrically connect the bit line to the sense amplifier.

Abstract: An evaluation circuit includes a test circuit configured to provide a test voltage indicative of a characteristic of a semiconductor device, a reference circuit configured to provide a first reference voltage, a first delay circuit configured to convert the test voltage into a first delay, a second delay circuit configured to convert the first reference voltage into a second delay, and a first latching circuit configured to determine a relationship between the first delay and the second delay.

Abstract: A unit cell is composed of a memory cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the memory cell transistor. A memory cell block is composed of a plurality of unit cells connected in series. One end of the memory cell block is connected to a bit line via a block selecting transistor. The other end of the memory cell block is connected to a plate line. A redundancy unit cell is composed of a redundancy cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the redundancy cell transistor. A redundancy memory cell block is composed of a plurality of unit cells connected in series, the number of which is smaller than that of the unit cells in the memory cell block.

Abstract: To reduce the area relating to location of redundant elements for relieving defects of a memory. A memory device has row address and input/output data as two dimensional redundancy parameters for relieving defects of an embedded memory 30. It comprises a built-in self-test circuit 10 for testing defects of the embedded memory 30, a redundant element location operator 20 for determining which redundant element replaces a defect based on a preset order and according to the order in which defects are detected by the self-test circuit 10, and a row redundancy unit 31 and an I/O redundancy unit 32 for replacing the defects in the embedded memory according to the determined order. The redundant element location operator 20 determines the priority axis according to the preset order and according to the order in which the defects are detected, and holds redundant element location information.

Abstract: A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory cells connected by a pair of common bit-lines are written with opposite, or complementary, data, for example, logical “0” and logical “1”. Next, the two memory cells are subjected to a stress condition by pre-charging the common bit-lines connecting the two adjacent memory cells, and then simultaneously asserting the word-line of each memory cell. Finally, the data in each cell is read and compared with the data written to the cell prior to generating the stress condition.

Abstract: A bit line sense amplifier control circuit includes a driving signal generating unit adapted and configured to generate first through third driving signals in response to a bit line sense amplifier enable signal and an overdrive enable signal for setting an overdrive period, and to disable a first driving signal which is enabled for an overdrive period in response to a refresh signal which is enabled at a refresh mode, and a bit line sense amplifier control signal generating unit adapted and configured to generate first and second bit line sense amplifier control signals in response to the first through third driving signals. As a result, an overdrive pulse is not generated at a refresh mode to remove an overdriving period, thereby reducing current consumption at a refresh mode.

Abstract: Pseudo SRAM capable of arbitrating refresh requests with external access requests is provided. An access waiting circuit 20 for generating an access waiting signal /ECP in response to an external access request signal /CE or the like, an access activating circuit 21 for generating an access activating signal /AE in response to L level of the access waiting signal /ECP and H level of a busy signal /BUSY, a refresh waiting circuit 22 for generating a refresh waiting signal /REFP in response to a refresh request signal /REFT, and a refresh activating circuit 23 for generating a refresh activating signal /REFE in response to H level of the access waiting signal /ECP, L level of the refresh waiting signal /REFP, and H level of the busy signal /BUSY are provided. An array control circuit 12 performs an access operation in response to the access activating signal /AE, and performs the refresh operation in response to the refresh activating signal /REFE.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such as allowing the bit line to float allowing the bit line voltage to be established by balance of leakage currents to the minimum leakage through the bit line. Advantageously, a controller (22, 32) also controls voltages of supplies Vdd, Vss and the n-well (Vnwell) voltage. The controller reduces a voltage differential between the supply voltage Vdd and voltage Vss in the standby mode. In one embodiment, the bit line may be tied to the reference voltage Vss, and a time delay may be introduced to reduce the possibility of using more charge in switching than that saved.

Abstract: An internal power supply voltage generating circuit of semiconductor memory devices configured such that only a predetermined internal power driver is driven but the remaining internal power drivers are not driven, in a standby mode so that the leakage current in standby mode is reduced and the standby current is thus reduced. Furthermore, the leakage current of an internal power driver that does not operate in the standby mode is reduced using a high voltage as a back bias of the internal power driver.

Abstract: In an embodiment of the invention an integrated circuit includes a memory array having a first plurality of decoded lines traversing across the memory array and a pair of dual-mode decoders, each decoder coupled to each of the plurality of decoded lines a respective location along said decoded lines, such as at opposite ends thereof. Both decoder circuits receive like address information. Normally both decoder circuits operate in a forward decode mode to decode the address information and drive a selected one of the decoded lines. During a test mode, one decoder is enabled in a reverse decode mode while the other decoder remains in a forward decode mode to verify proper decode operation and integrity of the decoded lines between the decoders.

Abstract: Disclosed is an input data distribution device for a memory device, the input data distribution device comprising: a decoding section for receiving a starting column address applied when a write command is activated; and N number of switching sections each of which receives N bits of data applied sequentially through one data pin after the write command is activated, wherein each of the switching sections exclusively outputs one bit from among the N bits of data by using an output signal of the decoding section and a signal for determining a burst type.

Abstract: In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.

Abstract: A semiconductor memory module, which is formed as an FBDIMM memory module, for example, has a planar design. In the 2R×4 configuration, semiconductor components are arranged in two rows on a top side of a module board and semiconductor memory components are likewise arranged in two rows on an underside of the module board. In contrast to a “Stacked DRAM” design, the semiconductor components in accordance with the planar design contain only one memory chip. By using a parallel routing for a command address bus and an on-die termination bus, the address, clock, and control buses can be adapted in terms of load, so that different signal propagation times on the different buses are avoided to the greatest possible extent.

Abstract: A clock generator is provided that is compatible with both DDR1 and DDR2 applications. The internal YCLK signal is turned on only when an active read or write occurs on the integrated circuit memory, even though the main chip clock is always running. A circuit block within the clock generator detects when a read or write is active and initiates a YCLK signal on the next falling edge of the internal clock. Two separate mechanisms are used for determining when to terminate the YCLK. One mechanism is a timer path and the other is a path determined by DDR1 and DDR2 control signals. The timer path is strictly time based and is the same for DDR1 and DDR2 parts or modes of operation. The other signal path is different for DDR1 and DDR2 operating modes. A DDR1 control signal turns off YCLK at the next rising edge of the internal clock, and a DDR2 control signal turns off YCLK at the next falling edge of the internal clock.

Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.

Abstract: A self-contained data acquisition unit is provided for acquiring seismic data. The unit has a microprocessor and an antenna adapted to receive an electromagnetic signal. A decoder is connected with the microprocessor and adapted to convert received electromagnetic signals to dual-tone multiple-frequency (“DTMF”) digits. A geophone interface is provided with a geophone for collecting acoustic data incident on the geophone. A memory is connected with the geophone interface for storing a representation of the collected acoustic data and for storing a representation of a reference electromagnetic signal to be used in synchronizing acoustic data collected by other data acquisition units. A battery power source is connected with the microprocessor.

Abstract: A seismic streamer includes a jacket covering an exterior of the streamer. At least one strength member extends along the length of and is disposed inside the jacket. At least one seismic sensor is disposed in a sensor spacer mounted to the at least one strength member. The streamer includes means for retaining the at least one sensor spacer to the at least one strength member. The means for retaining provides substantial acoustic isolation between the at least one spacer and the at least one strength member.

Abstract: A time attendance system, including a time attendance clock, designed to be used in harsh conditions, such as outdoor job sites. A portable touch button, including a passively readable code, is brought into contact with the time attendance clock so as to create a time attendance record stored in the clock. Visual indicators and audible notification alert the employee of the acceptance of the act. Periodically, the time attendance records are retrieved from the time attendance clock, such as by using a hand-held electronic device which communicates in a wireless manner with the time attendance clock.

Abstract: A method and a device for adjusting control parameters of a servo system of an optical disk drive. A first sinusoidal signal is introduced into a control loop of the servo system, while a band-pass filter is used to extract a second sinusoidal signal. Gain and/or phase variations of the control loop are derived by comparing signal parameters of both the first and second sinusoidal signals. A compensator is then employed to adjust the derived gain and/or phase variations of the control loop so as to overcome the disadvantage of system instability after a long-term working.

Abstract: An optical pickup for recording and/or reproducing data with respect to a multilayer recording medium having a plurality of recording layers, where the optical pickup includes a light source emitting a beam having a predetermined wavelength, a diffraction unit separating the beam emitted from the light source into a main beam and a sub-beam, and a photodetector having a main photodetector detecting a main beam reflected from the multilayer recording medium and a sub-photodetector detecting the sub-beam. In the optical pickup, the main photodetector and sub-photodetector are separated a predetermined distance from each other so that a beam spot formed by the beam reflected from a defocus recording layer is not detected by the sub-photodetector.

Abstract: The optical pickup apparatus includes a light emitting means, an optical means, and an optical detection means. The light emitting means emits a single beam. The optical means diffracts the single beam, focuses the optical spot of the diffracted beam on a track, and transmits the diffracted beam to an outside. The optical detection means includes a first optical detection unit on which a central beam having a 0-order diffraction coefficient is focused, and second and third optical detection units on which side beams having ±1 diffraction coefficients are focused, respectively. Each optical detection unit is segmented into a specific number of optical detection areas, and at least one of the optical detection units is provided with an optical detection area on which a tracking error signal used to compensate for tracking offset attributable to optical axis offset of an objective lens is not formed.

Abstract: An optical disc drive is has a voice coil motor that carries and moves focal optics to focus a laser beam onto an optical disc The voice coil motor is responsive to input signals which are based on a calibrated temperature. A temperature measurement is made at the voice coil motor for an operating temperature, and a difference is calculated between calibrated and operating temperatures. The temperature differences are used to calculate adjustment in input signals used to drive the voice coil motors.

Abstract: A rotating recording device, such as an electron beam recorder, is provided with a dual encoder arrangement. A first encoder is employed as a spindle motor controller and located at a first end of a spindle. A second encoder is mounted at a turntable adjacent to a recording surface and used as a position, velocity or clock source for recording the pattern on the substrate. Eccentricity of the mounting of the second encoder is measured against the more accurately mounted spindle control encoder and compensated by a digital clock generating system using a digital phase locked loop.

Abstract: A write power determining method for an optical disk drive determines optimum write power information of an optical disk during the high-speed rotation of the disk. A push-pull signal amplitude is obtained at two positions in a radial direction of an optical disk before writing. A linearization value of optimum write power associated with radial positions over the whole writing area of the disk is determined on the basis of the obtained push-pull signal amplitude. The determined result is adopted as optimum write power information associated with the radial positions of the disk.

Abstract: An optical disc apparatus provided with an automatic power control circuit which controls power of laser light by obtaining a difference between a value detected by a front monitor 6 and a target value individually for reproduction power and for recording power includes: a detector 7 for detecting light reflected from an optical disc, a sample-hold circuit 26 which performs on an output of the detector 7 a sample-hold operation at the timing of the reproduction power; and a microcomputer 29 which computes a reference value from the reflected light of the reproduction power at the timing just before the start of a recording operation after receiving a recording command until opening of a recording gate, and at the time of recording operation an intensity of reflected light on which a sample-hold operation is performed is compared with the reference value to correct a target value of the reproduction power.

Abstract: An optical disk drive includes drive current generation unit for supplying a mark forming semiconductor laser drive current and a space forming semiconductor laser drive current; first high-frequency superimposition unit for superimposing a high-frequency component on the space forming semiconductor laser drive current; and high-frequency superimposition control unit for controlling the first high-frequency superimposition unit to stop the superimposition of the high-frequency component for a predetermined duration prior to a timing at which to switch from the space forming semiconductor laser drive current to the mark forming semiconductor laser drive current, eliminating positional variations on the disk of the mark leading and trailing edges due to the high frequency superimposition.

Abstract: It is an object of the present invention to provide an information recording method for recording information in a data rewritable type optical recording medium having a plurality of information recording layers, which can form recording marks having good shapes. In the information recording method according to the present invention, information is recorded in an optical recording medium 10 having at least a stacked L0 layer 20 and L1 layer 30 by projecting a laser beam whose power is modulated thereonto via a light incidence plane 13a. When information is recorded, ?/NA is set to be equal to or shorter than 700 nm, where ? is the wavelength of the laser beam and NA is the numerical aperture of an objective lens for converging the laser beam, and a pulse width Ttop0 of a top pulse of the laser beam when information is to be recorded in the L0 layer 20 is set to be shorter than a pulse width Ttop1 of a top pulse of the laser beam when information is to be recorded in the L1 layer 30.

Abstract: An optical information recording/reproducing apparatus is provided that condenses a light flux from a light source on an optical recording medium and effects recording/reproduction and comprises a light source; an objective lens; a spherical aberration generating mechanism; a sensor for receiving light reflected by an optical recording medium and converting the light into an electric signal; an equalization filter for effecting waveform equalization of an output from the sensor in accordance with a predetermined partial response characteristic; a quality evaluating circuit for measuring reproduction quality of an output signal from the equalization filter; and an adaptive equalization circuit for sequentially updating a coefficient for the equalization filter, wherein while the update of the coefficient for the equalization filter by the adaptive equalization circuit is stopped, the spherical aberration generating mechanism is driven on the basis of the reproduction quality measured by the quality evaluating

Abstract: Disclosed is a disk-like recording medium, a disk recording apparatus and a disk recording method, and a disk playback apparatus and a disk playback method. Disk ID is recorded over a circle of a burst cutting area on an optical disk. The circle is divided into n blocks, each of the blocks is divided into m frames, and ID information is recorded in each of the frames with k channel bits.

Abstract: The present invention comprises an apparatus and method for recording information on a multi-layer diffractive optics memory to extend storage capacity. A composite mirror device comprises a plurality of sets of mirror elements. Each one of the mirror elements of the sets is configured to direct a reference beam to a point of the multi-layer memory at one of a plurality of angles. A plurality of planes is associated with the plurality of sets. There is one plane per set, each plane being defined for each of the sets of mirror elements so that the paths formed from the mirror elements of the set to the point lie in the plane. Each of the planes is separated from its neighbor by an angle selected to avoid crosstalk.

Abstract: An optical pickup in an optical disk reproducing device is operable to switch operations between a low-power operation mode and a high-power operation mode, and includes a liquid crystal element and a polarization beam splitter, which together attenuate, only in the low-power operation mode, a laser beam emitted by a laser diode onto an optical disk. The liquid crystal element is turned ON only in the low-power operation mode to serve as a polarization rotating element. Working with the polarization beam splitter, the polarization rotating element attenuates a polarized component of the incident light on the optical disk.