Abstract: An organic semiconductor device including: a substrate having a first thermal expansion coefficient; and an organic semiconductor material coupled to the substrate at an interface therebetween. The organic semiconductor material includes a polymer organic semiconductor material and/or an oligomer organic semiconductor material. The organic semiconductor material also has a second thermal expansion coefficient that is different from the first thermal expansion coefficient, such that a mechanical stress is transferred from the substrate to the organic semiconductor material through the interface. This mechanical stress is related to the difference between the first and second thermal expansion coefficients and the change in temperature of the organic semiconductor device.

Abstract: Novel ruthenium, rhodium, palladium, osmium, iridium or platinum complexes of thianthrene ligands are electroluminescent compounds. According to the invention there is provided complexes of Formula (I).

Abstract: Provided is a multicolor organic EL display having plural organic EL devices arranged on a substrate. The multicolor organic light-emitting device includes a substrate; plural organic light-emitting elements provided on the substrate, including a first organic light-emitting element of first emission color and a second organic light-emitting element of second emission color different from the first emission color, wherein the first organic light-emitting element has a first electrode of a first material, an organic compound layer including at least a light-emitting layer, and a light transmissive, second electrode, provided sequentially in the mentioned order from the substrate side, and wherein the second organic light-emitting element has a first electrode of a second material different in reflectance or phase shift from the first material, an organic compound layer including at least a light-emitting layer, and the second electrode, sequentially provided in the mentioned order from the substrate side.

Abstract: A zinc oxide (ZnO) thin film transistor (TFT) and method of forming the same are provided. The ZnO may include a ZnO semiconductor channel, a conductive ZnO gate forming an electric field around the ZnO semiconductor channel, an ZnO gate insulator interposed between the conductive ZnO gate and the ZnO semiconductor channel and an insulating ZnO passivation layer on the ZnO semiconductor channel, the conductive ZnO gate and the ZnO gate insulator to protect the ZnO semiconductor channel, the conductive ZnO gate, and the ZnO gate insulator. A thin film transistor (TFT) may be formed by forming a semiconductor channel, forming a conductive gate having an electric field around the semiconductor channel, forming a gate insulator between the conductive gate and the semiconductor channel, and forming an insulating passivation layer on the semiconductor channel, the conductive gate and the gate insulator.

Abstract: A charge pump includes a current source/sink unit that charges/discharges an output node in response to an UP/DOWN signal generated by a PFD (phase frequency detector). The charge pump also includes a pull-down/pull-up unit configured to discharge/charge a cascode node within the current source/sink unit for a limited time period after the UP/DOWN signal reaches a threshold level during transition of the UP/DOWN signal for turning off the current source/sink unit.

Abstract: An IC testing device with conduction interface comprising an electrical circuit board having a test circuit; an insulation pad set on the circuit board; and a pressing block provided on the insulation pad for depressing the pins of the IC. While the conduction interface comprises a plurality of contactors provided in the insulation pad for electrically connecting with the pins of the IC and the electrical circuit on the circuit board. The insulation pad is also provided with an accommodation cavity in communication with outside and for accommodating the contactors. In addition, the conduction interface further comprises an elastic axle provided in the accommodation cavity whereas each of the contactors has a receptacle to hold the elastic axle; a conducting lead which is extended and protruded out of the insulation pad in contact with the pins of the IC; and a contact surface for electrically contacting with the electrical test circuit of the circuit board.

Abstract: Provided are a semiconductor device having a mesa-type active region including a plurality of slabs and a method of manufacturing the semiconductor device. The semiconductor device includes a first active region and a second active region. The first active region is formed in a line-and-space pattern on a substrate and includes the slabs, each slab having a first surface, a second surface facing a direction opposite to the first side, and a top surface. The first active region and the second active region are composed of identical or different materials. The second active region contacts at least one end of each of the slabs on the substrate to connect the slabs to one another The method includes forming a first active region in a line-and-space pattern on the substrate and forming the second active region.

Abstract: A TFT LCD array substrate and a manufacturing method thereof. The TFT LCD array substrate includes a substrate and a pixel array on the substrate. Each pixel has: a gate line and a gate electrode formed on the substrate; a gate insulating layer formed on the gate line and the gate electrode; a semiconductor layer formed on the gate insulating layer disposed on the gate electrode; an ohmic contact layer having two parts, which are disposed on two sides of the semiconductor layer respectively and are apart from one another; an isolation insulating dielectric layer covering the substrate and the gate insulating layer except a portion on which the semiconductor layer is formed; a pixel electrode formed on the isolation insulating dielectric layer and the ohmic contact layer over the semiconductor layer; a source/drain electrode formed on the pixel electrode over the ohmic contact layer, and a passivation layer at least covering the semiconductor layer.

Abstract: A TFT according to an embodiment of the present invention includes an insulative base film formed on a TFT array substrate, and a semiconductor film including a channel region formed on the base film, in which an impurity concentration of a channel region in the semiconductor film becomes substantially uniform in a film thickness direction of the semiconductor film, the impurity concentration of the channel region is discontinuous at a boundary between the semiconductor film and the base film, and an impurity concentration of the base film is lower than an impurity concentration of the semiconductor film and is monotonously decreased toward the TFT array substrate.

Abstract: A thin film transistor includes a semiconductor layer a source electrodes a drain electrode and a gate electrode. The semiconductor layer includes a plurality of grain boundaries disposed along a first direction. An acute angle between a gate electrode and a grain boundary prevents grain to boundaries from being formed at the boundary between a channel part and an ion doped part.

Abstract: The present invention relates to a diamond n-type semiconductor in which the amount of change in carrier concentration is fully reduced in a wide temperature range. The diamond n-type semiconductor comprises a diamond substrate, and a diamond semiconductor formed on a main surface thereof and turned out to be n-type. The diamond semiconductor exhibits a carrier concentration (electron concentration) negatively correlated with temperature in a part of a temperature region in which it is turned out to be n-type, and a Hall coefficient positively correlated with temperature. The diamond n-type semiconductor having such a characteristic is obtained, for example, by forming a diamond semiconductor doped with a large amount of a donor element while introducing an impurity other than the donor element onto the diamond substrate.

Abstract: A light-emitting diode package (LED package) includes a LED and a carrier. The LED includes a substrate, a semiconductor layer, a first electrode and a second electrode. The semiconductor layer is located on a surface of the substrate and has a rough surface. The semiconductor layer includes a first-type doped semiconductor layer, a second-type doped semiconductor layer and a light-emitting layer disposed between the two doped semiconductor layers. The first electrode and the second electrode are disposed on and electrically coupled the first-type doped semiconductor layer and the second-type doped semiconductor layer, respectively. The carrier has a rough carrying surface and includes a first contact pad and a second contact pad disposed on the rough carrying surface. The first electrode and the second electrode of the LED face the carrier and are electrically coupled to the first contact pad and a second contact pad, respectively.

Abstract: A device has a plurality of ultra-small resonant structures, each of said structures constructed and adapted to emit light at a particular wavelength when a beam of charged particles is passed nearby, wherein at least one of the light emitters emits light in a first range of wavelengths and wherein at least another of said light emitters emits light in a second range of wavelengths, distinct from said first range of wavelengths; and a controller mechanism constructed and adapted to selectively switch different ones of said light emitters on and off, whereby said device emits light in said first range of wavelengths or said second range of wavelengths. The wavelengths may be selected to emulate or provide warm light, cold light.

Abstract: The present application relates to a semiconductor device comprising one or more protective layers, and more specifically to a light-emitting diode comprising one or more ultraviolet protective layers. The use of said UV protective layers prevents the degradation of a LED by UV light.

Abstract: A light-emitting diode includes a substrate, a buffer layer on the substrate, a first semiconductor layer on the buffer layer, a light-emitting layer on the first semiconductor layer, a second semiconductor layer on the light-emitting layer, wherein the first semiconductor layer is partially exposed through the second semiconductor layer and the light-emitting layer, a first electrode on the exposed first semiconductor layer, and a second electrode on the second semiconductor layer, the second electrode having a grid shape.

Abstract: A light-emitting diode with an improved service life is provided. The diode is formed from a transparent outer shell that contains a heat-resistant encapsulant at least partially surrounding a light-emitting diode clip. The first encapsulant is compressed between the outer shell and a second encapsulant when it is sealed into the outer shell by the second encapsulant.

Abstract: A laser diode includes a first n-cladding layer disposed on and lattice-matched to an n-semiconductor substrate, wherein the first n-cladding layer is n-AlGaInP or n-GaInP; a second n-cladding layer of n-AlGaAs supported by the first n-cladding layer; and an inserted layer disposed between the first n-cladding layer and the second n-cladding layer, wherein the inserted layer includes the same elements as the first n-cladding layer, the inserted layer has the same composition ratios of Al and Ga (and P) as the first n-cladding layer, and the inserted layer contains a lower composition ratio of In than the first n-cladding layer.

Abstract: A nitride based light emitting device is disclosed. More particularly, a nitride based light emitting device capable of improving light emitting efficiency and reliability thereof is disclosed. The nitride based light emitting device includes a first conductive semiconductor layer connected to a first electrode, a second conductive semiconductor layer connected to a second electrode, an active layer located between the first conductive semiconductor layer and the second conductive semiconductor layer and having a quantum well structure, a first insertion layer located in at least one of a boundary between the first conductive semiconductor layer and the active layer and a boundary between the second conductive semiconductor layer and the active layer, and a second insertion layer located adjacent to the first insertion.

Abstract: A nitride semiconductor light emitting device is provided with a substrate, an n-type nitride semiconductor layer, a p-type nitride semiconductor layer, an n-side pad electrode, a translucent electrode and a p-side pad electrode, wherein the translucent electrode is formed from an electrically conductive oxide, the n-side pad electrode adjoins the periphery of the translucent electrode and the p-side pad electrode is disposed so as to satisfy the following relationships: 0.3L?X?0.5L and 0.2L?Y?0.5L where X is the distance between ends of the p-side pad electrode and the n-side pad electrode, Y is the distance between the end of the p-side pad electrode and the periphery of the translucent electrode, L is the length of the translucent electrode on the line connecting the centroids of the p-side pad electrode and the n-side pad electrode minus the outer diameter d of the p-side pad electrode.

Abstract: A light-emitting element storing package which ensures the efficient reflection of light emitted by a light-emitting element by a reflector frame and thereby improves the brightness of the emitted light, and a method of manufacturing the same are provided. The light-emitting element storing package includes: an insulating substrate consisting of a ceramic board, a reflector frame composed of a ceramic material, joined to the upper surface of the substrate along its outer edge and having an inner wall surface defining a light-reflecting surface, and a wiring pattern layer formed on the upper surface of the substrate for connection with a light-emitting element, a light-emitting element storing concave portion, which is defined by the substrate and the reflector frame, and in which the light-emitting element is mounted on the wiring pattern layer, the reflector frame is mainly composed of nitride ceramics and its light-reflecting surface is composed of white ceramics.

Abstract: The present invention discloses tunnel vertical semiconductor devices and chips comprising tunnel vertical GaN based, GaP based and ZnO based LEDs and manufacturing method. The structure of an embodiment of tunnel vertical semiconductor devices and chips is the following: first and second electrodes formed on first surface of a supporting silicon chip; third and fourth electrodes formed on second surface of the supporting silicon chip. First and second electrodes are respectively electrically connected with third and fourth electrodes. The position and shape of second electrode correspond to that of the reflector/Ohmic/bonding layer of a semiconductor chip, while the position and shape of first electrode is corresponded to that of a protection plug. A half-tunnel-metal-plug electrically connects a patterned electrode deposited on a current spreading layer to the first electrode on the first surface of the supporting silicon chip.

Abstract: A semiconductor device includes a light emitting semiconductor die mounted on at least one of first and second electrically conductive bonding pads, which are located on a first major surface of a substrate of the device. The light emitting semiconductor die has an anode and a cathode, which are electrically connected to the first and second electrically conductive bonding pads. The semiconductor device further includes first and second electrically conductive connecting pads, which are located on a second major surface of the substrate. The first and second electrically conductive bonding pads are electrically connected to the first and second electrically conductive connecting pads via first and second electrically conductive interconnecting elements.

Abstract: A method for producing Group-III-element nitride crystals by which an improved growth rate is obtained and large high-quality crystals can be grown in a short time, a producing apparatus used therein, and a semiconductor element obtained using the method and the apparatus are provided. The method is a method for producing Group-III-element nitride crystals that includes a crystal growth process of subjecting a material solution containing a Group III element, nitrogen, and at least one of alkali metal and alkaline-earth metal to pressurizing and heating under an atmosphere of a nitrogen-containing gas so that the nitrogen and the Group III element in the material solution react with each other to grow crystals.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, a resistance is formed. Around the resistance, a protection element having a PN junction region is formed. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of the resistance. By use of this structure, when negative ESD surge is applied to a pad for an electrode which applies a voltage to a P type diffusion layer, the PN junction region of the protection element breaks down. Accordingly, the resistance can be protected.

Abstract: The present invention relates to a structure and a manufacturing method of epitaxial layers of gallium nitride-based compound semiconductors with less dislocation densities. Surface treatment is carried out first on the surface of a substrate using reaction precursors Cp2Mg and NH3. Then a gallium nitride-based buffer layer is formed on the substrate to form a semiconductor epitaxial structure with an interface layer or an interface zone between the substrate and the buffer layer. The structure can reduce effectively the dislocation density formed in the gallium nitride-based epitaxial layer on top of the gallium nitride-based buffer layer. Thereby, high-quality epitaxial layers tend to be attained and the uniformity of the dislocation density can be enhanced.

Abstract: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain inducing porous layer or a porous silicon layer and strain inducing porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain inducing porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.

Abstract: A field-effect transistor has a so-called double heterostructure which is formed such that a channel layer through which electrons travel is provided between an electron supply layer and a liner layer, wherein a forbidden band width of the liner layer and a forbidden band width of the electron supply layer are broader than a forbidden bandwidth of the channel layer.

Abstract: Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in the neutral region of the emitter layer. This quasi-drift field induces valence bandgap grading within the emitter layer so as to accelerate movement of holes from the base layer through the emitter layer. Accelerated movement of the holes from the base layer through the emitter layer reduces emitter delay time and thereby, increases the cut-off frequency (fT) and the maximum oscillation frequency (fMAX) of the resultant HBT.

Abstract: A low power consuming semiconductor device comprises a p substrate, a first semiconductor cell formed over the p substrate, a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell, and a tap cell for coupling a power pin to n-well structures of the first semiconductor cell and the second semiconductor cell, and for coupling a ground pin to the p substrate. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.

Abstract: Provided is an inverter having a new structure capable of easily controlling a threshold voltage according to position in fabricating an inverter circuit on a plastic substrate using an organic semiconductor. A driver transistor is formed with a dual-gate structure and a positive bias voltage is applied to the top gate of the driver transistor so that a body effect appears in the organic semiconductor. Accordingly, the threshold voltage is shifted to a negative zone due to positive potential applied to the top gate of the driver transistor so that the driver transistor acts as an enhancement type transistor. A dual-gate organic structure may be applied to a load transistor rather than the driver transistor, or a p-type dual-gate organic transistor structure may be applied to both the driver transistor and the load transistor.

Abstract: It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated circuit. In a semiconductor integrated circuit apparatus according to the invention, a first wiring layer is provided with a plurality of signal wirings having an equal width which is disposed in parallel with each other at a regular interval, and at least two of the signal wirings which are adjacent to each other are electrically connected to each other.

Abstract: A method of fabricating a semiconductor memory device includes forming a first insulating layer and a sacrificial layer on a substrate. The first insulating layer and the sacrificial layer have an opening therein. A first conductive layer is formed in the opening and on the sacrificial layer. A second insulating layer is formed on the first conductive layer. The second insulating layer, the first conductive layer and the sacrificial layer are then planarized until the first insulating layer is exposed, thereby forming a first conductive pattern and a second insulating layer pattern in the opening. A phase change material layer is formed on the first conductive pattern, the first insulating layer and the second insulating layer pattern. A second conductive pattern is formed on the phase change material layer. A semiconductor memory device and a data processing system adopting the semiconductor memory device are also provided.

Abstract: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used to form nanotubes in arrays in the presence of directing electric fields, optionally in combination with self-assembled monolayer patterns. Bistable devices are described.

Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

Abstract: A power semiconductor device with charge compensation structure and a method for producing the same is disclosed. In one embodiment, the power semiconductor device has in a semiconductor body a drift path between a body zone and a substrate region. The drift path is divided into drift zones of a first conduction type. A field stop zone is provided having the first conduction type, which is arranged on the substrate region, wherein the net dopant concentration of the field stop zone is lower than that of the substrate region and higher than that of the drift zones.

Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.

Abstract: A nickel-based germanide contact includes a processing material that inhibits agglomeration of nickel-based germanide during processing to form the contact as well as during post-germanidation processes. The processing material is either in the form of a capping layer over the nickel layer or integrated into the nickel layer used to form the nickel-based contact. Reducing agglomeration improves electrical characteristics of the contact.

Abstract: A control electrode is provided via an insulating film on one main surface of a semiconductor substrate having a first conductivity type. A pair of dopant diffusion regions are formed, with the control electrode therebetween, in a surface layer region of the semiconductor substrate. Resistance variation sections are formed in the surface layer region of the semiconductor substrate between the control electrode and the dopant diffusion regions. The resistance variation sections are of the second conductivity type and have a dopant concentration lower than that of the dopant diffusion regions. First and second main electrodes are provided on the dopant diffusion regions of the semiconductor substrate. A first charge storage section is provided between the first main electrode and control electrode on the semiconductor substrate. A second charge storage section is provided between the second main electrode and control electrode on the semiconductor substrate.

Abstract: Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the direction of the gate electrode of the transistor. The source field plate may reduce the electrical field (e.g., peak electrical field and/or integrated electrical field) in the region of the device between the gate electrode and the drain electrode which can lead to a number of advantages including reduced gate-drain feedback capacitance, reduced surface electron concentration, increased breakdown voltage, and improved device reliability. These advantages enable the gallium nitride material transistors to operate at high drain efficiencies and/or high output powers. The devices can be used in RF power applications, amongst others.

Abstract: Pixel portions each of which has a charge storage portion formed in a semiconductor substrate 11 and a transfer gate for transferring charges stored in the charge storage portion are isolated from each other by a device isolation region in the semiconductor substrate. A buried gate electrically connected to the transfer gate is embedded in the device isolation region. The buried gate includes a gate dielectric film and gate electrode formed in a trench of the semiconductor substrate.

Abstract: A method of manufacturing a ferroelectric memory cell includes: forming device isolation regions; and source/drain regions; forming a gate insulating film on the semiconductor substrate; forming a gate electrode on the gate insulating film; forming; forming a contact plug to be connected to one of the source/drain regions. The method further includes: forming a lower electrode to be connected to the contact plug; depositing a sol-gel solution containing a ferroelectric minute crystal on the lower electrode to form a ferroelectric film; forming an upper electrode on the ferroelectric film; forming a second interlayer insulating film. The method further includes: forming a capacitor contact plug to be connected to the upper electrode; forming a substrate contact plug to be connected to the other one of the source/drain regions; and forming first and second wiring layers to be connected to the capacitor contact plug and the substrate contact plug, respectively.

Abstract: The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.

Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

Abstract: A semiconductor device having in a deep hole formed in a first interlayer insulating film a memory cell region that comprises a plurality of capacitors having a lower electrode 229 composed of a crown structure having an outside face and inner face, a first upper electrode 231 facing the outside face of the lower electrode, and a dielectric and a second upper electrode extending from the inner face of the lower electrode to the surface of a first interlayer insulating film other than the deep hole; wherein the first upper electrode is connected to the second upper electrode by connecting a first upper electrode 227 formed on the inner wall of the deep hole to the wiring 241a via a conductor film 224 and a conductor plug 236a, and connecting a second upper electrode 231 to be a plate to a wiring 241a via a conductor plug 239a.

Abstract: Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the trenches; a base region formed in a region of the silicon substrate located between the two trenches; and an emitter region and a collector region formed on portions of side surfaces of the trenches, respectively, the portions of the sides located above the insulating film and formed in the base region.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: A method of fabricating a nonvolatile semiconductor memory device includes forming a first dielectric layer on a major surface of a semiconductor substrate, forming a floating gate electrode layer on the first dielectric layer, and forming a second dielectric layer, which includes a metal oxide film or a stacked film thereof, on the floating gate electrode layer. The method of fabricating the nonvolatile semiconductor memory device further includes forming a control gate electrode layer on the second dielectric layer by using a material including silicon having no silicon (Si)-hydrogen (H) bond.

Abstract: A new MOSFET device is described comprising a metal gate electrode, a gate dielectric and an interfacial layer. The electrostatic potential at an interface between the gate electrode and the gate dielectric of a MOSFET device can be controlled by introducing one or more interfacial layer(s) of a dielectric material, at the monolayer(s) level (i.e., preferably two monolayers), between the gate electrode and the gate dielectric. A method for its manufacture is also provided and its applications.

Abstract: Separate first and second floating gates for attracting carriers transferring in a transistor structure having a channel region and first and second main electrode regions into charge storage films therebelow are formed so as to largely face a control gate. The control gate between the separate first and second floating gates faces to the channel region via thin interlayer insulating layer. Therefore, a semiconductor device according to the present invention can inject electrons the charge storage film without causing writing errors in a writing operation, and therefore can increase in reliability thereof, control a writing voltage, prevent loss of the electrons stored in the charge storage film, and reliably apply a bias voltage to a channel region.