Abstract: A semiconductor package, a chip carrier structure thereof, and a method for fabricating the chip carrier structure are provided. A substrate having a mounting region and a covering region is disposed in an opening of a carrier. A molding process is performed to form an encapsulant on the covering region of the substrate, with the mounting region of the substrate being exposed from the encapsulant. A cutting process is performed along edges of the substrate, such that the chip carrier structure is fabricated. A semiconductor chip is mounted on the mounting region of the substrate in a flip-chip manner, such that the semiconductor package is completed. The encapsulant formed on the covering region of the substrate provides the substrate with supporting strength and prevents poor electrical contact for the semiconductor package caused by substrate warpage.

Abstract: The present invention provides a method of manufacturing semiconductor device. The method includes providing a semiconductor wafer having a main surface; defining a chip forming region which includes chip regions defined by scribe lines, and a peripheral region which surrounds the chip forming region, on the main surface; forming circuit elements and electrode pads connected to the circuit elements on the chip areas; forming an insulating film, which exposes respective portions of the electrode pads, on the main surface; forming protruded electrodes on the insulating film provided in the chip areas so that the protruded electrodes are arranged at predetermined intervals in the chip area; forming an encapsulating material, which exposes top faces of the protruded electrodes, on the insulating film; and cutting the semiconductor wafer along the scribe lines.

Abstract: A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.

Abstract: In a semiconductor device comprising a ceramic substrate, a surface mount component, and sealing resin and obtained by division into pieces, the ceramic substrate is composed of a multiple piece substrate provided with dividing grooves for the division into pieces on both front and rear surfaces in advance, a plurality of the surface mount components are mounted on the multiple piece substrate and sealed collectively by the sealing resin, and the substrate is divided along the dividing grooves. Further, when the shortest distance from an end on the front surface of the ceramic substrate to an end of the surface mount component is set to “a” ?m, a thickness of the ceramic substrate is set to “b” ?m, and sum of depths of the dividing grooves on the front and rear surfaces of the ceramic substrate is set to “c” ?m, a relationship of a?269×c/b+151 is established.

Abstract: An apparatus and method for a wire-bond die-up area array package is described. The package includes an integrated circuit (IC) die, a substrate, and a thermally conducting body. A bottom surface of the IC die is exposed through an opening in a central region of the substrate. The die is mounted to the thermally conducting body. A bottom surface of the thermally conducting body is configured to be connected to a circuit board, such as a PWB, when the package is mounted to the circuit board. The bottom surface of the thermally conducting body may be connected directly to the circuit board, or may be coupled to the circuit board via solder balls or other mechanism. One or more wirebonds are used to electrically connect the die to a top surface of the substrate. A mold compound encapsulates the die, the wirebonds, and at least a portion of the top surface of the substrate, and fills a gap between peripheral edges of the IC die and inner walls of the substrate central window opening.

Abstract: The present invention relates to a closed system for cooling without moving mechanical parts and at a low noise level, one or more heat-emitting elements. The system comprises a first heat-receiving part that is adapted to receive heat from the at least one heat-emitting element, a cooling fluid for absorption of heat by heating and evaporation, a bubble pump for generation of a fluid flow in the system, the bubble pump being positioned downstream the first heat-receiving part and moving the cooling fluid towards a radiator emission of heat from the cooling fluid in liquid form to the surroundings, and a condenser for condensing of evaporated cooling fluid and emission of the heat of condensation.

Abstract: A bonding-bump (1) of small dimensions comprises a gold pedestal portion (2) formed on a circuit element (10), a nickel barrier layer (3) formed on the pedestal portion (2), and a soldering portion (5) formed on the barrier layer (3). The soldering portion (5) comprises first (6) and second (8) gold layers having an intermediate tin layer (7) sandwiched therebetween. The relative masses of gold and tin in the first, second and intermediate layers (6-8) gives the soldering portion (5) a composition corresponding to the eutectic gold-tin composition. The bonding-bump (1) may be manufactured by depositing a titanium seed layer onto the circuit element (10), removing portions of the titanium layer where there are contact pads (P) on the circuit element (10), electroplating the layers and portions (2-8) constituting the bonding-bump (1), and removing the remaining portions of the seed layer. This bonding-bond technique is used to connect circuit elements in electronic devices.

Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

Abstract: A method of forming a dual damascene pattern for a metal interconnection by a relatively simple process. Only a portion of an interlayer insulating film is initially etched when forming a via hole. When the interlayer insulating is etched to form a trench, the remaining portion of the via hole may be etched simultaneously.

Abstract: A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.

Abstract: A photo mask set for forming multi-layered interconnection lines and a semiconductor device fabricated using the same includes a first photo mask for forming lower interconnection lines and a second photo mask for forming upper interconnection lines. The first and second photo masks have lower opaque patterns parallel with each other and upper opaque patterns that overlap the lower opaque patterns. In this case, ends of the lower opaque patterns are located on a straight line that crosses the lower opaque patterns. As a result, when upper interconnection lines are formed using the second photo mask, poor photo resist patterns can be prevented from being formed despite the focusing of reflected light.

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

Abstract: A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger. The bond finger is made of copper. The conductive layer is made of copper or gold. The bond stud is made of gold and overlies a side portion and top portion of the copper layer.

Abstract: An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.

Abstract: A board interconnection structure having a first printed wiring board in which a first conductive circuit is arranged on a first insulating layer, the first conductive circuit having, on an end portion thereof, a first connection terminal in which an upper surface width is narrower than a bottom surface width; a second printed wiring board in which a second conductive layer having a second connection terminal is arranged on a second insulating layer; and a connection layer that forms fillets along longitudinal side surfaces of the first connection terminal, and interconnects the first connection terminal and the second connection terminal. The first connection terminal may have a projection portion.

Abstract: A semiconductor component with connecting elements between a semiconductor chip made from a semiconductor wafer with discrete semiconductor components and a superordinate circuit carrier is disclosed. The semiconductor component has a coplanar area having top sides of the connecting elements and a plastic housing composition. The connecting element has a mesa structure or a mushroom-shaped form for surface mounting. Moreover, the connecting element includes a structured nickel- and lead-free contact coating. The connecting element is arranged on contact areas of the semiconductor chip, the areal extent of the connecting elements corresponding to the contact areas of the semiconductor chip.

Abstract: A printed wiring board having an interlayer insulation layer and conductive circuits formed on the interlayer insulation layer. The conductive circuits include a first conductive circuit and a second conductive circuit positioned adjacent to each other, and the first and second conductive circuits satisfy a formula, 0.10 T?|W1?W2|?0.73 T, where W1 represents an upper conductive circuit space between the first and second conductive circuits, W2 represents a lower conductive circuit space between the first and second conductive circuits, and T represents a thickness of the first and second conductive circuits.

Abstract: An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.

Abstract: Apparatuses, methods, and systems for improved integrated circuit packages are described. An integrated circuit (IC) package includes a substrate having opposing first and second surfaces, an IC die, a plurality of conductive elements, and an encapsulating material. The substrate has a plurality of contact pads on the first surface that are electrically coupled to a plurality of electrically conductive features on the second surface. The plurality of conductive elements is formed on the first surface of the substrate. The IC die is located on the first surface of the substrate. The encapsulating material encapsulates the IC die and a portion of each element of the plurality of conductive elements.

Abstract: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing an unsealed semiconductor device into a mold and subjecting a curable liquid silicone composition that fills the spaces between the mold and the unsealed semiconductor device to compression molding under a predetermined molding temperature, wherein the curable liquid silicone composition has viscosity of 90 Pa·s or less at room temperature, a time interval from the moment directly after measurement of a torque with a curometer at the molding temperature to the moment when the torque reached 1 kgf·cm being not less than 1 min.

Abstract: A curable organopolysiloxane composition capable of forming cured products of superior optical transmittance exhibiting little heat-induced yellowing over time. A semiconductor device having semiconductor elements encapsulated in a cured product of the composition. The composition includes (A) an organopolysiloxane having at least two silicon-bonded alkenyl groups per molecule and bearing silicon-bonded aryl groups, whose content relative to all silicon-bonded organic groups is not less than 40 mol %, (B) an organopolysiloxane having at least two silicon-bonded hydrogen atoms per molecule, and (C) an organosiloxane oligomer complex of platinum, where the oligomer has not more than eight silicon atoms per molecule and bears silicon-bonded alkenyl groups and silicon-bonded aryl groups.

Abstract: An evaporator assembly unit, especially for a vehicle heater or a reformer arrangement of a fuel cell system, includes a wall arrangement (12) enclosing an evaporation chamber (20) with a circumferential wall (14) and with a bottom wall (16). An air introduction shoulder (18) extending in the direction of a wall longitudinal axis (L) is provided with a plurality of first air introduction openings (22). Evaporator medium (26), that is porous at least in some areas, is provided on the side of the wall arrangement (12) facing the evaporation chamber (20). An auxiliary air opening arrangement (34) with at least one second air introduction opening (36) is provided in the wall arrangement (12).

Abstract: A composition for forming a pattern includes: about 1% to about 10% by weight of a liquid prepolymer, about 40% to about 60% by weight of an acrylate having a hydrophilic group, about 10% to about 20% by weight of a viscosity modifier, about 1% to about 5% by weight of a photoinitiator, and an additive.

Abstract: A method manufactures a digital image sensor including at least one optical lens using a hardenable liquid or gelatinous material. The method includes depositing a calibrated volume of the material on a lens formation base using a tubular needle of a small diameter, so that the volume of material deposited has at least one convex part under the effect of interface energies, and hardening all or part of the volume of deposited material.

Abstract: A method of fabricating a metamaterial is provided, comprising providing a sample of engineered microstructured material that is transparent to electromagnetic radiation and comprises one or more voids, passing through the voids a high pressure fluid comprising a functional material carried in a carrier fluid, and causing the functional material to deposit or otherwise integrate into the engineered microstructured material to form the metamaterial. Many microstructured materials and functional materials can be used, together with various techniques for controlling the location of the integration of the functional material within the microstructured material, so that a wide range of different metamaterials can be produced.

Abstract: The present invention relates to a conical wedge-shaped lensed fiber and the method of making the same. The method comprises: (a) providing an optical fiber having a central axis and an end; (b) machining the end of the optical fiber to form a flat end face; (c) machining the end of the optical fiber to form a conical region; (d) machining one side of the conical region to form a flat first surface; (e) machining another side of the conical region to form a flat third surface, wherein the first surface and the third surface intersect at a intersecting line that is perpendicular to the central axis; and (f) fusing the intersecting line to form a lens. The method has simplified fabricating processes and need not to set up any particular angle of rotation of the fiber. Therefore, the fabricating time and cost are reduced, and the coupling efficiency of the lensed fiber is up to 90%.

Abstract: Process for the manufacture of a light filter compatible with night vision goggles having at least the following stages: preparation of a homogeneous solution comprising one monomer, one dye; one photoinitiator; photochemical crosslinking by ultraviolet radiation of the solution in the film form; annealing the photocrosslinked film.

Abstract: Method of forming a plastic element include dispensing a quantity of a liquid precursor material into a first die mold, positioning a carrier tape on the first die mold above the dispensed liquid precursor material, bringing a second die mold into contact with the carrier tape and the first die mold, and applying pressure to the first die mold and the second die mold. The liquid precursor material may include a liquid silicone.

Abstract: Disclosed are: (i) a molding-system platen actuator, (ii) a molding system having a molding-system platen actuator, and/or (iii) a method of a molding-system platen actuator, amongst other things.

Abstract: Apparatus for controlling the rate of flow of fluid material through an injection molding flow channel leading to a mold cavity, the apparatus comprising: a pin having a longitudinal length and a diameter slidably mounted in an aperture in a housing that is adapted for back and forth axial movement of the pin through the flow channel; the pin having a protrusion at a selected position along its length, the protrusion having an upstream end and a downstream end and a maximum diameter circumferential surface intermediate the upstream and downstream ends; the channel having an interior surface area portion which is complementary to the maximum diameter circumferential surface of the protrusion of the pin; the pin being slidable to a position within the channel such that the maximum diameter circumferential surface of the protrusion is matable with the complementary interior surface portion of the channel to stop flow of the fluid material.

Abstract: Prepare a foam structure that includes hollow coalesced foam strands and, optionally, solid coalesced foam strands using an extrusion die block equipped with apertures that promote forming the hollow strands and, optionally, the solid foam strands.

Abstract: The invention provides a pre-mix of positive electrode material in transportable solid form comprising polymer and solid particles of electrochemically active material and/or electronically conductive additives and a process for preparing a pre-mix positive electrode in transportable solid form. The pre-mix positive electrode material may also comprise an alkali metal salt either dissolved or dispersed in the mixture. The invention also provides making a cathode film from the transportable solid pre-mix of positive electrode material.

Abstract: A method and apparatus for continuously producing preselected lengths of coiled tubing are disclosed. According to the method, plastic tubing is continuously wound onto a rotating main tube shaft (24). Downstream from the point where the tubing begins to wind about the shaft, a heat source (46) is directed toward the coiled tubing, softening it as it traverses thereby. Further downstream, a cool-air source (48) directed at the softened tubing sets the tubing into its coiled form. Subsequently, the coiled tubing is cut into preselected lengths by a cutter (50) downstream from the cool-air source.

Abstract: A hard mold and method of preparing the mold is disclosed. The hard mold is designed for manufacturing articles having various shapes and patterns. The shaping mold includes a layer of hardened material provided over the entire surface of the selected master. The inventor has found that a polyurea coating or other polyurethane hybrid is preferred. Once the layer of hardened material has dried, the surface of the hardened material is sanded with a 20-40 grit sandpaper and a layer of polyester resin is then applied to the layer of hardened material. Once the polyester resin is applied, multiple layers of vinyl ester are applied to the polyester resin to prevent the polyester resin from shrinking. In the preferred embodiment, the application includes at least three (3) layers of vinyl ester.

Abstract: An object is to provide a mold-clamping apparatus (10) which can sufficiently increase accuracy of mold opening and closing. The mold-clamping apparatus (10) includes a first stationary member to which a stationary mold (15) is attached; a first movable member disposed in opposition to the first stationary member and to which a movable mold (16) is attached; a second movable member which is advanced and retreated in association with advancement and retreat of the first movable member; a mold-clamping-force transmission member connecting the first and second movable members; and a drive section for mold opening and closing, the drive section advancing and retreating the first movable member to thereby effect mold opening and closing. The drive section for mold opening and closing overlaps the mold-clamping-force transmission member at least partially.

Abstract: The present invention relates to a multimodal linear low density polyethylene composition for the preparation of a pressure pipe. The invention further relates to a pressure pipe, comprising said composition, a process for the manufacturing of a pipe made of the composition and to a process for the recycling of pipe material consisting of the composition according to the invention. Furthermore the invention relates to the use of the pressure pipe as an irrigation pipe, especially a drip irrigation pipe.

Abstract: A method is provided for making a composite laminate aircraft skin for a fuselage in multiple composite panels. A resin-impregnated composite tape is placed on a lay-up surface of a mandrel tool to form the composite laminate aircraft skin as a barrel that is substantially the shape of a fuselage section. The barrel is cut into a plurality of panels on the mandrel tool, and at least one panel of the plurality of panels is transferred, individually and independently of all other of the plurality of panels, from the lay-up surface of the mandrel tool to a first cure tool of a plurality of cure tools having an aero surface tooled to an outer mold line. The at least one of the panels is cured on the first cure tool to form a cured composite panel. The first cure tool defines and controls the outer mold line of the at least one panel. The cured composite panel is removed from the first cure tool.

Abstract: An apparatus for the extrusion a multi-layer parison comprises an extrusion blow molding head having a bore passing through the head with a diverter sleeve located within the bore. There is a first manifold in fluid communication with a first die inlet, the first manifold substantially surrounds the diverter sleeve and is in fluid communication with a proximal end of a flow path formed by the diverter sleeve and the bore; wherein the flow path extends from the proximal end to a head exit and a first land that has a variable width is positioned between the first manifold and the flow path. A second manifold is in fluid communication with a second die inlet, the second manifold substantially surrounds the diverter sleeve and is in fluid communication with the flow path at a first location downstream from the proximal end of the flow path; wherein the flow path has a width that increases at the first location; and a second land that has a variable width positioned between the second manifold and the flow path.