Abstract: A field-effect transistor is provided which includes: a first nitride semiconductor layer having a lattice constant a1 and a bandgap Eg1; a second nitride semiconductor layer stacked on the first nitride semiconductor layer and having a lattice constant a2 and a bandgap Eg2; a source electrode and a drain electrode formed on the second nitride semiconductor layer; a piezo-effect film formed on the second nitride semiconductor layer in a region between the source electrode and the drain electrode; and a gate electrode formed on a region of the piezo-effect film. The relation between the lattice constants a1 and a2 is a1>a2. The relation between the bandgaps Eg1 and Eg2 is Eg1<Eg2.

Abstract: A non-volatile memory and a method of fabricating the same are described. First, a substrate is provided. Then, a plurality of stack structures is formed on the substrate. Each stack structure comprises, from bottom to top, a bottom dielectric layer, a charge trapping layer, a top dielectric layer, a control gate and a cap layer. Next, a plurality of spacers is formed on the sidewalls of the stack structures. Thereafter, a gate dielectric layer is formed over the substrate. A word line is formed between two neighboring stack structures. After that, the cap layers in the stack structures are removed. A source and a drain are formed in the substrate beside the stack structures adjacent to the sides of each word line.

Abstract: In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and has one or more inflected portions at its sidewalls exposed from the first isolation layer, where the first active region is divided into an upper part and a lower part by the inflected portions and a width of the upper part is narrower than that of the lower part. A tunneling insulation layer is formed on the first active region. A storage node layer is formed on the tunneling insulation layer. Also, a blocking insulation layer is formed on the storage node layer, and a control gate electrode is formed on the blocking insulation layer.

Abstract: A semiconductor device, in which both a reduction in a resistivity of a gate electrode and stabilization of transistor characteristics is achieved, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a semiconductor substrate, a plurality of gate electrodes each including an electric charge storage layer formed on the semiconductor substrate through a first insulator, first and second conductor layers, and a second insulator disposed between the electric charge storage layer and the first conductor layer, a barrier insulator provided between the gate electrodes and being in contact with side surfaces alone of the gate electrodes, and an interlayer insulator provided in contact with an upper surface of the second conductor layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer interposed between a sidewall of the control gate electrode and the semiconductor substrate, a tunneling insulation layer interposed between the storage node layer and the semiconductor substrate, a blocking insulation layer interposed between the storage node layer and the control gate electrode, and first and second channel regions formed around a surface of the semiconductor substrate to at least partially surround the control gate electrode. The semiconductor memory device may include a plurality of control gate electrodes, storage node layers, tunneling insulation layers, blocking insulation layers, and continuous first and second channel regions.

Abstract: A non-volatile memory cell with twin gates formed on an N-well is provided. The non-volatile memory cell includes at least a first gate, a second gate, a pair of NO (Nitride/Oxide) spacer layers, a pair of ONO (Oxide/Nitride/Oxide) spacers, a source, a drain, an extension source and an extension drain. The NO spacer layers are formed at the inner sidewalls of the first gate and the second gate to form a U-shape spacer for storing one bit of data. The ONO spacers are formed at the outer sidewalls of the first gate and the second gate. The source and drain and the extension source and the extension drain have P-type impurity dopants.

Abstract: A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.

Abstract: A power semiconductor module having an electrically insulating substrate, to be arranged with a circuit board. The circuit board is spaced apart from the substrate by a housing. First conductor tracks are disposed inside the substrate, facing the circuit board, for receiving power semiconductor devices which can be driven by a control IC device. Second conductor tracks are provided on the inside of the circuit board facing the substrate. In the housing, elastic connecting elements are pressure-contacted by a rigid pressure body to establish electrical connection between the first and second conductor tracks. An optimum electromagnetic compatibility is achieved due to the fact that IC conductor tracks and the control IC device are also provided on the inside of the substrate.

Abstract: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.

Abstract: A semiconductor device includes a semiconductor body defining a trench structure having walls. A plurality of vertical gate zones each have a gate electrode and a gate oxide that covers the walls of the trench structure. A body zone of a first conduction type is arranged between two of the gate zones and a drift zone of a complementary conduction type with respect to the first conduction type vertically adjoins the body zone. Floating shielding zones of the first conduction type are arranged adjacent to the gate zones and extend into the semiconductor body deeper than the trench structure of the gate zones. A pn junction with the drift zone is below the trench structure. A buried dopant zone of the same charge type as the drift zone has a higher impurity concentration than the drift zone and is arranged in a space charge region of the pn junction at a distance from the trench bottom of the trench structure.

Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region.

Abstract: A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor includes a photodiode formed in a substrate structure, first to fourth gate electrodes formed over the substrate structure, spacers formed on both sidewalls of the first to fourth gate electrodes and filled between the third and fourth gate electrodes, a first ion implantation region formed in a portion of the substrate structure below the spacers filled between the third and fourth gate electrodes, and second ion implantation regions formed in portions of the substrate structure exposed between the spacers, the second ion implantation regions having a higher concentration than the first ion implantation region.

Abstract: Provided is an electro-optical apparatus including a first thin-film transistor having a first gate electrode, a first gate insulating layer and a first active layer, which are respectively formed of a conductive film, an insulating film and a semiconductor film, in a pixel region of a device substrate, the apparatus including: a second thin-film transistor having a first gate electrode formed of the conductive film, a second gate insulating layer formed by removing a portion of the insulating film in a thickness direction and a second active layer formed of the semiconductor film, in a region other than the pixel region of the device substrate.

Abstract: An active device array substrate, including a substrate, a plurality of pixel units, a plurality of first lead wires, an insulating layer, a plurality of second lead wires and a passivation layer, is provided. The active device array substrate has a display area and a peripheral area. The pixel units are disposed in the display area of the substrate. The first lead wires and the second lead wires are disposed in the peripheral area, and electrically connected to the pixel units respectively. The first lead wires have two opposite first tips. Moreover, the first lead wires are covered by the insulating layer having at least a first opening to expose the two opposite first tips. Additionally, the second lead wires are covered by the passivation layer.

Abstract: Provided is a semiconductor device manufacturing method including a field oxide insulation film forming step including forming a field oxide insulation film (12) so that, in an active region (13), a portion (13a), which corresponds to a side surface portion of the active region (13) opposing a rotation center (O) in spin-coating on the surface of the semiconductor substrate (11) in a centrifugal force acting direction (F) along the surface of the semiconductor substrate (11) and located in a forward side of the centrifugal force acting direction (F), has a curved surface convex to the forward side of the centrifugal force acting direction (F) when the semiconductor substrate (11) is seen in a plan view.

Abstract: A memory device includes a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; and a second memory cell area being disposed adjacent to a first side of the first memory cell area, and having a second latch area where one or more electronic components are constructed for storing a value, and a second peripheral area surrounding the second latch area. One edge of the first memory cell area shifts away from its corresponding edge of the second memory cell area. Thus, the area or yield rate of the memory device can be adjusted.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: The present invention relates to a non-volatile electrical phase change memory device comprising a substrate, a first interlayer dielectric film deposited on the substrate, a bottom electrode layer formed on the first dielectric layer, a second interlayer dielectric film formed on the bottom electrode layer, a phase change material layer deposited on the second interlayer dielectric film, and a top electrode layer formed on said phase change material layer, the bottom electrode layer being brought into contact with the phase change material layer through a contact hole which is formed in the second interlayer dielectric film and filled with the phase change material or bottom electrode material, so that the phase change layer and the bottom electrode layer come into close contact with each other, wherein an interfacial control layer is formed at the interface of the contact hole between the phase change layer and the bottom electrode layer, said interfacial control layer having strong chemical bonds with t

Abstract: There is disclosed a voltage regulating apparatus with a short settling time and a small current consumption. The voltage regulating apparatus comprises a reference voltage generator including an MOSFET array comprising a plurality of MOSFETs with a structure in which a drain and a source are connected in series with each other, a supply voltage is applied to the drain of the MOSFET located in an end of the MOSFET array and the source of the MOSFET located in another end is grounded, and the reference voltage is a voltage obtained by dividing by the plurality of MOSFETs of the MOSFET array at a predetermined ratio.

Abstract: In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

Abstract: According to an exemplary embodiment of the present invention, a diffusion tube includes a diffusion housing which includes a first cavity within a first end which receives a diffusion target, a second cavity within a second end which receives a dopant source for diffusion, and a diffusion port disposed between the diffusion target and the dopant source, wherein the diffusion port provides fluid communication between the first cavity and the second cavity.

Abstract: A method and device for alternately contacting two wafer-like component composite arrangements (12, 14) consisting of a plurality of cohesively designed similar components, in particular of a semiconductor wafer with a function component wafer for manufacturing electronic modules on a wafer level, in which the two component composite arrangements, each provided with contact metallizations on their opposing contact surfaces (38, 39), are brought into a coverage position with their contact metallizations to form contact pairs, in which position the contact metallizations that are to be joined together are pressed against one another, the contact metallizations being thereby contacted by exposing the rear of one of the component composite arrangements (12) to laser radiation (20), the wavelength of the laser radiation being selected as a function of the degree of absorption of the component composite arrangement exposed to laser radiation at the rear, so that a transmission of the laser radiation through the com

Abstract: A first semiconductor chip includes a fixed electrode formed on a first semiconductor substrate and a plurality of first metal spacers formed on a first interlayer dielectric. A second semiconductor chip includes a vibrating electrode formed on a second semiconductor substrate and a plurality of second metal spacers formed on a second interlayer dielectric. The first and second semiconductor chips are metallically bonded to each other using the first and second metal spacers. An air gap is formed in a region of the condenser microphone located between the first semiconductor chip and the second semiconductor chip except bonded regions of the first and second metal spacers.

Abstract: The present invention creates an optical sensor assemblage, in particular a thermopile sensor assemblage, comprising a sensor chip assemblage (10; 10?) having an optically transparent irradiation region (OB; OB?), a mounting region (RB; RB?) surrounding the latter, and a wire-bond region (BB); an optically isolating mounting frame (MLF; MLF?) having a chip receiving region (DP; DP?) and a plurality of connector elements (AB-AB??); and an optically isolating packaging device (MV-MV??); the sensor chip assemblage (10; 10?) being joined in the mounting region (RB; RB?) to the chip receiving region (LB; LB?), and in the wire-bond region (BB) to one or more of the connector elements (AB-AB??); the chip receiving region (DP, DP?) having a window (F; F?) disposed in such a way that at least a portion of the optical irradiation region (OB; OB?) is not covered by the chip receiving region (DP; DP?); and the packaging device (MV-MV??) surrounding the sensor chip assemblage (10; 10?) and the mounting frame (MLF; MLF?) i

Abstract: A sensor semiconductor device is proposed. A plurality of metal bumps and a sensor chip are mounted on a substrate. A dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the metal bumps and the sensor chip. Thus, the sensor chip is electrically connected to the substrate via the circuit layer and the metal bumps. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid covers the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. A plurality of solder balls are mounted on a surface of the substrate free of mounting the sensor chip, for electrically connecting the sensor chip to an external device.

Abstract: A photosensitive device is provided. The photosensitive device can be an image sensor or a solar cell. The photosensitive device includes a driving circuit such as photo sensor circuit or solar cell circuit, and a nano-crystal layer. The nano-crystal layer is located above the driving circuit and includes a silicon compound layer and plural nano-crystal particles. The nano-crystal particles are distributed in the silicon compound layer and capable of capturing photon and further converting into photocurrent.

Abstract: A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.

Abstract: With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor substrate 10, a wiring substrate 20, conductive bumps 30, and a resin 32. A CCD 12 and a thinned portion 14 are formed on semiconductor substrate 10. Electrodes 16 of semiconductor substrate 10 are connected via conductive bumps 30 to electrodes 22 of wiring substrate 20. Insulating resin 32 fills a gap between outer edge 15 of thinned portion 14 and wiring substrate 20 to reinforce the bonding strengths of conductive bumps 30. This resin 32 is a resin sheet that has been formed in advance so as to surround a periphery of a gap between thinned portion 14 and wiring substrate 20 except for portions of the periphery.

Abstract: With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor substrate 10, a wiring substrate 20, conductive bumps 30, and a resin 32. A CCD 12 and a thinned portion 14 are formed on semiconductor substrate 10. Electrodes 16 of semiconductor substrate 10 are connected via conductive bumps 30 to electrodes 22 of wiring substrate 20. Wiring substrate 20 is subject to a wettability processing by which a region 26a that surrounds a region opposing thinned portion 14 and regions 26b that extend to the outer side from region 26a are lowered in the wettability with respect to the resin.

Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on- resistance and breakdown voltage.

Abstract: A semiconductor fabrication method comprises steps of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.

Abstract: A system-on-chip semiconductor structure. The system-on-chip semiconductor structure comprises a substrate, a low voltage device, a middle voltage device, at least one high voltage device and a plurality of isolation structures. The substrate has a low voltage circuit region and a high voltage circuit region. The low voltage device is located on the low voltage circuit region of the substrate. The middle voltage device is located on the low voltage circuit region of the substrate. The high voltage device is located on the high voltage circuit region of the substrate. The isolation structures are located in the substrate for isolating the low voltage device, the middle voltage device and the high voltage device from each other.

Abstract: An integrated circuit device is provided with a plurality of normally open fuse elements. A fuse element includes a fuse insulation film lining a sidewall and a bottom of a recess in a semiconductor substrate. A semiconductor fuse region of first conductivity type (e.g., N-type) is provided in the semiconductor substrate. The semiconductor fuse region extends to the sidewall of the recess. A fuse conductor is provided on a portion of the fuse insulation film extending opposite the semiconductor fuse region. A voltage induced rupture in the fuse insulation film results in a direct electrical connection between the fuse conductor and the semiconductor fuse region.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device is provided. The method includes the steps of forming a first insulating layer on a top surface of a semiconductor substrate having a plurality of patterns, immediately before gaps between the patterns are completely closed; forming a lower insulating film by isotropically etching the first insulating layer for a specific amount of time, such that aspect ratios of the gaps between the patterns are reduced; forming a second insulating layer on the lower insulating film such that the gaps between the patterns are completely filled with the second insulating film; and forming an upper insulating film by planarizing the second insulating layer.

Abstract: The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.

Abstract: A method of fabricating an MIM type capacitor includes at least one of: Forming a first trench within an insulating interlayer formed on a semiconductor substrate. Forming a lower electrode layer of a metal nitride layer substance to fill an inside of the first trench. Forming a second trench on a surface of the lower electrode layer to have a depth less than the first trench. Forming a capacitor dielectric layer conformal along a surface of the lower electrode layer including the second trench. Forming an upper electrode layer of a metal nitride layer substance on the capacitor dielectric layer. Sequentially patterning the upper electrode layer and the capacitor dielectric layer by photolithography.

Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.

Abstract: The invention relates to NPN and PNP bipolar transistors and to a method for the production thereof, said transistors being characterised by a particularly high collector-emitter and collector-base blocking voltage. The blocking voltage is increased by a particular doping profile. An NPN bipolar transistor comprises a p-doped substrate (1), a trenched n-doped layer (3) forming the collector, a p-doped layer (7) which is arranged above the trenched n-doped layer and is made of a base and an n-doped layer which is arranged within the p-doped layer and forms an emitter of the transistor. A spatial charge area (RLZ 1) is formed between the p-doped layer and the trenched n-doped layer and a second spatial charge area (RLZ 2) is formed between the trenched n-doped layer and the p-doped substrate, which expands in the vertical direction on the collector when the transistor is operated with an increasing potential.

Abstract: A multilayer dielectric substrate that mounts a semiconductor device in a cavity formed on a substrate. The multilayer dielectric substrate includes an opening formed in a surface-layer grounding conductor on the substrate in the cavity, and an impedance transformer, with a length of about ¼ of an in-substrate effective wavelength of a signal wave, electrically connected through the opening to the cavity. The multilayer dielectric substrate further includes a short-circuited end dielectric transmission line with a length of about ¼ of the in-substrate effective wavelength of the signal wave, a coupling opening formed on an inner-layer grounding conductor in a connecting section of the impedance transformer and the dielectric transmission line, and a resistor formed in the coupling opening.

Abstract: Two DBC wafers have patterned first conductive surfaces which receive a semiconductor die in sandwich fashion. Lead frame terminally extending into the package interior and are connected to the die terminals. The outer conductive surfaces of each of the wafers are available for two-sided cooling of the semiconductor.

Abstract: The semiconductor device whose structure is formed from a die attached to a leadframe comprises a die having an attachment member, and a leadframe having a recess configured to receive a corresponding attachment member so as to establish a connection between the die and the leadframe.

Abstract: A method for fabricating a module having an electrical contact-connection is disclosed. One embodiment provides a chip having a contact area, applying a contact elevation to the contact area and applying a solder material to the contact elevation. The contact elevation may be applied to the contact area by using a bonding process in order to implement the contact elevation in the form of a stud bump.

Abstract: A semiconductor device comprising, a layer on which a semiconductor element is arranged, an insulation layer on which a wiring connected to the semiconductor element is arranged, dummy metal plates arranged in the insulation layer, wherein the dummy metal plates have an aspect ratio larger than 1, and are arranged substantially perpendicularly to the wiring.

Abstract: Embodiments of the present disclosure provide systems and methods for producing micro electro-mechanical device packages. Briefly described, in architecture, one embodiment of the system, among others, includes a micro electro-mechanical device formed on a substrate layer; and a thermally decomposable sacrificial structure protecting at least a portion of the micro electro-mechanical device, where the sacrificial structure is formed on the substrate layer and surrounds a gas cavity enclosing an active surface of the micro electro-mechanical device. Other systems and methods are also provided.

Abstract: A System in Package (SIP) module. The module includes a printed circuit board with at least one cavity formed therein. The module also includes at least one first device mounted in the cavity and a circuit pattern formed on an undersurface of the cavity and electrically connected to the first device. The module further includes at least one second device mounted on a printed circuit board surface corresponding to the undersurface of the cavity.

Abstract: A semiconductor device 1 includes a semiconductor chip 10. Each of the semiconductor chips 10 includes a semiconductor substrate 12, a semiconductor layer 14 and an interconnect layer 16. The semiconductor substrate 12 has a specific resistance ?1 (first specific resistance). A semiconductor layer 14 is provided on the semiconductor substrate 12. Such semiconductor layer 14 exhibits a specific resistance ?2 (second specific resistance). The relationship of these specific resistances is: ?2<?1. The interconnect layer 16 is provided on the semiconductor layer 14. An inductor 18 for transmitting and receiving signals with an external element outside the semiconductor chip 10 is provided in the interconnect layer 16.

Abstract: A semiconductor die has devices such as MOSgated devices, diodes and the like formed into the top and bottom surfaces of the die. One terminal of each of the devices terminal in the interior center of the die and a common contact is made to the interior center of the die at one edge of the die. Various packages for the die having a reduced foot print on a support substrate are disclosed.

Abstract: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved.

Abstract: It is made possible to provide a highly integrated, thin apparatus can be obtained, even if the apparatus contains MEMS devices and semiconductor devices. A semiconductor apparatus includes: a first chip comprising a MEMS device formed therein; a second chip comprising a semiconductor device formed therein; and an adhesive layer bonding a side face of the first chip to a side face of the second chip, and having a lower Young's modulus than the material of the first and second chips.