Abstract: Compositions and methods for protecting a plant from a pathogen, particularly a fungal pathogen, are provided. Compositions include novel amino acid sequences, and variants and fragments thereof, for antipathogenic polypeptides that were isolated from microbial fermentation broths. Nucleic acid molecules comprising nucleotide sequences that encode the antipathogenic polypeptides of the invention are also provided. A method for inducing pathogen resistance in a plant using the nucleotide sequences disclosed herein is further provided. The method comprises introducing into a plant an expression cassette comprising a promoter operably linked to a nucleotide sequence that encodes an antipathogenic polypeptide of the invention. Compositions comprising an antipathogenic polypeptide or a transformed microorganism comprising a nucleic acid of the invention in combination with a carrier and methods of using these compositions to protect a plant from a pathogen are further provided.

Abstract: When a dry analysis element contained in an element cartridge to be loaded in a sample tray of an automatic analysis apparatus projects from a take out port, the element is returned to its proper position, thereby preventing conveyance failure and information readout failure, with the result that higher operation reliability is ensured. An element mounting portion is equipped with a correcting means, such as a restricting projection. The correcting means contacts and pushes a dry analysis element which projects from an element cartridge back to its predetermined position therein, in association with a loading operation of the element cartridge.

Abstract: Method for determining deposit formation tendencies for a plurality of fluid samples of different compositions is provided. Each sample includes one or more lubricating oil compositions containing at least one or more base oils of lubricating viscosity and one or more lubricating oil additives. The methods can advantageously be optimized using combinatorial chemistry, in which a database of combinations of lubricating oil compositions are generated. As market conditions vary and/or product requirements or customer specifications change, conditions suitable for forming desired products can be identified with little or no downtime.

Abstract: The present invention relates to an in vitro diagnostic method for patients with suspected deep venous thrombosis wherein by combined testing of patients' samples for D-dimer and CRP both the sensitivity and the negative predictive value of DVT diagnostics can be increased up to 100%.

Abstract: The invention relates to a composition for the stabilization of sulphur-containing amino acids and/or for the inhibition of the continuous formation of sulphur-containing amino acids in withdrawn blood, to the use of suitable substances and compositions therefor as well as optionally for the determination of sulphur-containing amino acids in blood, to a process for these purposes, as well as to a blood collecting device applied appropriately to these processes.

Abstract: A measuring apparatus and method for use in measuring diffusible hydrogen concentrations in materials, structures, and other objects. In an embodiment of the invention for use in welding applications, the measuring apparatus (10) includes a sensor assembly (20) that, with an included sealing member (40), defines a sample area (17) on a weld bead (16) from which hydrogen evolves into a sample volume (18) defined by the sealing member (40), a sensor housing (34) and a sensor (22) of the sensor assembly (20). The hydrogen reacts with a sensing layer (28) and a reflector layer (30) positioned on the end of an optical fiber (24), all of which are included in the sensor assembly (20) and are sealably positioned within the sensor (22).

Abstract: A method for determination of at least one of the triglyceride molecular species in a biological sample comprising the subjecting sample to lipid extraction to obtain a lipid extract and subjecting the resulting lipid extract to 2D electrospray ionization tandem mass spectrometry (ESI/MS/MS) with neutral loss scanning of all naturally occurring aliphatic chains and contour analysis of 2D intercept peaks. A method for determination of tricylglyceride content and/or TG molecular species directly from a lipid extract of a biological sample comprising subjecting said lipid extract to electrospray ionization tandem mass spectrometry.

Abstract: A method of determining the cause of disease is described, which method uses the detection of “signature” or “fingerprint” volatile compounds in an emission, especially flatus, from a patient.

Abstract: MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching reliability may be achieved by altering the shape of the layered magnetic stack structure. Forming recessed regions with sloped interior walls in an ILD layer prior to depositing the layered magnetic stack structure produces a significant advantage over the prior art by allowing a CMP process to be used to define the magnetic bit shapes. The sloped interior walls of the recessed regions, which is singular to the present invention, provide a unique formation and shaping of the magnetic stack structure, which may reduce the magnetic coupling effect between magnetic layers of the magnetic stack structure.

Abstract: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the structural pattern is bonded to a carrier wafer with a bonding layer, and a plurality of back scribe lines are defined on the back surface of the wafer. Finally, the filling layer filled in the front scribe lines is removed.

Abstract: A variable temperature and/or reactant dose atomic layer deposition (VTD-ALD) process modulates ALD reactor conditions (e.g., temperature, flow rates, etc.) during growth of a film (e.g., metallic) on a wafer to produce different film properties a different film depths.

Abstract: A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

Abstract: A composite monitor is capable of determining a variety of defects of a semiconductor device. The composite monitor has an isolation region in a well region, an active region pattern in the well region and defined by the isolation region, and a metal line pattern partially overlying the active region pattern. The composite monitor further has an optional well region pad electrically coupled to the well region and separated from the metal line pattern, an active region pad electrically coupled to the active region pattern and separated from both the metal line pattern and the well region pad, a metal line pad electrically coupled to the metal line pattern and separated from both the well region pad and the active region pad, and a first contact between the active region pattern and the metal line pattern to provide an electrical path therebetween.

Abstract: This disclosure concerns methods for fabrication of integrated high speed optoelectronic devices. In one example of such a method, a device region that includes a top surface and a bottom surface is formed on a top surface of a substrate. The device region may take the form of an optical emitter, such as a VCSEL, or a detector, such as a photodiode. Next, an isolation region is formed that is configured such that the device region is surrounded by the isolation region. A superstrate is then disposed on the top surface of the device region. Finally, a micro-optical device, such as a lens, is placed on a top surface of the superstrate.

Abstract: The invention concerns a light-emitting diode chip comprising a radiation-emitting active region and a window layer. To increase the luminous efficiency, the cross-sectional area of the radiation-emitting active region is smaller than the cross-sectional area of the window layer available for the decoupling of light. The invention is further directed to a method for fabricating a lens structure on the surface of a light-emitting component.

Abstract: The present invention provides an optical device and a surface emitting type device which have high efficiency and a stable operation and are manufactured at high manufacturing yield. The optical device and the surface emitting type device are characterized in that they have a distributed Bragg reflector (DBR) including a plurality of semiconductor layers made of a nitride semiconductor with substantially same gaps therbetween. Further, the optical device and the surface emitting type device are characterized in that they have a distributed Bragg reflector (DBR) in which a plurality of semiconductor layers made of nitride semiconductor and a plurality of organic layers made of organic material are alternately laminated.

Abstract: A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).

Abstract: Methods are disclosed generally directed to design and synthesis of quantum dot nanoparticles having improved uniformity and size. In a preferred embodiment, a release layer is deposited on a semiconductor wafer. A heterostructure is grown on the release layer using epitaxial deposition techniques. The heterostructure has at least one layer of quantum dot material, and optionally, one or more layers of reflective Bragg reflectors. A mask is deposited over a top layer and reactive ion-beam etching applied to define a plurality of heterostructures. The release layer can be dissolved releasing the heterostructures from the wafer. Some exemplary applications of these methods include formation of fluorophore materials and high efficiency photon emitters, such as quantum dot VCSEL devices. Other applications include fabrication of other optoelectronic devices, such as photodetectors.

Abstract: The present invention relates to a method of manufacturing a vertically-structured GaN-based light emitting diode. The method of manufacturing a vertically-structured GaN-based light emitting diode includes forming a GaN layer on a substrate; patterning the compound layer in a predetermined shape; forming an n-type GaN layer on the patterned compound layer through the epitaxial lateral over-growth process and sequentially forming an active layer and a p-type GaN layer on the n-type GaN layer; forming a structure supporting layer on the p-type GaN layer; sequentially removing the substrate and the GaN layer formed on the substrate after forming the structure supporting layer; removing the patterned compound layer exposed after removing the GaN layer so as to form an n-type GaN layer patterned in a concave shape; and forming an n-type electrode on the n-type GaN layer patterned in a concave shape.

Abstract: A first electrode thin film is formed on an upper surface of the oxygen ion conductive thin film so as to have a through hole. A resistor is formed on part of the upper surface of the oxygen conductive thin film located in the through hole. Thus, the oxygen ion conductive thin film can be directly heated by the resistor, so that oxygen ions can be speedily transferred with a low power. Therefore, the oxygen ion conductivity of the oxygen ion conductive thin film can be improved.

Abstract: In a method for manufacturing a semiconductor component having a semiconductor substrate, a flat, porous diaphragm layer and a cavity underneath the porous diaphragm layer are produced to form unsupported structures for a component. In a first approach, the semiconductor substrate may receive a doping in the diaphragm region that is different from that of the cavity. This permits different pore sizes and/or porosities to be produced, which is used in producing the cavity for improved etching gas transport. Also, mesopores may be produced in the diaphragm region and nanopores may be produced as an auxiliary structure in what is to become the cavity region.

Abstract: A method of manufacturing high temperature thermistors from an ingot. The high temperature thermistors can be comprised of germanium or silicon. The high temperature thermistors have at least one ohmic contact.

Abstract: The invention relates to an organically based photovoltaic element, in particular a solar cell comprising a photovoltaically active layer whose absorption maximum can be shifted into the longer wavelength region and/or whose efficiency can be increased.

Abstract: A method is disclosed for making a metal electrode which minimizes the contact resistance between it and an organic semiconductor. Acid-stabilized metal nanoparticles are deposited upon a substrate and annealed. This creates a metal electrode and releases acid. Upon deposition of semiconductor and subsequent annealing, the acid diffuses from the electrode into the semiconductor layer and acts as a dopant, minimizing the contact resistance. The use of oleic acid-stabilized silver nanoparticles is demonstrated.

Abstract: A method for manufacturing an organic electronic device including a stack of layers with a lateral structure on a substrate, at least one of the layers being an organic material layer. A method includes with the step of providing a stamp with at least one protrusion of the surface area corresponding to the lateral structure. The stack of layers is deposited with a first face on the surface area of the protrusion of the stamp. A second face of the stack that is opposite to the first face is brought into adhesive contact with the substrate. The stamp is released from the stack.

Abstract: Individual pieces of film adhesive (42) are placed on a support surface (46). Diced semiconductor chips (24) are individually placed on the individual pieces of the film adhesive thereby securing the diced semiconductor chips to the support surface to create first chip subassemblies (52). The diced semiconductor chip and support surface of each of a plurality of the first chip subassemblies are electrically connected, such as by wires (54), to create second chip subassemblies ((56). At least a portion of at least some of the second chip subassemblies are encapsulated, such as with molding compound (58), to create semiconductor chip packages (60).

Abstract: The invention realizes excellent electrical and mechanical connection between electrodes in a packaging structure where a plurality of semiconductor chips having electrodes are connected with each other through the low-melting metallic members. Bump electrodes are formed on a front surface of a first semiconductor chip. Penetrating holes are formed in a second semiconductor chip, and a penetrating electrode having a gap in a center is formed in each of the penetrating holes. Low-melting metallic members are interposed between connecting surfaces of the bump electrodes and the penetrating electrodes, and a part of each of the low-melting metallic members flows in each of the gaps of the penetrating electrodes when dissolved. This prevents short-circuiting between the bump electrodes which is caused by oversupplying the low-melting metallic members between the adjacent bump electrodes.

Abstract: A semiconductor multi-package module includes a processor and a plurality of memory packages mounted on a surface of the multipackage module substrate. In some embodiments the memory packages include stacked die packages, and in some embodiments the memory packages include stacked memory packages. In some embodiments the processor is situated at or near the center of the multipackage module substrate and the plurality of memory packages or of stacked memory package assemblies are situated on the multipackage module substrate adjacent the processor.

Abstract: Packaged microelectronic devices, methods for packaging microelectronic devices, and methods of operating microelectronic devices. In one embodiment, a packaged microelectronic device comprises a die including integrated circuitry, a first casing coating at least a portion of the die, a heat sink proximate to the die, and a second casing on at least a portion of the heat sink and coating at least a portion of the first casing. The first casing has a plurality of first interconnect elements, and the second casing engages the first interconnect elements to the first casing. The interconnect elements can be surface striations or other features that project into or away from the first casing. For example, the interconnect elements can be ridges extending across a surface of the first casing. In other embodiments, the first interconnect elements can be bumps and/or dimples across the surface of the first casing.

Abstract: The invention provides apparatus and methods for sawing and singulating individual devices from a silicon or glass-bonded semiconductor wafer. Using methods of the invention, wafer device singulation includes a step of sawing kerfs approximately coinciding with the peripheries of numerous devices arranged on a wafer. Kerfs are also sawn into the opposite side of the wafer approximately opposing the first kerfs. Mechanical stress is applied to the wafer causing controlled breakage of the intervening wafer material, severing each of the devices from its neighbors. A saw blade apparatus of the invention provides enhanced cutting characteristics and is particularly suited for glass-bonded semiconductor wafer device singulation. The saw blade has a diamond disc suitable for high-speed rotation about its axis. The saw blade of the invention also preferably has a radiused cutting edge, and an annular gutter symmetrically disposed about the circumference on each of the opposing planes of the disc.

Abstract: During the formation of an underfill material provided between a carrier substrate and a semiconductor chip, a common motion of particles contained in the underfill material is initiated towards the semiconductor chip, thereby adjusting the thermal and mechanical behavior of the underfill material. For instance, by applying an external force, such as gravity, a depletion zone with respect to the filler particles may be created in the vicinity of the carrier substrate, while a high particle concentration may be obtained in the vicinity of the semiconductor chip. Hence, thermal and mechanical stress redistribution by means of the underfill material may be enhanced.

Abstract: Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

Abstract: The present invention provides a highly stable light emitting device having high light-emitting efficiency (light-extraction efficiency) with high luminance and low power consumption, and a method of manufacturing thereof. A partition wall and a heat-resistant planarizing film are formed of a same material so as to be well-adhered to each other, thereby reducing material costs. Either an anode or a cathode is formed on the heat-resistant planarizing film. The partition wall and the heat-resistant planarizing film is adhered to each other without inserting a film having different refractive index therebetween, and therefore reflection of light is not caused in an interface.

Abstract: A method of fabricating a thin film transistor substrate for a display device is provided.

Abstract: A number of minuscule LDD thin film transistors with high precision are arranged on a substrate for use in a liquid crystal display apparatus or other similar devices. The gate electrode is used as a mask at the time of injecting impurities into the semiconductor layer. To realize an LDD structure, the impurities are injected in two installments. The size of the gate electrode is changed in accordance with the length of the LDD regions between the first and second injections. The size of the gate electrode is changed by means of metal oxidation or dry etching. For precision dry etching of the gate electrode, various ideas are put into forming the photo resist.

Abstract: It is an object of the invention that, in semiconductor device, in order to promote the tendency of miniaturization of each display pixel pitch, which will be resulted in with the tendency toward the higher precision (increase of pixel number) and further miniaturizations, a plurality of elements is formed within a limited area and the area occupied by the elements is compacted so as to be integrated. A plurality of semiconductor layers 13, 15 is formed on different layers with insulating film 14 sandwiched therebetween. After carrying out crystallization by means of laser beam, on each semiconductor layer (semiconductor layers 16, 17 having crystal structure respectively), an N-channel type TFT of inversed stagger structure and a P-channel type TFT 30 of top gate structure are formed respectively and integrated so that the size of CMOS circuit is miniaturized.

Abstract: It is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least 600° C.) and the employment of lower temperature processes (600° C. or lower), and to achieve step simplification and throughput improvement. In the present invention, a barrier layer (105), a second semiconductor film (106), and a third semiconductor layer (108) containing an impurity element (phosphorus) that imparts one conductive type are formed on a first semiconductor film (104) having a crystalline structure. Gettering is carried out in which the metal element contained in the first semiconductor film (104) is allowed to pass through the barrier layer (105) and the second semiconductor film (106) by a heat treatment to move into the third semiconductor film (107). Afterward, the second and third semiconductor films (106) and (107) are removed with the barrier layer (105) used as an etching stopper.

Abstract: The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a protective layer to a device, applying a first silicon nitride liner to the device, removing a portion of the first silicon nitride liner, removing a portion of the protective layer, and applying a second silicon nitride liner to the device.

Abstract: For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.

Abstract: A gate insulating film having an insulating film that contains at least nitrogen is formed on a substrate, and the gate insulating film is subjected to heat treatment for about 500 milliseconds or less using a flash lamp. Thereafter, a gate electrode is formed on the gate insulating film. Specifically, for example, a laminated film of SiO2 film and an SixN(1-x) film, a laminated film of an SiO2 film, HfSiO film, and an SixN(1-x) film, or the like, is formed in forming the gate insulating film.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form atop electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A capacitor structure and a method of fabricating the capacitor structure wherein. The lower electrode and the upper electrode are constructed to be separated from each other by a predetermined interval and to be engaged with each other using a series of alternating ridges so that an effective surface area can increase within a limited area.

Abstract: Methods of making memory devices/cells are disclosed. A memory cell contains first and second electrode layers and a controllably conductive media therebetween. The controllably conductive media contains a copper sulfide-containing passive layer and active layer containing a Cu-doped tantalum oxide and/or titanium oxide layer. Methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.

Abstract: A fabricating method of a semiconductor device includes: forming a first metal layer on a substrate and patterning the first metal layer to form a bottom metal line and a bottom electrode of a capacitor; forming an interlayer insulating layer on the resulting structure; forming a via hole in the interlayer insulating layer and forming a contact; etching the interlayer insulating layer to form a trench exposing the bottom electrode; forming a dielectric layer on the resulting structure, and removing the dielectric layer formed outside the trench; and forming a second metal layer on the resulting structure to form a top metal line and a top electrode of the capacitor.

Abstract: An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavity (6), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate (7) side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer (5) by Coulomb interactive force between the electrons (or positive holes 8) accumulated in the floating gate layer (5) and external electric field, and by reading the channel current change based on the state of the floating gate layer (5).

Abstract: A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.

Abstract: A flash memory device includes control gates that are formed to completely surround the top and sides of floating gates. The control gates are located between the floating gates that are adjacent in the word line direction as well as the floating gates that are adjacent in the bit line direction. The present flash memory device reduces a shift in a threshold voltage resulting from interference among floating gates and increases an overlapping area of the floating gate and the control gates. Thus, there is an effect in that the coupling ratio can be increased.

Abstract: A method for fabricating a semiconductor device with a recessed channel, including the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor substrate having the trenches; forming a gate conductive layer on the entire surface of the resulting structure so that the trenches are buried; forming a silicon-rich amorphous metal silicide layer having seams on the gate conductive layer; filling the seams of the silicon-rich amorphous metal silicide layer with a metal thin film; forming a gate hard mask on the silicon-rich amorphous metal silicide layer and the metal thin film; patterning the gate insulating layer, the gate conductive layer, the silicon-rich amorphous metal silicide layer and the gate hard mask to form gate stacks; and thermally processing the silicon-rich amorphous metal silicide layer and the metal thin film to form a crystallized metal silicide layer.

Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

Abstract: An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.