Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract: A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.

Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element.

Abstract: A capacitor for a semiconductor device includes a first inter metal dielectric layer is disposed on a substrate. A first electrode is disposed on the first inter metal dielectric layer. A second electrode partially overlaps the first electrode. A first dielectric layer is disposed between the first and second electrodes. A third electrode partially overlaps the second electrode. A second dielectric layer is disposed between the second and third electrodes. An etch stop layer is disposed on the first, second, and third electrodes. A second inter metal dielectric layer is formed on the etch stop layer and includes first, second, and third via holes exposing the first and third electrodes and the etch stop layer. First, second, and third plugs are disposed in the first, second, and third via holes.

Abstract: A method of wafer repairing comprises identifying locations and patterns of defective regions in a semiconductor wafer; communicating the locations and patterns of defective regions to a direct-writing tool; forming a photoresist layer on the semiconductor wafer; locally exposing the photoresist layer within the defective regions using an energy beam; developing the photoresist layer on the semiconductor wafer; and wafer-processing the semiconductor wafer under the photoresist layer after exposing and developing.

Abstract: A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

Abstract: A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.

Abstract: A method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices is disclosed. The method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices includes the following steps: (a) providing a substrate, (b) fixing the substrate, (c) applying a stress upon the substrate, and (d) inducing a strain in one of a device and a circuit by stressing the substrate.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: It is an object of the present invention to provide a technology to manufacture a semiconductor sheet or a semiconductor chip with a high yield using a circuit having a thin film transistor. A manufacturing method for a semiconductor device comprises: attaching a flexible base material to an element layer x times (x is an integer number of 4 or more), wherein a thickness of a base material which is attached to the element layer (y+1)th (y is an integer number of 1 or more and less than x) time is the same or smaller than that of a base material which is attached to the element layer y-th (y is an integer number of 1 or more and less than x) time.

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 ?m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract: Methods of forming a cell pad contact hole on an integrated circuit include forming adjacent gates on an integrated circuit substrate having a source/drain region extending between the gates. Gate spacers are formed on facing sidewalls of the adjacent gates. A cell pad contact hole is formed aligned to the gates and gate spacers that exposes the source/drain region in the integrated circuit substrate. A first poly film is formed in the cell pad contact hole. An ion region is formed in the source/drain region by ion-implanting through the first poly film and a second poly film is formed on the first poly film that substantially fills the cell pad contact hole.

Abstract: A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.

Abstract: A method for processing a semiconductor substrate less than 200 ?m thick has been provided. The substrate has one or a plurality of semiconductor elements, which may be identical or different. The substrate is arranged onto a chuck during processing, the front side of the substrate facing the chuck. During processing, an electrically conductive film, for example, made of metal, may be applied on the rear side of the substrate. The film may serve as electrical contact, heat sink or mechanical stabilizer.

Abstract: A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

Abstract: A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the etch stop layer. The layer of contact material is patterned to form posts. Dielectric is deposited over and between the posts, then the dielectric planarized to expose the tops of the posts. The posts can serve as vertical interconnects which electrically connect a next conductive layer formed on and in contact with the vertical interconnects with the underlying etch stop layer. The patterned dimension of vertical interconnects formed according to the present invention can be substantially the same as the minimum feature size, even at very small minimum feature size.

Abstract: A method for etching to form a planarized surface is disclosed. Spaced-apart features are formed of a first material, the first material either conductive or insulating. A second material is deposited over and between the first material. The second material is either insulating or conductive, opposite the conductivity of the first material. The second material is preferably self-planarizing during deposition. An unpatterned etch is performed to etch the second material and expose the top of the buried features of the first material. The etch is preferably a two-stage etch: The first stage is selective to the second material. When the second material is exposed, the etch chemistry is changed such that the etch is nonselective, etching the first material and the second material at substantially the same rate until the buried features are exposed across the wafer, producing a substantially planar surface.

Abstract: A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.

Abstract: The CD uniformity of a damascene pattern and the reliability of interconnection lines may be enhanced when a semiconductor device is manufactured by a method including: forming a first insulating layer on a semiconductor substrate, the first insulating layer having a contact hole partially exposing the substrate; forming a photoresist layer filling the contact hole; removing the photoresist layer such that the first insulating layer is exposed and a recess is formed in the contact hole; reducing, removing or substantially eliminating the recess by removing an upper portion of the first insulating layer; forming a second insulating layer having a trench exposing the photoresist layer and a portion of the first insulating layer adjacent thereto; and removing the remaining photoresist layer.

Abstract: A processing method for the metal surface in a dual damascene manufacturing is applied to a dual damascene semiconductor structure. The dual damascene semiconductor structure has a metal structure and a spin-on-dielectric (SOD) layer formed on the metal structure, wherein the SOD layer has at least one opening exposing a partial surface of the metal structure. Before the opening is filled, the monoxide on the exposed surface is first removed, then the exposed surface is treated by the plasma at an angle inclined to an axis perpendicular to the exposed surface. The processing method provided in the present invention can avoid the exposed surface being damaged by the plasma and improve the adhesion force between the exposed metal surface and the stuff.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device includes a silicon substrate, a source region and a drain region. A gate electrode is formed on the silicon substrate. Also, a metal silicide layer is formed on each of the gate electrode, the source region, and the drain region. The metal silicide layer has a thickness uniformity of about 1˜20%. A disclosed fabrication method includes forming a metal layer on a silicon substrate having a gate electrode, a source region, and a drain region; performing a plasma treatment on the metal layer; forming a protective layer on the metal layer; and heat treating the silicon substrate on which the protective layer is formed to thereby form a metal silicide layer. A gas that includes nitrogen is used as a plasma gas during the plasma treatment.

Abstract: A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer is removed by using the patterned mask layer as a mask and a spacer is formed on a sidewall of the patterned mask layer and the conductive layer. A portion of the conductive layer is removed until the material layer is exposed to form a conductive line, wherein the spacer and the patterned mask layer serve as a mask.

Abstract: A method for treating a fluoro-carbon dielectric film for integration of the dielectric film into a semiconductor device. The method includes providing a substrate having a fluoro-carbon film deposited thereon, the film having an exposed surface containing contaminants, and treating the exposed surface with a supercritical carbon dioxide fluid to clean the exposed surface of the contaminants and provide surface termination. The supercritical carbon dioxide treatment improves adhesion and electrical properties of film structures containing a metal-containing film formed on the surface of the fluoro-carbon dielectric film.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A layer of required material, such as polysilicon, is planarized by first forming a sacrificial layer of material, such as an oxide, on the layer of required material. The combined layers of required and sacrificial materials are then planarized using chemical-mechanical polishing until the sacrificial material has been substantially, completely removed.

Abstract: A method of treating a conductive layer to assure enhanced adhesion of the layer to selected dielectric layers used to form a circuitized substrate. The conductive layer includes at least one surface with the appropriate roughness to enable such adhesion and also good signal passage if the layer is used as a signal layer. The method is extendible to the formation of such substrates, including to the formation of multilayered substrates having many conductive and dielectric layers. Such substrates may include one or more electrical components (e.g., semiconductor chips) mounted thereon and may also be mounted themselves onto other substrates.

Abstract: A method for polishing a Cu film comprises contacting a Cu film formed above a semiconductor substrate with a polishing pad attached to a turntable, and supplying a first chemical liquid which promotes the polishing of the Cu film and a second chemical liquid which contains a surfactant, to the polishing pad while the turntable being rotated, thereby polishing the Cu film, while monitoring at least one of a table current of the turntable and a surface temperature of the polishing pad to detect a change in at least one of the table current of the turntable and the surface temperature of the polishing pad. The supply of the second chemical liquid is controlled in conformity with the change.

Abstract: A flash memory and a fabrication method thereof, which is capable of improving a whole capacitance of the flash memory by forming a tunneling oxide and a floating gate only in a portion where injection of electrons occurs. A flash memory wherein a tunneling oxide and a floating gate are formed only in a portion where injection of electrons occurs and a gate insulation film is formed on a semiconductor substrate between two portions of the tunneling oxide.

Abstract: A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.

Abstract: According to the present invention, a wet chemical oxidation and etch process cycle allows efficient removal of contaminated silicon surface layers prior to the epitaxial growth of raised source and drain regions, thereby effectively reducing the total thermal budget in manufacturing sophisticated field effect transistor elements. The etch recipes used enable a controlled removal of material, wherein other device components are not unduly degraded by the oxidation and etch process.

Abstract: A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.

Abstract: Disclosed is a film-forming method, comprising supplying into a plasma processing chamber at least three kinds of gases including a silicon compound gas, an oxidizing gas, and a rare gas, the percentage of the partial pressure of the rare gas (Pr) based on the total pressure being not smaller than 85%, i.e., 85%?Pr<100%, and generating a plasma within the plasma processing chamber so as to form a film of silicon oxide on a substrate to be processed.

Abstract: A plasma treatment apparatus and a method for plasma treatment are provided that made possible to control accurately a distance between plasma and an object to be treated (hereinafter referred to as an object), and that facilitated a transportation of a substrate that a width is thin and grown in size. The plasma treatment apparatus of the present invention is provided with a gas supply means for introducing a processing gas into a place between a first electrode and a second electrode under an atmospheric pressure or around atmospheric pressure; a plasma generation means for generating plasma by applying a high frequency voltage to the first electrode or the second electrode under the condition that the processing gas is introduced; and, a transport means for transporting the object by floating the object by blowing the processing gas or a transporting gas to the object.

Abstract: The method for forming a quantum dot according to the present invention comprises the step of forming an oxide in a dot-shape on the surface of a semiconductor substrate 10, the step of removing the oxide to form a concavity 16 in the position from which the oxide has been removed, and the step of growing a semiconductor layer 18 on the semiconductor substrate with the concavity formed in to form a quantum dot 20 of the semiconductor layer in the concavity. The concavity is formed in the semiconductor substrate by forming the oxide dot in the surface of the semiconductor substrate and removing the oxide, whereby the concavity can be formed precisely in a prescribed position and in a prescribed size. The quantum dot is grown in such a concavity, whereby the quantum dot can have good quality and can be formed in a prescribed position and in a prescribed size.

Abstract: A breathable composite sheet material, a method for making such a sheet material, and an absorbent article utilizing the sheet material are provided. The composite sheet material is comprised of a thermoplastic film adhered directly to a fibrous substrate. The thermoplastic film comprises at least 50% by weight of a polymer material from the group of block copolyether esters, block copolyether amides and polyurethanes. The substrate comprises a fibrous web of at least 50% by weight of polyolefin polymer synthetic fibers. The composite sheet exhibits a peel strength of at least 0.1 N/cm, a dynamic fluid transmission of less than about 0.75 g/m2 when subjected to an impact energy of about 2400 joules/m2, and a moisture vapor transmission rate, according to the desiccant method, of at least 1500 g/m2/24 hr.

Abstract: Objects of the present invention are to provide a low-temperature co-fired ceramic material having a coefficient of linear thermal expansion controlled and has a high dielectric constant, and to reduce the warpage of a fired product even if it has an unsymmetrical lamination structure in a multilayer wiring board in which glass-ceramic mixed layers of different compositions are laminated. A low-temperature co-fired ceramic material in accordance with the present invention includes: SiO2—B2O3—Al2O3— alkaline earth metal oxide based glass, alumina, titania, and cordierite; glass, titania, and cordierite; or glass, titania, and mullite. When a multilayer wiring board is made of the low-temperature co-fired ceramic material, the content of cordierite or mullite of the substrate material is adjusted to control a difference in a coefficient of linear thermal expansion between the layers of the substrate material to not more than 0.25×10?6/° C.

Abstract: A method for producing an ?-alumina particulate is described. The method for producing an ?-alumina particulate comprises steps of (Ia) and (Ib), or a step of (II): (Ia) removing water from a mixture containing water, a seed crystal and a hydrolysate obtained by hydrolysis of an aluminum compound under conditions of a pH of 5 or less and a temperature of 60° C. or less, (Ib) calcining the resulted powder, (II) calcining a mixed powder containing 75-1 wt % of an ?-alumina precursor (in terms of Al2O3) and 25-99 wt % of a seed crystal (in terms of oxide of metal component).

Abstract: A transalkylation process for reacting carbon number nine aromatics with toluene to form carbon number eight aromatics such as para-xylene is herein disclosed. The process is based on the discovery that deactivating contaminants present in typical hydrocarbon feeds, such as chlorides, can be removed with an alumina guard bed prior to contacting with a transalkylation catalyst. Effective transalkylation catalysts have a solid-acid component such as mordenite, and a metal component such as rhenium. The invention is embodied in a process, a catalyst system, and an apparatus. The invention provides for longer catalyst cycle life when processing aromatics under commercial transalkylation conditions.

Abstract: The present invention relates to an adduct comprising MgCl2, an alcohol (ROH) in which R is a C1-C10 hydrocarbon group, and a compound containing a transition metal M selected from the Groups 3 to 11 or the lanthanide or actinide groups of the Periodic Table of the Elements (new IUPAC version) in an amount such as to give a weight of M atoms lower than 10% based on the total weight of the adduct. The catalyst components that are obtained by reacting the adducts with halogenating agents show very high specific activity.

Abstract: A highly active alpha-olefin polymerization catalyst component is disclosed. In the presence of a co-catalyst, the catalyst component is useful for the production of LLDPE resins. The catalyst component is produced by a method whereby organic silicon compounds are reacted with a transition metal complex and active transition metal species is deposited on a silicon-containing MgCl2 that is prepared in situ in the presence of the organic silicon compounds.

Abstract: Metallic catalysts of the general formula (I) and their precursors, suitable for chemo- regio- and stereoselective reactions, derived from ortho-bis-(1-phospholanyl)-heteroarenes.

Abstract: Processes for preparing a composition comprising (i) an acidic metal oxide containing substantially no zeolite, (ii) an alkali metal, alkaline earth metal, and mixtures thereof, and (iii) an oxygen storage component are disclosed. Preferably, the process comprise forming a single slurry of components (i)–(iii), spray drying and calcining to obtain metal oxide particles comprising components (i)–(iii). Preferably, the slurry comprise a base peptized acidic metal oxide containing slurry wherein the component (ii) is provided in the slurry as a metal of the base. Compositions prepared are impregnated with a noble metal to provide compositions useful to reduce gas phase reduced nitrogen species and NOx in an effluent off gas of a fluid catalytic cracking regenerator.

Abstract: In an exhaust gas purification catalyst comprising a honeycomb support and a catalytic layer that is formed on wall surfaces of each cell of the honeycomb support and contains active alumina and a mixed oxide containing Ce, Zr and Nd and doped with catalytic precious metal, the mixed oxide has a CeO2/ZrO2 mass ratio of 1.4 or more and the ratio of Nd2O3/(CeO2+ZrO2+Nd2O3) in the mixed oxide is 20 mass % or less.

Abstract: A catalyst for the hydrogenation of C4-dicarboxylic acids and/or derivatives thereof, preferably maleic anhydride, in the gas phase comprises a) 20-94% by weight of copper oxide (CuO), preferably 40-92% by weight of CuO, in particular 60-90% by weight of CuO, and b) 0.005-5% by weight, preferably 0.01-3% by weight, in particular 0.05-2% by weight, palladium and/or a palladium compound (calculated as metallic palladium) and c) 2-79.995% by weight, preferably 5-59.99% by weight, in particular 8-39.95% by weight, of an oxidic support selected from the group consisting of the oxides of Al, Si, Zn, La, Ce, the elements of groups IIIA to VIIIA and of groups IA and IIA of the Periodic Table of the Elements.

Abstract: A substantially light-insensitive thermographic recording material comprising a support and a thermosensitive element, the thermosensitive element containing a substantially light-insensitive organic silver salt, an organic reducing agent therefor in thermal working relationship therewith, a binder and at least one compound selected from the group consisting of mono-alkyl tetrachloro-phthalates, di-alkyl tetrachlorophthalates and N-(tetrachloro-phthalimyl)n-alkanes, wherein n is an integer greater than or equal to 1.

Abstract: The present invention provides a thermal recording material, which is easy to manufacture and has excellent productivity, water resistance, heat resistance (running stability) and chemical resistance, by solving various problems caused by using a crosslinking agent for a protective layer. The thermal recording material of the present invention comprises a protective layer mainly composed of a resin emulsion (a) comprising a copolymer resin emulsion (b) containing (meth)acrylonitrile and a vinyl monomer copolymerizable therewith, and having an SP value (solubility parameter) of 12.0 or more, a glass transition temperature (Tg) of 10 to 70° C., and a minimum film-forming temperature (MFT) of 5° C. or less, and a polyolefin copolymer resin emulsion (c).

Abstract: An aqueous composition suitable for applying insecticides or acaricides to plant propagation materials comprising water, an insecticidally or acaricidally effective amount of at least one nitroimino- or nitroguanidino-compound in free form or in agrochemically useful salt form and a blend of the following components, by weight: a) 2-10% of a surface-active agent comprising a1) at least one anionic surfactant; b) 4-20% of at least one inorganic solid carrier; and c) 3-25% of at least one antifreeze agent. In one embodiment, the aqueous composition further comprises a fungicidally effective amount of at least one fungicidally active compound. The inventive composition is storage stable, ready-to-apply (RTA), ecologically and toxicologically favorable and has good fungicidal efficacy.

Abstract: The present invention relates to novel 3-biphenyl-substituted, 3-substituted 4-keto-lactams and -lactones of the formula (I) in which A, B, Q, G, W, X, Y and Z are as defined in the disclosure, to processes for their preparation, and to their use as pesticides and/or microbicides and/or herbicides.

Abstract: A signal switching device is disclosed that is capable of transmitting signals with less signal loss while securing a good isolation characteristic. The signal switching device includes a first section formed from a superconducting material connected to a first transmission path. The first section has a smaller cross section at the input end than at the output end or, the signal switching device may include a first section formed from a superconducting material connected to a first transmission path in series, and a second section formed from a superconducting material connected to a second transmission path in parallel. The cross section of the second section is smaller than that of the second transmission path. The length of the second transmission path is determined in such a way that an input impedance of the second transmission path is sufficiently large when the second section is in a superconducting state.