Abstract: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure of the semiconductor device. The failure analyzer 13 has an analysis region setter for comparing an intensity distribution in the failure observed image with a predetermined intensity threshold to extract a reaction region arising from a failure, and for setting an analysis region used in the failure analysis of the semiconductor device, in correspondence to the reaction region. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.

Abstract: The edges of the reticle are detected with respect to the microstructured patterns exposed by the stepper, and the shapes of the microstructured patterns at the surface and at the bottom of the photoresist are detected. The microstructured patterns are evaluated by calculating, and displaying on the screen, the dislocation vector that represents the relationship in position between the detected patterns on the surface and at the bottom of the photoresist. Furthermore, dislocation vectors between the microstructured patterns at multiple positions in a single-chip or single-shot area or on one wafer are likewise calculated, then the sizes and distribution status of the dislocation vectors at each such position are categorized as characteristic quantities, and the corresponding tendencies are analyzed. Thus, stepper or wafer abnormality is detected.

Abstract: The present invention provides a probe card that can examine an object with small electrode spacing. A probe supporting plate is provided to a lower face side of a printed wiring board of a probe card. A plurality of probes are supported by the probe supporting plate. The probes comprise an upper contact, a lower contact, and a main body portion. An upper end portion of the upper contact protrudes toward an upper side of the probe supporting plate and contacts a terminal of the printed wiring board. A lower end portion of the lower contact protrudes toward a lower side of the probe supporting plate. On the probe supporting plate, a through-hole and a concave portion are formed to lock the probes, and the probes can be inserted and removed freely against the probe supporting plate from above.

Abstract: The present invention provides a probe card that can examine an object with small electrode spacing. A probe supporting plate is provided to a lower face side of a printed wiring board of a probe card. A plurality of probes are supported by the probe supporting plate. The probes comprise an upper contact, a lower contact, and a main body portion. An upper end portion of the upper contact protrudes toward an upper side of the probe supporting plate and contacts a terminal of the printed wiring board. A lower end portion of the lower contact protrudes toward a lower side of the probe supporting plate. On the probe supporting plate, a through-hole and a concave portion are formed to lock the probes, and the probes can be inserted and removed freely against the probe supporting plate from above.

Abstract: A probe station includes a fully guarded chuck assembly and connector mechanism for increasing sensitivity to low-level currents while reducing settling times. The chuck assembly includes a wafer-supporting first chuck element surrounded by a second chuck element having a lower component, skirting component and upper component each with a surface portion extending opposite the first element for guarding thereof. The connector mechanism is so connected to the second chuck element as to enable, during low-level current measurements, the potential on each component to follow that on the first chuck element as measured relative to an outer shielding enclosure surrounding each element. Leakage current from the first chuck element is thus reduced to virtually zero, hence enabling increased current sensitivity, and the reduced capacitance thus provided by the second chuck element decreases charging periods, hence reducing settling times.

Abstract: Some embodiments of a method and apparatus to facilitate battery management using a hall-effect sensor. The apparatus includes a hall-effect sensor and a battery management unit. The hall-effect sensor is disposed near the electrical transmission line to detect an amount of current flowing through the electrical transmission line. The current originates from a direct current power source coupled to the transmission line. The power source management unit is coupled to the hall-effect sensor to process a sensor signal from the hall-effect sensor. The power source management unit also determines the amount of current flowing through the electrical transmission line. Other embodiments are described.

Abstract: A micro-spray cooling system beneficial for use in testers of electrically stimulated integrated circuit chips is disclosed. The system includes micro-spray heads disposed about a probe head, which provide a coolant flow onto the IC. A flow inducing injector is provided that directs a fluid jet onto zones where stagnation of the coolant flow is present. This reduces or eliminates any stagnation points and enhance temperature uniformity over the area of the IC.

Abstract: A method and system for probing with electrical test signals on an integrated circuit specimen using a high resolution microscope positioned for observing a surface of the specimen exposing electrically conductive terminals thereon. A housing is provided with a carrier therein for supporting the specimen in relation to the microscope and a probe assembly is positionable on the surface of the specimen for conveying and acquiring electrical test signals to and from the specimen. A drive system is provided for shifting at least one of the probe and the carrier to a predetermined test position. In one form the system has a heat shield for protecting one of the probe assembly and the carrier from heat energy generated upon operation of the drive system, and in another form, the system has an environmental control for maintaining a desired temperature within the housing so that accurate measurements may be taken from the specimen.

Abstract: A method and circuit for adjusting packaged device output characteristics without dedicated pads or pins are disclosed. As opposed to multiple bit selection for the purpose of trimming, the method utilizes an iterative and dynamic means to trim the bits of a built-in trimming network such as an impedance network one bit at a time. Trim time will be short because each single loop trim cycle is very short. The method is robust and not overly complicated thus may be implemented very practically. The system is dynamic in nature because the operation of the device to be trimmed need not be changed from one mode to another.

Abstract: A composite substrate for testing semiconductor devices is formed by selecting a plurality of substantially identical individual substrates, cutting a corner from at least some of the individual substrates in accordance with their position in a final array configuration, and then assembling the individual substrates into the final array configuration. The final array configuration of substrates with corners cut or sawed away conforms more closely to the surface area of a wafer being tested, and can easily fit within space limits of a test environment.

Abstract: An integrated circuit is provided. The integrated circuit includes an RFID tag configured to store various administrative information after testing at a wafer level in response to a radio frequency signal, and an interface unit configured to perform the function of an interface between the integrated circuit and the RFID tag for storing the information in the RFID tag. An antenna of the RFID tag is formed using a wire and a lead frame. A method for writing information of an integrated circuit is also provided. The method includes the steps of performing a wafer processing of an integrated circuit having a RFID tag; performing a wafer level test of the integrated circuit; transmitting and receiving a radio frequency signal to store various administrative information in the RFID tag; and storing a chip confirmation code in the RFID tag.

Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.

Abstract: The present invention provides an inspection system with small increase in circuit area and capable of controlling increase in cost to be small. An inspection circuit intervenes between a first circuit and a second circuit. Further, the inspection circuit includes a signaling control portion and an inspection output portion. The signaling control portion controls signaling between the first circuit and the second circuit. Moreover, the inspection output portion outputs an output of the first circuit for inspection through the inspection circuit. In the present invention, the signaling control portion and the inspection output portion share a part of the circuit to realize their own function. Further, the first circuit, the second circuit and the inspection circuit are formed on the same substrate. The inspection circuit switches between the signaling control portion and the inspection output portion to use.

Abstract: Patterns for detecting displacement at probing occupying a small area are provided and are capable of detecting the direction of the displacement when a needle is displaced in probing. The patterns for detecting displacement at probing are arranged in pairs in a scribe region adjacent to IC chips, the pattern for detecting displacement at probing is formed of an inner conductor and an outer conductor arranged at a minute distance from the inner conductor which are concentrically formed, and the outer conductor is divided into a plurality of parts.

Abstract: A liquid crystal display (LCD) capable of hiding a defective pixel and a hiding method thereof applicable for a display mode of a liquid crystal display screen are provided. The method comprises firstly providing a substrate, detecting and recording the address data of all defective pixel dots of the substrate, and interrupting the display signal of defective pixel dots in response to the address data of the defective pixel dots.

Abstract: The present invention is directed to bidirectional buffer with slew rate control in at least one direction. The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.

Abstract: An active terminator is configured with switches to select between terminating two lines for transmitting one differential signal pair or two single ended signals terminated in a pseudo-differential receiver. The receiver circuitry is configured with three differential comparators. One differential comparator receives both signal lines and other two differential comparators each receive one signal line and a reference voltage. The signal lines are terminated in a resistive voltage divider with electronic switches coupling the positive and ground voltages. The top and bottom nodes of the resistor divider in both terminators are cross-coupled with pass gates. In the pseudo-differential mode the pass gates are OFF and the electronic switches are ON with known resistances. In the differential mode, the electronic switches are OFF and the pass gates are ON with known resistances. The pass gate and switch resistances are sized with the resistors to insure a desired termination impedance.

Abstract: An input termination circuit includes a first and a second resistor each having a terminal respectively coupled to a first and a second input terminal of the input termination circuit, a first and a second transistor coupled in series between the first resistor and the second resistor, and a third transistor having two terminals respectively coupled to the control circuit and a node between the first and the second transistor. The gate of the third transistor is coupled to ground. The gates of the first and the second transistor are coupled to a control circuit that is adapted to provide a control signal to turn the first and the second transistor on or off.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: Aspects of a method and system for using one-time programmable (OTP) read-only memory (ROM) to configure chip usage features are presented. Aspects of the system may include a one time programmable (OTP) memory on a chip that is configured to enable control of access to on-chip functions provided by on-chip modules. The chip may enable conditional activation or deactivation of on-chip functions provided by the on-chip modules in response to reception of an external activation or deactivation request based on the contents of the configured OTP memory.

Abstract: Disclosed herein is a multiplexing circuit for decreasing the output delay time of an output signal. The multiplexing circuit includes multiplexing units and a multiplexing output unit. Each multiplexing unit is initialized in response to an initialization signal, and outputs an input signal as a selection output signal in response to a selection control signal. The multiplexing output unit performs a logic operation on selection output signals received from the multiplexing units and outputs a multiplexing output signal based on the results of this operation. Preferably, the initialization signal is shared by two of the multiplexing units, and the initialization signal which is input to one of the two multiplexing units is the selection control signal which in input to the other of the two multiplexing units.

Abstract: A circuit analyzes the configured status of cells with a magnetic layer system, resistance of which may be altered by magnetic field pulses, forming a first line branch with data cells arranged in series and a second line branch with configurable cells arranged in series. The circuit includes a difference amplifier for determining a voltage signal giving the difference voltage of the line branches. Also included in the circuit is a voltage shifter for shifting the voltage signal to a value other than 0 volts, such as an adder or subtractor. In addition, the circuit includes a comparator or window comparator, for the decision as to whether the voltage signal lies in a valid or forbidden range and an evaluation unit for evaluating a valid voltage signal and for output of a logical low or high signal.

Abstract: In normal operation, an internal circuit 4 operates in synchronism with a clock CK, so that switching operation of the output circuit 2 is performed based on inputted data and an output enable signal. At this point, an output from the internal circuit 4 to a three-state control circuit 3 is forcedly set by state control circuits 5 and 6, whereby different test operations are performed on the output circuit 2.

Abstract: An N-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-charges a pre-charged node high when the symmetric clock signal is low and opens an evaluation window when the pulsed clock signal goes high, and pulls the pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The output stage provides an output signal based on states of the pre-charged node and a second preliminary output node.

Abstract: A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-discharges a pre-discharged node low when the symmetric clock signal is high and opens an evaluation window when the pulsed clock signal goes low, and pulls the pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The output stage provides an output signal based on states of the pre-discharged node and a second preliminary output node.

Abstract: A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift the output signal concurrently with the sensing operation. The sense amplifier includes a pair of differential cross-coupled inverters whose inputs are coupled to receive the data from the memory. Once the input nodes of the cross-coupled inverters are charged, the cross-coupled inverters are further coupled to pull-up and pull-down circuits that span the higher voltage range for performing the level-shifting functionality. In order to recondition the sense amplifier for a subsequent sensing process, a clamp circuit shorts the level-shifted outputs together to prevent a higher voltage level from being inadvertently passed to the memory device when isolating pass gates are reactivated.

Abstract: A liquid crystal display backlight inverter including a first error amplifying unit receiving and comparing a first detection voltage corresponding to a current flowing through a lamp with a first preset reference voltage and outputting a first error voltage corresponding to an error therebetween; a second error amplifying unit receiving and comparing a second detection voltage corresponding to a voltage applied to the lamp with a second preset reference voltage and outputting a second error voltage corresponding to an error therebetween; a feedback selector selecting one of the outputs of the first and second error amplifying unit according to an error between the second detection voltage and a third preset reference voltage; and a lamp control pulse generator generating a pulse signal having a duty controlled according to one of the first error voltage and second error voltage.

Abstract: A LCD backlight inverter including: a dimming control unit comparing a level of a triangle wave with a level of a dimming control signal and controlling a dimming control current to be supplied or interrupted according to a comparison result; an error amplification unit having an input end to which a detection voltage corresponding to the dimming control current and a current flowing through a lamp are inputted, comparing the detection voltage with a predetermined reference voltage, and outputting an error voltage corresponding to a difference via an output end thereof, the output end working as a ground when the dimming control current is not inputted; and a time constant circuit unit comprising a resistor connected between the output end of the error amplification unit and a voltage source and a capacitor connected between the output end of the error amplification unit and a ground.

Abstract: According to one embodiment, a comparator circuit includes: a plurality of comparator elements connected in parallel between at least one input signal line and at least one output signal line, each of the comparator elements comparing at least one input potential on the at least one input signal line and outputting comparison result to the at least one output signal line; and a switching device capable of setting each of the comparator elements to either an operation state to compare the at least one input potential or a non-operation state not to compare the at least one input potential, the switching device switching the number of comparator elements which are set to the operation state.

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output in response to a low phase input level in the first clock output. For a limited period of time, a low phase output level is forced irrespective of the phase level of the first clock input signal. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.

Abstract: A waveform of the output signal having high reproducibility to an input signal is outputted from capacitive load. Even the driving device is configured as a switching amplifier and drives capacitive load. Reactive power can be reduced to perform low power consumption. Output signals V1a and V1b that an output signal Vcap1 across output terminals 50 and 51 of load C1 fed back to input terminals 9a and 9b are compared with an input signal Vin so that error between output signals V1a and V1b is detected. A first error suppression signal Vout1 is produced so as to suppress the detected error between signals. The proportion of a first duration T1 that electric power is supplied to the load C1 to a second duration T2 that no electric power is supplied and load C1 is floated is altered according to the first error suppression signal.

Abstract: Apparatus and methods for setting wakeup times in a communication device are disclosed where setting the wakeup times includes estimating the lock on time of a frequency synthesizer in order to minimize the wakeup time and extend sleep times for maximal energy savings. A disclosed apparatus includes an estimator to receive a current lock on time of a frequency synthesizer, which is the time taken by the frequency synthesizer to lock on to particular frequency after a wakeup signal has been issued to turn on the synthesizer after a sleep period. The estimator calculates a latest estimated lock on time based at least on the current lock on time of the frequency synthesizer and determines an enable signal timing information based on the estimated lock on time. The apparatus also includes a timer configured to receive the enable signal timing information and issue at least one enable signal to turn on other circuitry in the transceiver after the synthesizer lock on period based thereon.

Abstract: A circuit and method for slew rate control is described. The circuit for slew rate control comprises a slew rate control circuit and an output buffer. The slew rate control circuit controls the rising slew rate and falling slew rate of an output voltage signal. The output buffer stabilizes the output voltage signal.

Abstract: The present invention discloses a PWM integrated circuit which may receive a programming signal without any extra pin. The PWM integrated circuit comprises: a comparator having two outputs; two pins respectively electrically connected with the two outputs; and a programming unit electrically connected with at least one of the two pins for setting a parameter inside the PWM integrated circuit. The two pins of the PWM integrated circuit may be used to respectively control a control switch and a synchronous switch, constituting a PWM circuit for generating PWM signals.

Abstract: A duty cycle correction circuit capable of generating a clock signal having good (e.g., approximately 50%) duty cycle is described. The duty cycle correction circuit includes a clock deskew circuit and a duty cycle detection circuit. The clock deskew circuit receives an input clock signal that may have poor duty cycle, adjusts the input clock signal based on a control, and provides an output clock signal having an adjustable duty cycle. The duty cycle detection circuit detects error in the duty cycle of the output clock signal and generates the control in response to the detected error in the duty cycle. The clock deskew circuit and the duty cycle detection circuit implement a feedback loop that senses error in the duty cycle of the output clock signal and feeds back the control to correct the duty cycle error.

Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Abstract: The present invention discloses a reset method for a digital circuit. The method includes: providing a clock signal to the digital circuit; keeping the clock signal at a logic level according to a first indicating signal; generating a reset signal for resetting the digital circuit; and recovering the clock signal to the digital circuit according to a second indicating signal.

Abstract: A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.

Abstract: In a clear period, transistors NT38 and PT38 turn on and state retention nodes HQ and H/Q are cleared to an L level and an H level, respectively. In this clear period, a transistor NT21 is off. Consequently, a precharge node PS maintains itself at an H level. Thus, transistors PT31 and NT32 are off, thereby preventing a short circuit from occurring in a clear period. A short circuit is also prevented from occurring in a preset period.

Abstract: A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level shifter circuit comprise a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially pull-up and pull-down sub-circuits to generate a positive feedback loop; an output node coupled to a shared node between the first pull-up and pull-down sub-circuits through an output inverter; a pull-up NMOS transistor with a gate contact coupled to the input of the second set, a source contact coupled to an input of the output inverter and a drain contact coupled to the output voltage of the level shifter circuit; and a pull-down NMOS transistor with a gate contact coupled to the input of the second set, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.

Abstract: The present invention discloses a level shift circuit which comprises: level shift means for receiving an input of a first operational voltage and generating an output of a second operational voltage; and a current path connecting with a source of the second operational voltage and providing current to the output of the level shift means to speed up output level switching. The circuit preferably further comprises a power consumption control circuit for stopping excess power consumption when the output of the level shift means has substantially accomplished level switching.

Abstract: There are various mobile communication standards such as GSM, EDGE, and W-CDMA. For a GSM or EDGE system, a receiver must be configured to work with an IF signal with a center frequency and bandwidth of 200 KHz. For WCDMA system, the same receiver must be configured to work with an IF signal with a center frequency of 600 KHz to 1000 KHz and band width of 2000 KHz. Accordingly, a configurable frequency IF filter with the capability to operate with multiple standards is provided.

Abstract: An integrated circuit device for switching electrical loads that have an inductive component comprises at least one switching channel that includes a power stage with a power MOS transistor and a driver circuit for driving the gate of the power MOS transistor, the switching stage being configurable for use in either of a High Side configuration and a Low Side configuration.

Abstract: In one embodiment, the present invention includes a current mirror having an input bipolar device and an output bipolar device, a first MOSFET device to control a current in the input bipolar device, and a second MOSFET device to control a bias current to common base terminals of the input and output bipolar devices. An output stack may be coupled to the bipolar output device, and may include at least one output MOSFET device.

Abstract: A current mirror arrangement is specified in which two current mirror transistors (2, 3) form a current mirror. Two cascode transistors (11, 12) are connected up to the two current mirror transistors (2, 3) to form a cascode stage. The cascode transistors (11, 12) in each case comprise a plurality of partial transistors (13, 14, 15; 16, 17, 18) connected up to one another in series with respect to their controlled paths. As a result it is possible to connect the connecting node of the current mirror transistors to a connecting node between two partial transistors (14, 15). This in turn brings about an increase in the input voltage range for a current source (4) that provides an input current for the current mirror.

Abstract: The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-noise ratio. One embodiment includes a switched capacitor amplifier comprising a CMOS amplifier, a feed-in switched capacitor, and a feedback switched capacitor. The feed-in switched capacitor couples an input signal to the non-inverting input of the CMOS amplifier. Similarly, the feedback switched capacitor couples the amplifier output to the non-inverting input to create a positive feedback loop. A capacitance of the feedback switched capacitor relative to a capacitance of the feed-in switched capacitor comprises a feedback proportion.

Abstract: A linear power amplifier filters an instantaneous input signal to generate a filtered input signal, combines the instantaneous input signal and filtered input signal to generate a modified drain source voltage waveform and modulates a switched mode power supply to the linear power amplifier in accordance with the modified waveform.

Abstract: A circuit and a method for controlling the power mode of a class-D amplifier are provided. The power mode control circuit comprises an amplitude detector and a duration detector. The amplitude detector provides an amplitude signal according to the absolute signal level of an input signal. The duration detector provides a shut-down signal to a switching control circuit of a class-D amplifier according to the length of the time period in which the amplitude signal is at a predetermined state, wherein the switching control circuit is turned on or turned off in response to the shut-down signal.

Abstract: The present invention provides an inexpensive radio frequency switching circuit having desirable radio frequency characteristics over a wide band and desirable endurance against the inflow of a high voltage signal such as an electrostatic surge. Either a negative bias voltage or a positive bias voltage being greater than or equal to 0V and less than or equal to a Schottky forward voltage is used for the control terminals V11 and V12 for controlling FETs 11 to 18 and FETs 21 to 28 so as to turn ON/OFF the path extending from the first input/output terminal P11 to the second input/output terminal P12 and the path extending from the first input/output terminal P11 to the third input/output terminal P13. Thus, it is possible to eliminate the need for DC cut capacitors.

Abstract: A low-noise amplifier, that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance, is shown. The multiple transformer topology permits negative and positive feedback to be applied constructively, allowing for a stable design with adequate gain and large reverse isolation without Noise Figure degradation.