Abstract: A storage device includes a storage element having first and second terminals that cause a first electrical characteristic change when an electric signal of a first threshold level or higher is applied and that cause a second electrical characteristic change, which is asymmetrical to the first electrical characteristic change, when an electric signal of a second threshold level or higher, the polarity of the electric signal of the second threshold level or higher being different from the polarity of the electric signal of the first threshold level or higher, is applied; and a unipolar transistor connected in series with the storage element. One of the first terminal and the second terminal of the storage element is electrically connected to the unipolar transistor. The unipolar transistor has a negative polarity or a positive polarity in accordance with the first terminal or the second terminal electrically connected to the unipolar transistor.

Abstract: A memory pumping circuit is proposed. The feature of the present invention is the charging capacitor of the pumping circuit is a DRAM cell for enhancing the capacitance.

Abstract: A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.

Abstract: A memory device using a nanotube cell comprises a plurality of nanotube sub-cell arrays each having a hierarchical bit line structure including a main bit line and a sub-bit line. In the memory device, a nanotube cell array comprising a capacitor and a PNPN nanotube switch which does not require an additional gate control signal is located between a word line and the sub-bit line, so that a cross point cell array is embodied to reduce the whole chip size.

Abstract: A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact probe can include a silicon core having a conductive coating. Contact probes in accordance with the present invention can be applied to a phase change media, for example, to form an indicia in the phase change media by changing the electrical resistivity of a portion of the phase change media.

Abstract: A memory circuit that retains stored data upon power down includes a volatile data storage circuit; and at least one nonvolatile memory coupled within the volatile data storage circuit, wherein the at least one nonvolatile memory includes a high resistive state and a low resistive state. The volatile data storage circuit can include cross-coupled inverters, cross-coupled NAND gates, or another volatile data storage circuit. The nonvolatile memories can include a spin-injection magnetic tunnel junction memory, a magnetic tunnel junction memory, a metal insulator phase change memory, an organic memory, or some other memory with two resistive states.

Abstract: To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.

Abstract: An electromechanical storage device includes an input element that facilitates the input of data, a series of data elements, and a terminating element that facilitates the reading out of data. The data elements each have at least two stable mechanical orientations, and these orientations can be utilized to store data. Data may be entered into the device by applying a transient electromagnetic pulse to the data elements. The device is constructed such that as a data bit is entered into the series of data elements, any data bits that have been previously entered into the series are shifted towards the terminating element.

Abstract: An advanced multi-bit magnetic random access memory device and a method for writing to the advanced multi-bit magnetic random access memory device. The magnetic memory includes one or more pair-cells. A pair-cell is two memory cells. Each memory cell has a magnetic multilayer structure. The structure includes a magnetically changeable ferromagnetic layer, a ferromagnetic reference layer having a non-changeable magnetization state, and a corresponding spacer layer separating the ferromagnetic layers. The memory cells are arranged such that an effective remnant magnetization of each of the cells is non-parallel from the cells' long-axis. This allows for more than one-bit to be stored as well as for efficient writing and reduced power consumption.

Abstract: Each of program cell and memory cells includes a magnetic storage portion of the same configuration. The program cell further includes a state change portion. That is, the program cell has the same structure as the memory cell, except that the state change portion is additionally provided thereto. As such, the program cell can be provided efficiently, as it can be designed the same as the memory cell in terms of the magnetic storage portion and others. The state change portion makes a transition to a fixed state based on an electrical change. Thus, the state change portion prevents program information from being rewritten by a magnetic noise or the like, and ensures stable storage of the program information.

Abstract: A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N? well. The N? well is in a P? type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N? well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N? well potential so that they remain reverse biased with respect to the N? well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N? well forms a second gate for the dual gate PMOS transistor since the potential of the N? well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible.

Abstract: A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode.

Abstract: A method for reading a NAND flash memory device having plural normal cells, which utilizes plural reference bit lines associated with plural reference cells to read the normal cells in one phase to reduce the read time, is disclosed. The method comprises ramping up a selected word line voltage in a predetermined period and reading the normal cells with a zero state, a first state, a second state and a third state in the predetermined period. The present invention also discloses a memory cell array concerning the method for reading a NAND flash memory device.

Abstract: An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance read port can acquire and transmit the logic state stored by the memory cell to another subsystem. The full pass gate can be implemented by connecting a P type metal semiconductor field effect transistor (PMOS) in parallel with an NMOS device and driving the gates of the transistors with a differential signal. When a write operation requires a current to flow in a first direction, the PMOS device provides a negligible voltage drop, and when the write operation requires current to flow in a second or the opposite direction, the NMOS device can provide a negligible voltage.

Abstract: A non-volatile memory device and drive method thereof uses a voltage bias condition to enable an electronic device to normally operate without employing a specific transistor, e.g., a recall transistor. The non-volatile memory device performs its function normally without the recall transistor, and by which a degree of cell integration can be considerably raised. A SRAM latch is controlled by the logic circuit, a SONOS (silicon-oxide-nitride-oxide-silicon) transistor is electrically connected to a Vcc node of the electronic device to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power, and a pass transistor controls read, program, and erase operations of the SONOS transistor.

Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

Abstract: Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively preventing testing of the respective memory block coupled thereto when that memory block is a known defective block. A non-volatile latch may also be coupled to each of the memory blocks for permanently preventing access, during normal operation of the memory device, to the respective memory block coupled thereto when that memory block is a known defective block.

Abstract: Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively preventing testing of the respective memory block coupled thereto when that memory block is a known defective block. A non-volatile latch may also be coupled to each of the memory blocks for permanently preventing access, during normal operation of the memory device, to the respective memory block coupled thereto when that memory block is a known defective block.

Abstract: A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell.

Abstract: A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

Abstract: An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor is coupled to a power supply ground. A gate of the first transistor is further coupled to a source of the first transistor. A second transistor is coupled in series with a memory cell with a source of the second transistor coupled to a positive power supply voltage and a gate of the second transistor is coupled to the drain of the first transistor.

Abstract: A flash memory device, such as a NAND flash, is included having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block. Methods for pre-charging word lines in unselected array blocks are included.

Abstract: A nonvolatile latch includes a memory element for storing an input data value. A write protect element is coupled to the memory element for utilizing a write protect signal to ensure the input data value stored by the memory element remains during a loss of a supply voltage to the latch.

Abstract: A non-volatile memory device with a page buffer having dual registers includes a memory cell array, a selector circuit and a page buffer circuit, the selector circuit being coupled to an exterior data line, the page buffer circuit including a first register and a second register being coupled between the memory cell array and the selector circuit, and the first register and second register being commonly coupled through a sense node. The first and second registers alternately write data to the memory cell array for programming. As one of the first and second registers performs programming, the other register stores data from the data line concurrently. In other words, the second register stores data from the data line when the first register is in programming, whereas the first register stores data from the data line when the second register is in programming.

Abstract: In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that can prevent the destructive read operation. In this state, after a word line is activated and a period in which the voltage is sufficiently discharged via a storage element which is in a low resistance state elapses (first read out), charge sharing is performed between the bit line and a read bit line of a sense amplifier which is precharged to a high voltage, and a read-out operation is performed again (second read out). Consequently, the read-out signal amount can be increased while suppressing the read current.

Abstract: A memory cell array has memory cells arranged in a matrix form. The memory cell includes a floating gate and a control gate. Word lines are each coupled to the control gates of the memory cells which are arranged on a corresponding one of the rows in the memory cell array. Bit lines are each coupled to drains of the memory cells which are arranged on a corresponding one of the columns in the memory cell array. An external voltage is supplied from the exterior to an external voltage input terminal. A first voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the word line coupled to the control gates. A second voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the bit line coupled to the drains.

Abstract: A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.

Abstract: A memory device has a memory array for storing memory data, a conditioning data storage unit for storing conditioning data, and data lines for transferring data. During a memory operation, the memory device transfers both of the condition data and the memory data to the same data lines at different time intervals. The condition data is transferred at one time interval. The memory data is transferred at another time interval. Transferring the conditioning data to the data lines improves the accuracy of the transfer of the memory data at the data lines.

Abstract: A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying the signal by a delay that is determined by a delay control signal. A selection circuit couples either the reference clock signal or the delayed clock signal to the input of the voltage controlled delay circuit. When the reference clock signal is coupled to the input of the voltage controlled delay circuit, the clock generating circuit functions as a delay-lock loop. When the delayed clock signal is coupled to the input of the voltage controlled delay circuit, the voltage controlled delay circuit operates as a ring oscillator so that the clock generating circuit functions as a phase-lock loop.

Abstract: A redundancy circuit and repair method for a semiconductor memory device. The redundancy circuit comprises an address buffer for outputting a first internal address and a second internal address (used only during redundancy programming to carry failed memory addresses) based on an external address; and address storage and comparison units, each one of the address storage and comparison units being selected for programming using the second internal address. The address storage and comparison units comprise ferroelectric storage cells that store the address of a defective (failed) main memory cell and outputs a redundancy decoder enable signal in response to a first internal address matching the stored (second internal) address. Accordingly, the redundancy circuit with ferroelectric storage cells and a repair method allows the performance of a second repair when a defective cell is detected after a first repair or after a packaging process.

Abstract: A semiconductor memory device and multi-row address test method reduce the time it takes to perform the multi-row address test. The semiconductor memory device comprises normal memory cell blocks, which can include normal memory cells and spare cells that replace defective cells. The device also includes a redundancy signal generator to output a redundancy signal indicating whether any memory cell blocks include defective cells and address signals of repair word lines corresponding to the defective cells. A redundancy signal decoder decodes the redundancy signal and the address signals of the repair word lines and outputs word line enable signals, and word line drivers that do not enable the repair word lines, but selectively enable the normal word lines in response to the word line enable signals.

Abstract: A device including a command decoder to receive a compound command, a timer to begin operating if the compound command includes an activate command and a precharge command, the timer to begin operating at substantially the same time as the activate command is issued, and control logic coupled to the command decoder to precharge bit lines no earlier than when the timer reaches a target time period.

Abstract: An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell field region, and for connecting/disconnecting the sense amplifier to/from from a bit line of a second cell field region, as a function of the state of control signals applied at control lines. Driver devices drive the control signal. Additional switches change the state of the control signals.

Abstract: A sense amplifier circuit for sensing a logic state of a selected memory cell in a memory circuit includes a precharge circuit and a latch circuit. The precharge circuit is adapted for connection to a pair of complementary bit lines corresponding to the selected memory cell and is operative to selectively drive the pair of complementary bit lines to a first voltage in response to a first control signal. The latch circuit is adapted for connection to the pair of complementary bit lines. The sense amplifier circuit further includes a replication circuit adapted for connection to the pair of complementary bit lines. The replication circuit is operative to selectively transfer a voltage representative of a logic state on a first bit line of the pair of complementary bit lines to a second bit line of the pair of complementary bit lines in response to at least a second control signal.

Abstract: A semiconductor memory device includes an IO circuit for receiving or outputting command signals, address signals and data which are serialized and an IO signal control circuit for parallel converting the serialized command signals, address signals and data inputted through the IO circuit and applying the parallel converted signals to an internal portion and serial converting parallel data applied from the internal portion and outputting the serial converted data to the IO circuit.

Abstract: A refresh control circuit is provide for a pseudo SRAM that includes a plurality of banks. The refresh control circuit includes a buffer enable control unit that outputs a chip select internal control signal, and a bank selection unit that generates a single bank select signal or an all-bank select signal in response to the chip select internal control signal. The single bank select signal is enabled in an active operation to perform a refresh operation on one bank and the all-bank select signal is enabled in a standby operation to perform a refresh operation on all the banks.

Abstract: A non-volatile magnetic memory device is proposed, which provides sufficient magnetic shielding performance for external magnetic fields. A first magnetic shield layer 60a and a second magnetic shield layer 60b, both made of a soft magnetic metal, are formed respectively on the bottom surface of the transistor section 20, which is the mounting side of the MRAM device 10, and on the top surface of the bit line 50, which is opposite to the bottom surface of the mounting side of the MRAM device 10. On the second magnetic shield layer 60a, a passivation film 70 is formed. The magnetic flux penetrated from the external magnetic field, is suppressed below the inversion strength of the MRAM device 10, thereby improving reliability.

Abstract: A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

Abstract: A semiconductor memory device is provided which comprises a group of address pads and an input circuit configured to receive a first address from the address pads at a first transition of an external clock signal and a second address from the address pads at a second transition of the external clock signal.

Abstract: A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured to variably delay the external clock signal in relation to the phase difference to generate an intermediate clock signal, a selection unit configured to select between the intermediate clock signal and an inverted version of the intermediate clock signal in relation to an inversion control signal, and to generate an internal clock signal according to the selection, and an inversion determination unit configured to generate the inversion control signal in relation to transition of the external clock signal within a duty error margin.

Abstract: Seismic data sets representative of a marine seismic streamer survey are constructed with test coverage holes in the data sets. The data sets are processed and data quality degradation in the processed data due to the test coverage holes is evaluated. Maximum acceptable coverage holes for the survey are determined from the evaluation of data quality degradation.

Abstract: An up-going wavefield and a down-going wavefield are calculated at a sensor position from a pressure sensor signal and a particle motion sensor signal. Then, an up-going wavefield is calculated at a water bottom position substantially without water bottom multiples from the up-going and down-going wavefields at the sensor position. In one embodiment, the up-going wavefield at the sensor position is backward propagated to the water bottom, resulting in an up-going wavefield at the water bottom. The down-going wavefield at the sensor position is forward propagated to the water bottom, resulting in a down-going wavefield at the water bottom. The up-going wavefield at the water bottom without water bottom multiples is calculated from the backward propagated up-going wavefield at the water bottom, the forward propagated down-going wavefield at the water bottom, and a reflection coefficient of the water bottom.

Abstract: A formation logging tool having a substantially continuous central mandrel with regularly spaced mass blocks disposed thereon, at least some of the mass blocks carrying sensors such as receivers. By adopting this structure, the tool can be made to behave as a mass-spring structure and its flexural and extensional behaviour controlled such that its dispersion curve does not extend into the dispersion curve of the formation to be logged. The structure can be applied to the whole of the logging tool or just to the receiver section and/or any spacer section between the receiver and the transmitter section.

Abstract: A method for obtaining an increased update rate in an indoor acoustic positioning system for determining the position of one or more identification tags, comprising transmitting from an identification tag an acoustic spread spectrum sequence that is unique to the identification tag, receiving the spread spectrum sequence in a detector unit and recording the arrival time of the spectrum sequence, and comparing the spectrum sequence with stored values of the spectrum sequences used by all the identification tags in the positioning system.

Abstract: The present invention is a medication reminder system and method for use with blister packs containing medications to be taken by a patient wherein the system alerts the patient when to take the medication contained in a particular blister. An audible alarm and a light indicate which blister is to be opened to remove the medication. The system comprises a case large enough to enclose a blister pack and has top and bottom halves that are releasably connected together. A circuit board comprising the electronics that operate the system is placed on top of the blister pack and is enclosed in the case along with the blister pack. Both the circuit board and the top case half have openings that allow the blisters of the pack to pass through. Openings on the bottom case half permit the medications in the blisters to be removed. The circuit board is programmable to set the time of an internal clock and to set up to four alarms a day when medications are to be taken.

Abstract: An educational alarm clock radio is provided that speaks a new word each day when the alarm goes off, the words each being stored in a memory cartridge as an individual increments of information in a sequential set of increments. When the alarm goes off, the word of the day, the definition of that word of the day and its use in a sentence are spoken via the audio portion of the device as the next information increment in the sequence. The word will also be displayed on a screen so the user can see the correct spelling of the word. The word may be replayed at any time during the day by activating a device control. Prior words may be displayed by energizing a reverse control. The entire sequence of previously played words, moreover, can be played in serial fashion through further activation of control or combination of controls. The device also serves as an alarm clock radio with alarm types such as wake by buzzer or radio as well as the wake by words function.

Abstract: The track jumping of a scanner on optical storage media in which information items are stored on groove and land tracks or which have not yet been written to is intended to be made possible in a reliable manner. For this purpose, firstly a fictitious track type is defined for a regulating circuit, which regulates the position of the scanner. The regulating circuit is then closed on the basis of the track type defined and a track scanning signal. The reaction of the scanner to the closing is detected in order to obtain from this an item of information about the track type. This method is also advantageous, in principle, for closing the track following regulation in information carriers having relatively high storage densities.

Abstract: An optical head device including a lens holder which holds an objective lens, six wires for supporting the lens holder and a holder support member which movably supports the lens holder by the six wires in a tracking, focusing and tilt direction. The six wires comprise two pairs, each of the pairs comprising a composite wire composed of two wires and a single wire composed of one wire which are respectively disposed on an upper side and a lower side of the lens holder in the focusing direction. The spring constant of the composite wire is set to be approximately equal to a spring constant of the single wire. Alternatively, the six wires may be disposed on the same circumference with respect to a drive center in the tilt direction or the spring constant of one wire of the pair may be set to be smaller than spring constants of the other two wires of the pair.

Abstract: A method for controlling long seeking operation in an optical disc drive is provided. The optical disc drive includes a sled actuator, a pickup head installed on the sled actuator for reading and/or writing data in an optical disc, and a controller for controlling the sled actuator to move together with the pickup head. The method includes the steps of (a) receiving remaining tracks information indicating a number of tracks remained to be crossed by the sled actuator and/or the pickup head; (b) receiving velocity information indicating a velocity of the sled actuator and/or the pickup head; (c) receiving acceleration information indicating an acceleration of the sled actuator and/or the pickup head; (d) driving the sled actuator to move according to the remaining tracks information, the velocity information, and the acceleration information.

Abstract: The invention pertains to an improvement for a tracking and focusing servo and defect management circuit that controls the tracking and focusing of an optical head on an optical media in an apparatus for reproducing a data, sound or image recorded on the optical media. The invention characterizes by the provision of a circuit for managing modulation of an RF signal from the optical pickup head caused when the optical pickup head encounters a non-continuous track in segment arrangement or a very long extended defect such as a extended flaw in the disc resulted discontinuous track segment thereon, and an adjusting circuit which manages the loop gain of the tracking servo circuit per the track arrangement of defect detection and a tracking profile, whereby the responsiveness of the optical pickup head is improved and track skipping prevented or recovered.