Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.

Abstract: A probe measurement system for measuring the electrical characteristics of integrated circuits or other microelectronic devices at high frequencies.

Abstract: A probe station for probing a test device has a chuck element for supporting the test device. An electrically conductive outer shield enclosure at least partially encloses such chuck element to provide EMI shielding therefor. An electrically conductive inner shield enclosure is interposed between and insulated from the outer shield enclosure and the chuck element, and at least partially encloses the chuck element.

Abstract: Systems and methods for testing packaged microelectronic devices are disclosed herein. One such system for testing a packaged microelectronic device includes a test socket configured to receive the device for testing and a tester interface including a plurality of test contacts aligned with external contacts of the device when the device is received within the test socket. The system further includes a mask proximate to the test socket and the test contacts. The mask includes a plurality of apertures arranged in a pattern corresponding to the plurality of test contacts and corresponding at least in part to the array of external contacts when the device is received within the test socket. The apertures include (a) first apertures sized to allow the corresponding test contacts to extend completely through the mask, and (b) one or more second apertures sized to allow the corresponding test contacts to extend only partially through the mask.

Abstract: According to an embodiment of a circuit substrate of the present invention, in a circuit substrate provided with a plurality of circuit blocks formed on a single substrate, at least one of the metal patterns connecting the circuit blocks is separated into two sections at some midpoint of wiring, and exposed conductor portions whose end portions are to be bridge-connected through soldering are provided at the end portions in the separated portion of the separated two wiring metal patterns.

Abstract: An apparatus for providing electrical pathways between one or more unsingulated integrated circuits and one or more test circuits external to the integrated circuits, includes a flexible substrate having a first major surface and a second major surface, a plurality of first contact structures disposed in a central portion of the first surface of the flexible substrate, a plurality of second contact structures disposed in a peripheral annular region of the first surface of the flexible substrate, and a plurality of first electrically conductive pathways, each of the plurality of first electrically conductive pathways coupled to a respective first and second contact structure, wherein the second surface is free from first contact structures, second contact structures, and first electrically conductive pathways.

Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.

Abstract: It is an object of the present invention to conduct highly reliable inspection by adjusting a contactor of a probe card and an inspection object in a prober to a parallel state even if the contactor and the inspection object become not parallel to each other. The present invention is a probe card mounted in a prober via a holder, the probe card including: a contactor; a circuit board electrically connected to the contactor; a reinforcing member reinforcing the circuit board; and a parallelism adjustment mechanism adjusting a degree of parallelism between the contactor and an inspection object disposed in the prober.

Abstract: For adjusting a positional relationship between a specimen and a probe to measure an electric characteristic of the specimen through a contact therebetween, a base table holding a specimen table holding the specimen and a probe holder holding the probe is positioned at a first position to measure the positional relationship between the probe and the specimen at the first position, and subsequently positioned at a second position to measure the positional relationship therebetween at the second position so that the probe and the specimen are contact each other at the second position, the specimen table and the probe holder are movable with respect to each other on the base table at each of the first and second positions to adjust the positional relationship between the probe and the specimen, and a measuring accuracy at the second position is superior to a measuring accuracy at the first position.

Abstract: A probing apparatus for integrated circuit devices comprises a probe card, a probe holder for holding the probe card, a test head and a temperature-adjusting mechanism. The probe card comprises at least one probe capable of forming an electrical connection with the integrated circuit device facing a first surface of the probe card, and the temperature-adjusting mechanism can be positioned on/above a second surface of the probe card. The temperature-adjusting mechanism can be positioned inside the probe card, inside the probe holder or on the probe holder. The test head comprises a plurality of pins configured to form electrical connections with connecting sites of the probe card and test and measurement units and apparatus. The temperature-adjusting mechanism can be positioned on or inside the test head. The temperature-adjusting mechanism comprises a flow line having at least one inlet and a plurality of outlets, and the outlets can be positioned on the second surface of the probe card.

Abstract: A spring probe having a barrel, plunger, spring and contact ring is provided in which the contact ring provides electrical contact between the plunger and the barrel. Two or more contact rings may be provided to improve the pointing accuracy of the probe.

Abstract: A contact probe includes a plurality of probes, each of the probes including: an conductive tube; an conductive plunger, contained in at least one end side of the tube, and having a distal end part protruding outward from the tube in an axial direction of the tube; and a coil spring, contained in the tube, and adapted to elastically urge the plunger outward. The plural probes are arranged in a first direction in a socket comprised of insulating material. A cross section of the tube in a direction perpendicular to the axial direction of the tube has a greater size in a direction different from the first direction than a size in the first direction.

Abstract: A program circuit activates a pass signal when a first program unit is programmed. The first program unit is programmed when a test of an internal circuit is passed. A mode setting circuit switches an operation mode to a normal operation mode or a test mode by external control. A state machine allows a partial circuit of the internal circuit to perform an unusual operation different from a normal operation when the pass signal is inactivated during the normal operation mode. By recognizing the unusual operation during the normal operation mode, it can be easily recognized that a semiconductor integrated circuit is bad. Since a failure can be recognized without shifting to the test mode, for example, a user who purchases the semiconductor integrated circuit can also easily recognize the failure.

Abstract: Microelectronic devices, methods for testing microelectronic devices, and detachable electrical components. One embodiment of an apparatus for testing microelectronic devices in accordance with the invention comprises a board having a primary side, a secondary side, a plurality of test sites at the primary side, and electrical lines electrically coupled to the test sites. The testing apparatus can further include a plurality of lead holes in the board. Individual lead holes have a sidewall and a conductive section plated onto the sidewall. In several embodiments, individual pairs of first and second lead holes are electrically coupled to electrical lines corresponding to an associated test site. The apparatus can further include a plurality of permanent fuses fixed to the board. Individual permanent fuses are electrically coupled to electrical lines associated with an individual test site and an individual pair of first and second lead holes.

Abstract: There is provided a threshold voltage control apparatus that controls a threshold voltage for a level comparing section that detects a logic pattern of an input signal by comparing a level of the input signal with the threshold voltage.

Abstract: The present invention provides a semiconductor device, including: a first semiconductor chip, and a second semiconductor chip connected to the first semiconductor chip through a plurality of bumps having not only a number of main bumps necessary for operation between the chips but also a predetermined number of measurement and control input bumps. Each of the first and second chips includes a plurality of measurement path switches individually connected to the main bumps, a plurality of current path switches connected to connecting points between the main bumps and the measurement path switches, and a control circuit for the measurement path switches, the first semiconductor chip further including a plurality of measurement and control terminals for inputting a control signal of the control circuit and supplying fixed current to be supplied to the current path switches and then measuring the voltage at the connecting points.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (?) which minimizes the standard deviation of the function F to be obtained (step ST1.

Abstract: A method of testing a liquid crystal display includes the steps of forming a plurality of chip positioning areas with a plurality of data connecting ends on a glass substrate, forming a plurality of data wires between two adjacent chip positioning areas which are linked to the plurality of data connecting ends of the two adjacent chip positioning areas, forming a testing circuit on each chip positioning area, which is linked to a predetermined amount of data connecting ends, and probing two testing circuits of two chip positioning areas to obtain an electrical parameter.

Abstract: The present invention relates to a module and method for detecting a defect of a thin film transistor (TFT) substrate, which can detect disconnection of a gate line of the TFT substrate having gate drivers provided with a dual structure in which the gate drivers are provided at both sides of the gate lines. There is provided a module and method for detecting a defect of a TFT substrate, wherein gate lines are separated into two portions by cutting a central region of the gate lines, gate power is supplied to the gate lines of which central portions are cut through gate drivers provided at both sides of the gate lines, and a signal of a negative voltage level is supplied to data lines, so that disconnection of the gate lines can be detected.

Abstract: There is provided a method that includes (a) determining a characteristic of a fundamental spectral component of a spectrum of a power spectrum of noise on a power line, and (b) determining a condition of the power line based on the characteristic.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

Abstract: In a gate driving circuit and a display apparatus having the same, a ripple preventing part is connected to a pull-up part and a control terminal (Q-node) to reset the Q-node. The ripple preventing part includes a first ripple preventing device that resets the Q-node during a high period of the first clock within a (n?1)H period, and a second ripple preventing device that resets the Q-node during a high period of a second clock within the (n?1)H period. A back-flow preventing device is connected between a previous carry node and the second ripple preventing device to prevent an electric charge of the Q-node from flowing back to the previous carry node.

Abstract: A transmission device transmits differential signals that are to be output, in the form of current signals via first and second output terminals. A first switching transistor and a first output transistor are serially connected between the grounded terminal, which is set to a fixed electric potential, and the first output terminal. A second switching transistor and a second output transistor are serially connected between the grounded terminal and the second output terminal. First and second bias transistors are provided in parallel with the first and second switching transistors, and generate a predetermined bias current. A pair of differential signals, which are to be transmitted, are input to the gates of the first and second switching transistors. The gates of the first and second output transistors are biased at a predetermined first voltage.

Abstract: An one-die termination includes: a code generator configured to generate a calibration code in response to a voltage of a first node and a reference voltage; a calibration resistor unit connected to the first node, and configured to be turned on and off in response to the calibration code; and a reference resistor unit coupled to the calibration resistor unit, and configured to be turned on and off in response to a control signal.

Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads.

Abstract: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group respectively, in which idle context data item is stored, connects storage elements of second group in series, loads context data item into second group whose storage elements are connected in series, connects first group and second group by connecting storage elements of first group to corresponding storage elements of second group respectively, and swaps context data items between first group and second group.

Abstract: A level shift circuit determining a logic value while preventing load capacitance from increasing. A voltage detector detects the states of first and second voltages and generates first and second detection signals. A first logic unit generates a first control signal having a level that is in accordance with an input signal or a level of a third voltage in response to the first detection signal. A second logic unit generates a second control signal having a level that is in accordance with the first control signal or a level of the second voltage in response to the second detection signal. A level converter generates an output signal based on the first and second control signals and clamps the output signal at a fixed level when an abnormality occurs in the first voltage.

Abstract: In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a pre-emphasis controller controls the pre-emphasis circuit. The pre-emphasis controller adjusts a pre-emphasis level of the pre-emphasis circuit to increase an amount of current supplied to the channel at a transition time of the input signal in accordance with the transition condition of the channel.

Abstract: An input buffer for an Ultradeep Sub Micron (UDSM) process which allows the UDSM process to interface with a 3V input. The input voltage is applied to a degenerated transistor which forms part of the input buffer. The input buffer effectively drops the input voltage to a voltage suitable for use by the core of the UDSM process.

Abstract: A drive circuit includes a load circuit, first and second series circuits, a bias circuit, and first and second voltage applying units. The load circuit is arranged between first and second nodes. The first series circuit is arranged between a first power supply node for supply of a first voltage and a second power supply node for supply of a second voltage. The first series circuit includes a first first-type transistor and a first second-type transistor connected in series with the first node therebetween. The second series circuit includes a second first-type transistor and a second second-type transistor connected in series with the second node therebetween. The bias circuit generates a first bias voltage to bias the first and second first-type transistors and generates a second bias voltage to bias the first and second second-type transistors. The first and second voltage applying units each include a plurality of switches.

Abstract: The buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an put/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Abstract: A domino circuit and method include a master evaluation node to which a master discharge path with a wide input AND gate is coupled and a virtual evaluation node to which an output stage and slave discharge path are coupled. A current mirror interconnects the master discharge path and the slave discharge path. The devices in the current mirror are sized so that current flowing in the master discharge path is amplified into the slave transmission path.

Abstract: Signal-integrity measurement systems and methods utilizing unique time-base generation techniques for controlling the sampling of one or more signals under test. A time-base generator made in accordance with the present disclosure includes a phase filter and modulation circuitry that generates a rapidly varying phase signal as a function of the output of a sigma-delta modulator. The phase filter filters unwanted high-frequency phase components from the rapidly varying phase signal. The filtered signal is used to clock one or more samplers so as to create sampling instances of the signal(s) under test. The sampling instances are then analyze using any one or more of a variety of techniques suited to the type of signal(s) under test.

Abstract: A sense amplifier-based latch is provided. It comprises an input circuit, a sense amplifier, a latch circuit and an output circuit. By employing the latch circuit, the variation frequency of an output signal and a complementary output signal as well as lots of charge consumption is reduced. Accordingly, the invention has less glitches and malfunctions, thus suitable for high-speed circuit applications.

Abstract: In an embodiment, a sense amplifier can perform a stable differential amplifying operation while having a high differential amplification gain. The sense amplifier comprises a current sense amplification unit, a voltage difference amplification unit, and an output stabilization unit. The current sense amplification unit receives differential input currents and generates differential output voltages corresponding to the differential input currents. The voltage difference amplification unit amplifies a voltage level difference between the differential output voltages through positive feedback using cross-coupled transistors. The output stabilization unit connects output stabilizing elements having a positive input resistance in parallel with the voltage difference amplification unit having a negative input resistance to stabilize the output of the voltage difference amplification unit.

Abstract: A comparator circuit for comparing a first voltage signal to a second voltage signal is described. The comparator circuit includes a first comparator and a second comparator and a selection unit for selecting one of the comparators depending on a selection condition. The invention also provides a method for operating a comparator circuit.

Abstract: A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.

Abstract: A comparator including an amplifier unit, a latch unit, and a switch unit is provided. The amplifier unit receives and gains an input signal pair respectively and then outputs an output signal pair. The latch unit is coupled to the amplifier unit. During a tracking period, the latch unit is not powered, and during a latching period, the latch unit is powered to latch the output signal pair and then output a logical signal pair accordingly. The switch unit is coupled between the amplifier unit and the latch unit. During the tracking period, the switch unit transfers the output signal pair to the latch unit, and during the latch period, the switch unit separates the amplifier unit from the latch unit, and thereby reducing the influences to the comparator caused by the kick back noise and the offset error.

Abstract: An abnormality detection circuit monitors a power supply voltage and, when the power supply voltage drops, outputs an abnormality detection signal of a predetermined level. The source of a detection transistor as a P-channel MOSFET is connected to a power supply line to which a power supply voltage to be monitored is applied. A detection resistor as an impedance element is provided between the drain of the detection transistor and a ground terminal. A capacitor is provided between the gate of the detection transistor and the ground terminal. A charging path is provided between the gate of the detection transistor and the power supply line. The abnormality detection circuit outputs a drain voltage of the detection transistor as an abnormality detection signal.

Abstract: A frequency synthesizer and method for synthesizing decimal frequencies. The synthesizer includes a seed generator, a clock synthesizer and an output synthesizer. The clock synthesizer includes a binary accumulator in a feedback signal path using a base reference frequency and a clock seed word for synthesizing a clock frequency and the output synthesizer includes a binary accumulator in a forward signal path using the clock frequency and an output seed word for synthesizing an output frequency. The output frequency is synthesized in decimal frequency steps from a decimal base reference frequency. Several output synthesizers may be driven in parallel from the same clock frequency for synthesizing several output frequencies in parallel.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: A CMOS Output Buffer providing controlled output impedance includes three internal sections each of which provides a impedance control for a corresponding region of the output V-I characteristics of deep linear, deep saturation and transition regions. Each internal section includes controlled current sinks/current sources enabled to provide a precise control over the DC impedance of the driver across the PAD voltage range.

Abstract: An output buffer circuit in a multi-power system operating at a high power supply voltage and a low power supply voltage includes a pre-driver, and a main driver. The pre-driver performs a differential switching operation on first and second differential input signals to output first and second differential output signals. The main driver performs a differential switching operation on the DC-eliminated and level-shifted first and second differential output signals to output third and fourth differential output signals. The main driver includes a differential switching circuit including first and second NMOS transistors, and performs a differential switching operation on the DC-eliminated and level-shifted first and second differential output signals to output the third and fourth differential output signals, and an equalizer coupled between source electrodes of the first and second NMOS transistors, and controls a bandwidth of the third and fourth differential output signals.

Abstract: A voltage generating circuit includes a voltage generating unit which generates plural constant voltages, plural switches, a control signal generating unit and a decoding circuit. The switches select any one of the plural constant voltages generated from the voltage generating unit and outputs it from a voltage output terminal. The control signal generating unit generates plural control signals which are switched between a high level and a low level through trimming on plural fuse resistors. The decoding circuit controls the state of connection of the switches-according to the control signals. The reference voltage Vx output from the voltage output terminal is applied to an electric-current generating resistor through an operational amplifier and a transistor to generate a constant electric current.

Abstract: A voltage/current converter circuit includes a bridge configuration having a first current path with a first resistor, a first transistor, and an input node to receive a ramp voltage to be converted, and a second current path with a second resistor and a second transistor. A current passes through the second current path. An amplifier arrangement balances the bridge configuration by providing an output signal to a control terminal of the first transistor and/or to a control terminal of the second transistor.

Abstract: An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. Further, when a plurality of phase comparators are disposed, in both cases where comparing phases all at once and comparing phases one after another, it is possible to complete the phase synchronization within a short time by making a delay amount variable.

Abstract: The present invention relates to an apparatus and a method thereof for generating a clock signal. The apparatus includes a clock generating module and at least one delay stage. The clock generating module receives a reference signal through a first signal path, receives a feedback signal through a second signal path, and provides a clock signal to a third signal path according to the reference signal, wherein the feedback signal corresponds to the clock signal. The at least one delay stage is located on at least one of the first, second, and third signal paths for providing a corresponding delay on the signal path at which the at least one delay stage is positioned.